FR2963982B1 - Procede de collage a basse temperature - Google Patents

Procede de collage a basse temperature

Info

Publication number
FR2963982B1
FR2963982B1 FR1056696A FR1056696A FR2963982B1 FR 2963982 B1 FR2963982 B1 FR 2963982B1 FR 1056696 A FR1056696 A FR 1056696A FR 1056696 A FR1056696 A FR 1056696A FR 2963982 B1 FR2963982 B1 FR 2963982B1
Authority
FR
France
Prior art keywords
bonding
substrate
annealing
temperature
low temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1056696A
Other languages
English (en)
Other versions
FR2963982A1 (fr
Inventor
Gweltaz Gaudin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1056696A priority Critical patent/FR2963982B1/fr
Priority to US12/904,744 priority patent/US8790992B2/en
Priority to TW100118741A priority patent/TWI459480B/zh
Priority to JP2011120794A priority patent/JP5555957B2/ja
Priority to DE102011076845.9A priority patent/DE102011076845B4/de
Priority to KR1020110065872A priority patent/KR101272675B1/ko
Priority to CN201610091145.6A priority patent/CN105742258B/zh
Priority to CN2011101994542A priority patent/CN102376653A/zh
Priority to SG2011059490A priority patent/SG178688A1/en
Publication of FR2963982A1 publication Critical patent/FR2963982A1/fr
Application granted granted Critical
Publication of FR2963982B1 publication Critical patent/FR2963982B1/fr
Priority to US14/334,370 priority patent/US9117686B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/036—Fusion bonding
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/27452—Chemical vapour deposition [CVD], e.g. laser CVD
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/276—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/2761—Physical or chemical etching
    • H01L2224/27616—Chemical mechanical polishing [CMP]
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    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2781—Cleaning, e.g. oxide removal step, desmearing
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
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    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
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    • H01L2224/29187—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
    • H01L2224/83014—Thermal cleaning, e.g. decomposition, sublimation
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
FR1056696A 2010-08-20 2010-08-20 Procede de collage a basse temperature Active FR2963982B1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FR1056696A FR2963982B1 (fr) 2010-08-20 2010-08-20 Procede de collage a basse temperature
US12/904,744 US8790992B2 (en) 2010-08-20 2010-10-14 Low-temperature bonding process
TW100118741A TWI459480B (zh) 2010-08-20 2011-05-27 低溫黏附製程
JP2011120794A JP5555957B2 (ja) 2010-08-20 2011-05-30 低温結合プロセス
DE102011076845.9A DE102011076845B4 (de) 2010-08-20 2011-06-01 Niedrigtemperaturbindeverfahren und Heterostruktur
KR1020110065872A KR101272675B1 (ko) 2010-08-20 2011-07-04 저온 본딩 공정
CN201610091145.6A CN105742258B (zh) 2010-08-20 2011-07-12 低温键合方法
CN2011101994542A CN102376653A (zh) 2010-08-20 2011-07-12 低温键合方法
SG2011059490A SG178688A1 (en) 2010-08-20 2011-08-18 Low-temperature bonding process
US14/334,370 US9117686B2 (en) 2010-08-20 2014-07-17 3D integrated heterostructures having low-temperature bonded interfaces with high bonding energy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1056696A FR2963982B1 (fr) 2010-08-20 2010-08-20 Procede de collage a basse temperature

Publications (2)

Publication Number Publication Date
FR2963982A1 FR2963982A1 (fr) 2012-02-24
FR2963982B1 true FR2963982B1 (fr) 2012-09-28

Family

ID=43827267

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1056696A Active FR2963982B1 (fr) 2010-08-20 2010-08-20 Procede de collage a basse temperature

Country Status (8)

Country Link
US (2) US8790992B2 (fr)
JP (1) JP5555957B2 (fr)
KR (1) KR101272675B1 (fr)
CN (2) CN102376653A (fr)
DE (1) DE102011076845B4 (fr)
FR (1) FR2963982B1 (fr)
SG (1) SG178688A1 (fr)
TW (1) TWI459480B (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2963982B1 (fr) * 2010-08-20 2012-09-28 Soitec Silicon On Insulator Procede de collage a basse temperature
JP6095903B2 (ja) * 2012-06-15 2017-03-15 浜松ホトニクス株式会社 固体撮像装置の製造方法及び固体撮像装置
KR101947165B1 (ko) 2012-10-16 2019-02-13 삼성디스플레이 주식회사 유기 발광 표시 장치와 이의 제조 방법 및 회로 필름의 회전 장치
CN105874571B (zh) * 2013-12-18 2019-12-17 英特尔公司 局部层转移的系统和方法
CN104934292A (zh) * 2014-03-17 2015-09-23 中芯国际集成电路制造(上海)有限公司 一种提高晶圆间键合强度的方法
EP3024019A1 (fr) * 2014-11-24 2016-05-25 IMEC vzw Procédé de liaison directe de substrats semi-conducteurs
CN104891430B (zh) * 2015-04-17 2016-09-28 上海华虹宏力半导体制造有限公司 硅片键合方法
CN104925749B (zh) * 2015-04-17 2017-01-25 上海华虹宏力半导体制造有限公司 硅片键合方法
CN105185720B (zh) * 2015-08-03 2018-05-08 武汉新芯集成电路制造有限公司 一种增强键合强度的超薄热氧化晶圆键合工艺
CN105206536B (zh) * 2015-08-17 2018-03-09 武汉新芯集成电路制造有限公司 一种增强键合强度的晶圆键合方法及结构
CN105261586B (zh) * 2015-08-25 2018-05-25 上海新傲科技股份有限公司 带有电荷陷阱和绝缘埋层衬底的制备方法
US9725312B1 (en) * 2016-02-05 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Preconditioning to enhance hydrophilic fusion bonding
CN107346746B (zh) * 2016-05-05 2020-09-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN109671614B (zh) * 2017-08-10 2020-08-21 长江存储科技有限责任公司 一种晶圆键合方法
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CN105742258B (zh) 2020-09-29
CN102376653A (zh) 2012-03-14
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SG178688A1 (en) 2012-03-29
DE102011076845B4 (de) 2020-02-06
US20140327113A1 (en) 2014-11-06
KR20120018063A (ko) 2012-02-29
TW201218289A (en) 2012-05-01
JP5555957B2 (ja) 2014-07-23
CN105742258A (zh) 2016-07-06
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US20120043647A1 (en) 2012-02-23
FR2963982A1 (fr) 2012-02-24

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