CN105742258A - 低温键合方法 - Google Patents
低温键合方法 Download PDFInfo
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- CN105742258A CN105742258A CN201610091145.6A CN201610091145A CN105742258A CN 105742258 A CN105742258 A CN 105742258A CN 201610091145 A CN201610091145 A CN 201610091145A CN 105742258 A CN105742258 A CN 105742258A
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Abstract
本发明涉及一种低温键合方法,是一种用于组装第一元件和第二元件的方法,所述第一元件包括至少一个第一衬底或者至少一个芯片,所述第二元件包括至少一个第二衬底,该方法包括:a)在每个衬底上形成被称为键合层的表面层,这些键合层的至少其中之一是在小于或等于300℃的温度下形成的;b)在组装之前对所述键合层进行被称为脱气退火的第一退火,所述第一退火至少部分在至少等于后续的键合界面强化温度(Tr)但低于450℃的温度下进行;c)通过使所述键合层的暴露表面接触来组装所述衬底;d)组装好的结构在低于450℃的键合界面强化温度(Tr)下退火。
Description
本申请是中国专利申请号201110199454.2、发明名称为“低温键合方法”、申请人为“S.O.I.TEC绝缘体上硅技术公司”的专利申请的分案申请,该专利申请的申请日为2011年7月12日。
技术领域
本发明涉及第一衬底、平板或芯片与第二衬底、平板或芯片在低温下的键合。尽管使用低温键合,本发明试图实现一种具有可能达到的最好质量和可能达到的最高键合能的键合。
背景技术
特别地,本发明能够应用于复合衬底的制造领域或部件的3D集成。更一般而言,当结构由于部件的存在或者由于材料的特性而不能经受高温热处理时,本发明可以用于通过直接(或者“分子”)键合来形成任何结构。
本发明优选地用于无法承受高处理温度的结构,特别是由于待组装的元件之一中的部件或电路或微部件的存在而无法承受高处理温度的结构。
文献“Waferlevel3-DICsProcesstechnology”C.S.Tan等人的Editors,p.197-217回顾了3D技术。其公开了一种键合方法,该键合方法包括在低温下沉积键合层以及在高于该氧化物的沉积温度的温度下对该氧化物进行脱气退火。
当使用这种技术时,在键合界面处观察到缺陷的存在。这些缺陷可能会转而影响键合能。
因此,出现了寻找通过在低温下键合层来实现两个元件的组装的新颖方法的问题。
发明内容
本发明首先涉及一种用于组装第一元件和第二元件的方法,所述第一元件包括至少一个第一衬底或者至少一个芯片,所述第二元件包括至少一个第二衬底,该方法包括:
a)在每个衬底上形成表面键合层,这些表面键合层的至少其中之一具有小于或等于300℃的温度;
b)在组装之前对所述键合层进行被称为脱气退火的第一退火,所述第一退火至少部分地在至少等于后续的键合界面强化温度(Tr)但低于450℃的温度下进行;
c)通过使所述键合层的暴露表面接触来组装所述衬底;
d)组装好的结构在低于450℃的键合界面强化温度(Tr)下退火。
两个键合层的至少其中之一可以通过沉积来形成,例如通过PECVD或LPCVD型沉积形成。
所述键合层的至少其中之一可以是氧化物型或氮化物型的,例如可以是二氧化硅SiO2或氮化硅Si3N4。
退火步骤b)可包括:
-产生温度斜坡,以便使温度从环境温度逐渐达到至少等于组装后的退火温度的温度;
-和/或在例如介于10分钟或30分钟和2小时或5小时之间的时长内,将温度保持在至少后续的键合界面强化温度(Tr),但低于450℃。
根据本发明的方法还可以在步骤c)之前或步骤b)之前包括为了组装步骤制备多孔表面层的表面的步骤。
步骤c)的组装例如是分子粘附型的。
所述第一衬底或芯片以及所述第二衬底的至少其中之一可包括一个或多个部件。
根据本发明的方法还可以在组装步骤c)之前包括为了形成一个或多个将与其他衬底组装的芯片而单独切割所述衬底的其中之一的步骤。
所述衬底或芯片的至少其中之一可以至少部分地由半导体材料制成,例如由硅制成。
本发明还涉及一种异质结构,包括第一元件和第二元件,所述第一元件包括至少一个第一衬底或至少一个芯片,所述第二元件包括至少一个第二衬底,每个元件包括被称为键合层的多孔表面层,两个元件通过所述键合层组装,该组装具有至少等于3J/m2的键合能。
所述键合层的至少其中之一可以是氧化物型或氮化物型的,例如可以是二氧化硅或氮化硅。
所述衬底或芯片的至少其中之一可以至少部分地由半导体材料制成,例如由硅制成。
优选地,所述键合层之间的组装是分子粘附型的。
更优选地,所述第一衬底或芯片以及所述第二衬底的至少其中之一包括一个或多个部件。
附图说明
图1A至图1C表示根据本发明的方法的一个实施例。
图2A至图2C表示根据本发明的在组装前处理键合层的步骤中的温度变化的各个曲线图。
图3A至图3C表示根据本发明的方法的变形。
图4表示在对比试验中所进行的测量。
具体实施方式
图1A-图1C表示了本发明的第一示意性实施例。
在第一衬底2的表面处形成键合层,此处为薄氧化物层4(图1A),第一衬底2例如由半导体材料制成,有利地由硅、氧化铝(Al2O3)、玻璃或锗制成。该键合层是在低于300℃的低温下形成的。氧化物例如为二氧化硅SiO2,一种用于二氧化硅SiO2的沉积技术可以是PECVD技术。前驱气体例如可以是TEOS(原硅酸四乙酯)、SiH4或N2类型的。
该氧化物层具有例如介于200nm和4μm之间的厚度e1。衬底2包含使其可以提供一种或多种电气功能、电子功能或其他功能的装置(全部用附图标记6表示),例如一个或多个电子和/或光学部件和/或一个或多个MEMS和/或NEMS。
在第二衬底12上形成另一键合层(图1B),此处为薄氧化物层14,第二衬底12例如由半导体材料制成,有利地也是由硅、玻璃或锗制成。该键合层是在低于300℃的低温下形成的。氧化物例如为二氧化硅SiO2,一种用于二氧化硅SiO2的沉积技术可以是PECVD技术。前驱气体例如可以是上文已指出的前驱气体其中之一。该氧化物层具有例如介于200nm和4μm之间的厚度e2。衬底12自身还可以可选地包括使其可以提供一种或多种电气功能、电子功能或其他功能的装置(全部用附图标记16表示),例如一个或多个电子和/或光学部件和/或一个或多个MEMS和/或NEMS。
所获得的键合层4、14均为多孔的,并且不是非常致密。
一般而言,在根据本发明的方法中,由于一个和/或另一衬底中的部件6和部件16的存在,将温度保持在低于450℃或者甚至低于400℃。该条件与形成键合层的步骤有关,因为如上文所述,该步骤是在低于250℃、300℃或350℃的温度下执行的。
可以通过沉积,例如通过LPCVD或PECVD类型的沉积来形成层4、14中的每一个。
在组装两个衬底之前,执行键合层4、14的第一退火。在该退火过程中,这些层4、14所经受的温度至少达到温度Tr,在组装之后,使用该温度Tr来执行键合界面的强化。由于部件6、16的存在,该强化温度Tr本身低于能够使用的最大温度Tmax,例如400℃或450℃。
例如,温度按照斜坡从环境温度逐渐上升到至少强化温度Tr,或者达到高于强化温度Tr但低于能够使用的最大温度Tmax的温度。
图2A中表示了这种斜坡的示例,其中温度以例如介于1℃/分钟和几℃/分钟之间(例如介于1℃/分钟和5℃/分钟之间)的斜率非常缓慢地上升,达到例如350℃的强化温度Tr,然后在该温度Tr保持几小时。
根据如虚线所示的一种变形,温度可以以上述斜率上升到温度T’,温度T’高于强化温度Tr,介于强化温度Tr和最大温度Tmax之间,最大温度Tmax例如等于400℃或450℃。
根据图2B所示的另一种可能,温度非常快速地上升到强化温度Tr,然后在该值稳定一小时或多个小时。根据虚线所示的一种变形,温度非常快速地上升到温度T’,温度T’温度高于强化温度Tr,介于强化温度Tr和最大温度Tmax之间,最大温度Tmax例如等于400℃或450℃。
图2C表示了另一种可能,其中温度以例如介于1℃/分钟和几℃/分钟之间(例如介于1℃/分钟和5℃/分钟之间)的斜率非常缓慢地上升,达到例如350℃的强化温度Tr,然后在该温度保持相对较短的时间,例如介于10分钟和2小时之间,然后逐渐回到环境温度。根据虚线所示的一种变形,温度如上文所述以非常缓和的斜率上升,达到高于强化温度Tr但低于最大温度Tmax的温度T’,然后在该温度T’保持相对较短的时间,例如介于10分钟和2小时之间,然后逐渐回到环境温度。
在组装之前对层4、14退火的这一步骤具有下列作用。在低温下沉积的每个键合层包含许多污染物,其例如源自于诸如N2O的气体前驱物或者是碳基链(carbon-basedchains)类型的。如果这些污染物不事先被去除,则会趋向于在组装两个衬底之后的后续的键合界面强化退火过程中迁移(脱气),并且在这两个衬底的组装界面处形成“气泡”或其他缺陷。这种气泡是无法去除的,并且会使所获得的组装无法使用。
在上文结合图2A-图2C所解释的预先退火步骤中,可以将这些污染种类从键合层4、14除去,而不会导致这些层的多孔性的显著降低。因此,还可以保持键合多孔材料的有利特性。考虑到衬底组装之前该退火步骤中所达到的介于最大温度Tmax和键合界面强化温度Tr之间的退火温度,一定会从键合层4、14提取出这些污染物种。因此在强化退火步骤中这些污染物种不是破坏性的,因为已经精确地在至少等于强化退火温度的温度将它们事先提取出来。
接下来(图1C),通过键合层4、14的自由表面来组装如此处理的两个衬底。在该组装步骤之前可以执行预备处理步骤,例如化学机械抛光CMP。
最后,在小于或等于最大温度Tmax的强化温度Tr下对如此组装的结构进行退火。
根据本发明的方法可以在界面处获得大约数J/m2(例如大于3J/m2或4J/m2)的优质的高键合能。事实上,使用该方法的结果是在键合界面处没有“鼓泡”型的缺陷。例如可以通过被称为“刀片技术(bladetechnique)”(或“双悬臂技术(doublecantilevertechnique)”)的技术来测量键合能。
同样的原理也适用于平板上的一个或多个芯片的键合:只需在根据本发明的第一退火之前或之后切割平板其中之一,以便形成一个或多个芯片。然后将这些芯片单独地组装到第二平板上。
图3A-图3C更详细地表示了该示例。
在第一衬底2’的表面处形成键合层,此处为薄氧化物层4’(图3A),第一衬底2’例如由半导体材料制成,有利地由硅、玻璃或锗制成。
该氧化物层4’是以与上文结合图1A所描述的层4相同的方式(特别是相同的温度)形成的。因此具有相同的特点,特别是多孔性的特点。
该衬底然后被切割成单独的芯片22、24、26、28,在图3A中用垂直的虚线表示。每个单独的芯片本身包括一个或多个电路或者部件22’、24’、26’、28’,上方是键合层4’2,4’4,4’6,4’8的一部分。
图3B所表示的第二衬底与上文结合图1B描述的衬底相同,其键合层是在与已介绍的条件相同的条件下获得的。
如上文所述,根据本发明,可以令每个单独的芯片22、24、26、28和图3B中的衬底12在组装之前接受退火热处理,例如,使温度根据图2A-图2C的任一图中所表示的曲线图其中之一变化。
在该退火之后,可以通过键合层4’2、4’4、4’6、4’8和14的自由表面来组装如此处理的单独的芯片和衬底12。可以在该组装步骤之前执行预备处理步骤,例如每个单独的芯片的键合层以及衬底12的键合层14的化学机械抛光CMP。
作为一种变形,可以在预备退火步骤之后将衬底2’切割成单独的芯片22、24、26、28。其他操作与上文已经描述的类似。
现在给出示意性实施例。
提供第一平板或衬底2和第二平板或衬底12,至少其中之一包括电路或微部件6、16。因此,配置是上文结合图1A和图1B所描述的配置。
由硅烷和N2O或TMS(三甲基硅烷)和N2O前驱物开始,通过PECVD型的LTO技术(低温氧化物形成)在每个待组装表面上形成由SiO2制成的键合层4、14。
在低温(小于或等于250℃)下执行该沉积。由于这样形成的氧化物是相对多孔的和/或具有低密度,因此这种类型的低温沉积有利于获得高键合能。在组装衬底之后,这种特点使得该键合层后续能够吸收键合界面处所俘获的过多的水。
然后按照本发明的方法对这些氧化物进行退火:0.1℃/分钟到5℃/分钟的斜坡(例如:1℃/分钟),以便达到介于350℃和400℃之间的温度。在此温度下持续退火12小时。温度相对缓慢的上升确保混合到键合氧化物4、14中的物种根据它们不同的活化能接连脱气。
接下来,为了进行组装,通过如下方式来制备平板:首先进行表面极化,以便提供与分子键合适应的粗糙度(粗糙度<0.5nmRMS),然后进行清洗,也可以通过待组装的平板表面的刷光来进行补充。
接下来,通过“分子”键合来执行两个平板的组装,并在不超过脱气退火温度的温度下对该组装进行退火,以便不引发仍存在于氧化物中以及在之前的处理过程中未被除去的物种朝向键合界面的迁移。
按照该方法,可以获得大约3.6J/m2的优质的键合能,具体而言,注意到键合界面处没有“鼓泡”型缺陷。这个值应当能够与标准氧化物/氧化物键合(即无孔/致密氧化物)的大约2J/m2的键合能相比较。
对在不同温度下制备的不同类型的氧化物进行对比试验。
图4中对比了相应的测量。三种类型的SiO2氧化物能够被对比。它们是通过PECVD沉积的:
1)第一种是在400℃下以14nm/s的沉积速度沉积的TEOS(原硅酸四乙酯)型氧化物;
2)第二种是在210℃下以4.5nm/s的沉积速度沉积的“硅烷氧化物(silaneoxide)”型氧化物;以及
3)第三种是在400℃下以10nm/s的沉积速度沉积的“硅烷氧化物”型氧化物。
对以上同样的材料,但是是在任何强化退火之前进行键合能的补充测量:这些测量在图4中用短语“无强化退火”来标识。因此,它们对应于尚未执行强化退火情况下的键合能的测量。
从上文所述的条件可以看出,只有第二种氧化物是在低于250℃的温度下沉积的。
除了用短语“无强化退火”标识的图示之外,图4中的各个其他图示表示的是这三种材料所得到的作为(x轴上的)强化退火温度Tr的函数的(y轴上的)γ(单位为mJ/m2),其等于键合能的一半。强化退火温度在200℃和400℃之间变化。
可以观察到,第二种材料(LTOB,在图中为浅灰色)的键合能是第一种材料(TEOS,在图中为深灰色)的键合能的至少两倍,是第三种材料(硅烷氧化物,在图中为白色)所获得的键合能的将近三倍。
无论强化退火温度Tr(200℃、350℃或400℃)是多少,键合有利于第二种氧化物的这种很大的优势都是明显的。只有在“无强化退火”的条件下,3种材料之间才没有差别。
因此,这些试验显示出,低温沉积可以获得沉积氧化物的某种程度的多孔性,其低于使用高温PECVD所获得的沉积氧化物的多孔性。
另外,在无强化退火的情况下,键合能保持很低。
因此可以清楚看出,用于形成键合层的低温与低于450℃的强化温度下的强化退火的结合导致优质的高能键合。如上文所述,键合能等于所测量的参数γ的值的两倍:因此,键合能实际上达到至少3J/m2的值。
在图4的这些图示中,发现在400℃沉积的材料具有与C.S.Tan等人的文献“Lowtemperaturethermaloxidetoplasma-enhancedchemicalvapordepositionoxidewaferbondingforthinfilmtransferapplication”,AppliedPhysicsLetters,Vol.82,No.116,p.2649-2651,2003的图3所表示的能量水平相同的键合能水平。在该文献中,氧化物层本身也是在400℃沉积的。
因此,结合图4来介绍的对比试验与现有技术中已知的数据相吻合。
Claims (18)
1.一种用于组装第一元件和第二元件的方法,所述第一元件包括至少一个第一衬底(2)或者至少一个芯片(22,24,26,28),所述第二元件包括至少一个第二衬底(12),该方法包括:
a)在每个衬底上形成被称为键合层的表面层(4,4’2,4’4,4’6,4’8,14),这些键合层的至少其中之一是在小于或等于300℃的温度下形成的;
b)在组装之前对所述键合层进行被称为脱气退火的第一退火,所述第一退火至少部分地在至少等于后续的键合界面强化温度Tr且高于350℃但低于450℃的温度下进行,而不会导致所述键合层的多孔性的显著降低;
c)通过使所述键合层(4,4’2,4’4,4’6,4’8,14)的暴露表面接触来组装所述衬底;
d)组装好的结构在高于350℃且低于450℃的键合界面强化温度Tr下退火。
2.根据权利要求1所述的用于组装第一元件和第二元件的方法,所述键合层的至少其中之一是通过PECVD或LPCVD沉积获得的。
3.根据权利要求1或2所述的用于组装第一元件和第二元件的方法,所述键合层的至少其中之一是氧化物型或氮化物型的。
4.根据权利要求3所述的用于组装第一元件和第二元件的方法,所述键合层的至少其中之一是氧化硅。
5.根据权利要求1至4中任一项所述的用于组装第一元件和第二元件的方法,所述键合层的至少其中之一是在小于或等于250℃的温度下形成的。
6.根据权利要求1至5中任一项所述的用于组装第一元件和第二元件的方法,所述键合界面强化温度Tr低于400℃。
7.根据权利要求1至6中任一项所述的用于组装第一元件和第二元件的方法,在组装之前对结构进行退火的步骤b)包括产生例如介于1℃/分钟和5℃/分钟之间的温度斜坡。
8.根据权利要求1至7中任一项所述的用于组装第一元件和第二元件的方法,在组装之前对结构进行退火的步骤b)包括在例如介于10分钟或30分钟和2小时或5小时之间的时长内将温度保持在至少后续的键合界面强化温度Tr,但低于450℃。
9.根据权利要求1至8中任一项所述的用于组装第一元件和第二元件的方法,还在步骤c)之前或步骤b)之前包括为了组装步骤制备多孔表面层的表面的步骤。
10.根据权利要求1至9中任一项所述的用于组装第一元件和第二元件的方法,步骤c)的组装是分子粘附型的。
11.根据权利要求1至10中任一项所述的用于组装第一元件和第二元件的方法,所述第一衬底或芯片以及所述第二衬底的至少其中之一包括一个或多个部件(6,16,22’,24’,26’,28’)。
12.根据权利要求1至11中任一项所述的用于组装第一元件和第二元件的方法,在组装步骤c)之前包括为了形成一个或多个将与其他衬底组装的芯片而单独切割所述衬底的其中之一的步骤。
13.根据前述权利要求中任一项所述的用于组装第一元件和第二元件的方法,所述衬底或芯片的至少其中之一至少部分地由半导体材料制成,例如由硅制成。
14.一种异质结构,包括第一元件和第二元件,所述第一元件包括第一衬底(2)或至少一个芯片(22,24,26,28),所述第二元件包括第二衬底(12),每个元件包括被称为键合层的多孔表面层(4,4’2,4’4,4’6,4’8,14),两个元件通过所述键合层组装,该组装具有至少等于3J/m2或4J/m2的键合能。
15.根据权利要求14所述的异质结构,所述键合层的至少其中之一是氧化物型或氮化物型的。
16.根据权利要求14或15所述的异质结构,所述衬底或芯片的至少其中之一至少部分地由半导体材料制成,例如由硅制成。
17.根据权利要求14至16中任一项所述的异质结构,所述键合层之间的组装是分子粘附型的。
18.根据权利要求14至17中任一项所述的异质结构,所述第一衬底或芯片以及所述第二衬底的至少其中之一包括一个或多个部件(6,16,22’,24’,26’,28’)。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108383080A (zh) * | 2018-03-06 | 2018-08-10 | 苏州大学 | 纳米间隙原位活化的复合阳极键合方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2963982B1 (fr) * | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | Procede de collage a basse temperature |
JP6095903B2 (ja) * | 2012-06-15 | 2017-03-15 | 浜松ホトニクス株式会社 | 固体撮像装置の製造方法及び固体撮像装置 |
KR101947165B1 (ko) | 2012-10-16 | 2019-02-13 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치와 이의 제조 방법 및 회로 필름의 회전 장치 |
US10236282B2 (en) | 2013-12-18 | 2019-03-19 | Intel Corporation | Partial layer transfer system and method |
CN104934292A (zh) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | 一种提高晶圆间键合强度的方法 |
EP3024019A1 (en) | 2014-11-24 | 2016-05-25 | IMEC vzw | Method for direct bonding of semiconductor substrates. |
CN104891430B (zh) * | 2015-04-17 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | 硅片键合方法 |
CN104925749B (zh) * | 2015-04-17 | 2017-01-25 | 上海华虹宏力半导体制造有限公司 | 硅片键合方法 |
CN105185720B (zh) * | 2015-08-03 | 2018-05-08 | 武汉新芯集成电路制造有限公司 | 一种增强键合强度的超薄热氧化晶圆键合工艺 |
CN105206536B (zh) * | 2015-08-17 | 2018-03-09 | 武汉新芯集成电路制造有限公司 | 一种增强键合强度的晶圆键合方法及结构 |
CN105261586B (zh) * | 2015-08-25 | 2018-05-25 | 上海新傲科技股份有限公司 | 带有电荷陷阱和绝缘埋层衬底的制备方法 |
US9725312B1 (en) * | 2016-02-05 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Preconditioning to enhance hydrophilic fusion bonding |
CN107346746B (zh) * | 2016-05-05 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN107633997B (zh) * | 2017-08-10 | 2019-01-29 | 长江存储科技有限责任公司 | 一种晶圆键合方法 |
CN112635299A (zh) * | 2020-12-17 | 2021-04-09 | 武汉新芯集成电路制造有限公司 | 低温沉积方法、半导体器件的键合方法和芯片 |
CN113380639A (zh) * | 2021-05-26 | 2021-09-10 | 西安交通大学 | 一种原子级离子清洁活化低温键合装置及方法 |
US20230026052A1 (en) * | 2021-07-22 | 2023-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Atomic layer deposition bonding layer for joining two semiconductor devices |
CN114420549B (zh) * | 2022-03-31 | 2022-11-18 | 深圳新声半导体有限公司 | 一种二氧化硅表面与硅表面低温键合的方法 |
CN114927538B (zh) * | 2022-07-20 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | 晶圆键合方法以及背照式图像传感器的形成方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101359605A (zh) * | 2003-05-19 | 2009-02-04 | 齐普特洛尼克斯公司 | 室温共价粘结的方法 |
EP2091071A1 (en) * | 2008-02-15 | 2009-08-19 | S.O.I.T.E.C. Silicon on Insulator Technologies | Process for bonding two substrates |
CN101853864A (zh) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | 晶片键合方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6090687A (en) | 1998-07-29 | 2000-07-18 | Agilent Technolgies, Inc. | System and method for bonding and sealing microfabricated wafers to form a single structure having a vacuum chamber therein |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
CN102250141B (zh) | 2000-05-22 | 2014-10-01 | 孟山都技术有限责任公司 | 制备n-(膦酰基甲基)甘氨酸化合物的反应系统 |
US6475072B1 (en) | 2000-09-29 | 2002-11-05 | International Business Machines Corporation | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) |
US20040126993A1 (en) * | 2002-12-30 | 2004-07-01 | Chan Kevin K. | Low temperature fusion bonding with high surface energy using a wet chemical treatment |
FR2860249B1 (fr) | 2003-09-30 | 2005-12-09 | Michel Bruel | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
US7235812B2 (en) | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
US8101498B2 (en) * | 2005-04-21 | 2012-01-24 | Pinnington Thomas Henry | Bonded intermediate substrate and method of making same |
FR2895420B1 (fr) | 2005-12-27 | 2008-02-22 | Tracit Technologies Sa | Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. |
US7485539B2 (en) * | 2006-01-13 | 2009-02-03 | International Business Machines Corporation | Strained semiconductor-on-insulator (sSOI) by a simox method |
FR2913528B1 (fr) | 2007-03-06 | 2009-07-03 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche d'oxyde enterree pour la realisation de composants electroniques ou analogues. |
US7795111B2 (en) * | 2007-06-27 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate and manufacturing method of semiconductor device |
FR2923079B1 (fr) * | 2007-10-26 | 2017-10-27 | S O I Tec Silicon On Insulator Tech | Substrats soi avec couche fine isolante enterree |
JP4947316B2 (ja) | 2008-08-15 | 2012-06-06 | 信越化学工業株式会社 | 基板の接合方法並びに3次元半導体装置 |
FR2963982B1 (fr) | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | Procede de collage a basse temperature |
-
2010
- 2010-08-20 FR FR1056696A patent/FR2963982B1/fr active Active
- 2010-10-14 US US12/904,744 patent/US8790992B2/en active Active
-
2011
- 2011-05-27 TW TW100118741A patent/TWI459480B/zh active
- 2011-05-30 JP JP2011120794A patent/JP5555957B2/ja active Active
- 2011-06-01 DE DE102011076845.9A patent/DE102011076845B4/de active Active
- 2011-07-04 KR KR1020110065872A patent/KR101272675B1/ko active IP Right Grant
- 2011-07-12 CN CN2011101994542A patent/CN102376653A/zh active Pending
- 2011-07-12 CN CN201610091145.6A patent/CN105742258B/zh active Active
- 2011-08-18 SG SG2011059490A patent/SG178688A1/en unknown
-
2014
- 2014-07-17 US US14/334,370 patent/US9117686B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101359605A (zh) * | 2003-05-19 | 2009-02-04 | 齐普特洛尼克斯公司 | 室温共价粘结的方法 |
EP2091071A1 (en) * | 2008-02-15 | 2009-08-19 | S.O.I.T.E.C. Silicon on Insulator Technologies | Process for bonding two substrates |
CN101853864A (zh) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | 晶片键合方法 |
Non-Patent Citations (1)
Title |
---|
C.S.TAN: "Low-temperature thermal oxide to plasma-enhanced chemical vapor deposition oxide wafer bonding for thin-film transfer application", 《APPLIED PHYSICS LETTERS》 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108383080A (zh) * | 2018-03-06 | 2018-08-10 | 苏州大学 | 纳米间隙原位活化的复合阳极键合方法 |
CN108383080B (zh) * | 2018-03-06 | 2020-04-10 | 苏州大学 | 纳米间隙原位活化的复合阳极键合方法 |
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JP2012044146A (ja) | 2012-03-01 |
US20120043647A1 (en) | 2012-02-23 |
KR20120018063A (ko) | 2012-02-29 |
CN105742258B (zh) | 2020-09-29 |
SG178688A1 (en) | 2012-03-29 |
US8790992B2 (en) | 2014-07-29 |
CN102376653A (zh) | 2012-03-14 |
TW201218289A (en) | 2012-05-01 |
US9117686B2 (en) | 2015-08-25 |
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