TW201218289A - Low-temperature bonding process - Google Patents

Low-temperature bonding process Download PDF

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Publication number
TW201218289A
TW201218289A TW100118741A TW100118741A TW201218289A TW 201218289 A TW201218289 A TW 201218289A TW 100118741 A TW100118741 A TW 100118741A TW 100118741 A TW100118741 A TW 100118741A TW 201218289 A TW201218289 A TW 201218289A
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Taiwan
Prior art keywords
temperature
substrate
adhesion
combination
tempering
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TW100118741A
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Chinese (zh)
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TWI459480B (en
Inventor
Gweltaz Gaudin
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Soitec Silicon On Insulator
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Publication of TWI459480B publication Critical patent/TWI459480B/en

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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

The invention relates to a process for assembling a first element comprising at least one first substrate (2) or at least one chip, and a second element comprising at least one second substrate (12), this process comprising: (a) the formation of a surface layer (4, 4'2, 4'4, 4'6, 4'8, 14), known as the bonding layer, on each substrate, at least one of these bonding layers being formed at a temperature less than or equal to 300 DEG C; (b) a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature (Tr), but below 450 DEG C; (c) an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers (4, 4'2, 4'4, 4'6, 4'8, 14), (d) an annealing of the assembled structure at a bonding interface strengthening temperature (Tr) below 450 DEG C.

Description

201218289 六、發明說明： 【發明所屬之技術領域】 本發明係關於在低溫下一板體或晶片之第一底材與一板體或晶片 之第二底材之黏附。本發明欲獲取即使在低溫下仍具有最佳品質及最佳 黏附能量之黏附。 本發明尤其可以應用於複合底材製造之領域或元件之三度空間集 積（3D integration)。更一般而言，當一構造因元件之存在或因材料之本 質，而無法施以高溫熱處理時，本發明可應用於經由直接（或「分子」） 黏附而形成該構造。 本發明優先適用於無法耐受高處理溫度之構造，尤其是因待組合之 組件中有元件或電路或微元件存在者。 【先前技術】 C.S. Tan 專人所編者之《wafer ievei 3-D ICs Process technology》一 書（ρ.197-217)提出了對3D科技的回顧。該書揭示一黏附製程其包 括在低/皿下/儿積一黏附層，以及在一高於此氧化物之沉積溫度下，對此 氧化物進行除氣回火。 該技術使用時’可觀察到黏附界面出現缺陷。這些缺陷可能轉而對 黏附能量有不利影響。 因此’找出-種新穎方法，以實現在低溫下經由細層組合兩個組 件之問題’便由此而產生。 【發明内容】 本發明首先與-種將一第一組件與一第二組件組合之製程有關唭 中第、件匕括至少一第一底材或至少一晶片，第二組件包括至少一第 二底材’該製程包括： 201218289 a) 於每一底材上形成一表面黏附層，該些黏附層至少其中之一形成 的溫度低於或等於300oC ; b) 在組合前對該些黏附層進行一第一回火，稱為除氣回火，除氣回 火至少部分期間之溫度至少等於後續之黏附界面強化溫度（Tr)，但低於 450°C ； c) 將該些黏附層之曝露表面互相接觸以組合底材， d) 在一低於450。(：之黏附界面強化溫度（Tr)下，對組合後之構造 施行回火。 該二黏附層至少其中之一可以應用沉積方式形成，例如，pECVD 或LPCVD形態之沉積。 該些黏附層至少其中之一可為氧化物或氮化物形態，例如，矽氧化 物Si〇2或矽氮化物Si3N4。 回火步驟b)可以包括： -產生一溫度斜坡’以便將溫度自環境溫度逐漸提高到至少等於組 合後回火之溫度； -及/或在一段時間内，例如介於1〇或3〇分鐘至2或5小時之間， 將溫度保持在至少等於後續之黏附界面強化溫度（Tr)，但低於45〇〇c。 根據本發明之一種製程可以額外包括，在步驟c)或步驟b)之前整 備該些多孔表面層之表面之一步驟，以便進行組合步驟。 、 步驟c)之組合，舉例而言，為分子附著形態。 該第-底材或晶片及該第二底材至少其中之__可以包括一個或多 個元件。 根據本發明之-種製程，其可以更另亦包括在組合步驟c)之前，對 其中之-的底材進订個別切割之一步驟，以形成所要與另一底材組合之 一個或多個晶片。 該些底材或晶片’至少其中之—有部分可為—種半導體材料所製， 例如為矽製。 4 201218289 本發明亦與-異質構造有關，其包括一第_組件及—第二組件，該 第組件包括至少-第一底材或至少一晶片，該第二組件包括至少一第 二底材’每—組件包括—多孔表面層，麟黏附層，該二組件係經由黏 附層而組合，其組合具有至少等於3 了/m2之—黏附能量。 該些黏附層至少其中之—可為氧化物或氮化物形態 ，例如，矽氧化 物或矽氮化物。 該些底材或晶片，至少其中之一有部分可為一種半導體材料所製， 例如為石夕製。 較佳情況者為，該些黏附層間之組合為分子附著形態。 更佳情況者為’該第一底材或晶片及該第二底材至少其中之一包括 一個或多個元件。 【實施方式】 本發明之第一個說明性質實施例呈現於圖1入至1C。 一黏附層，此處為一薄氧化物層4，形成於一第一底材2的表面上 (圖1A) ’該底材，舉例而言，為一種半導體材料所製，較有利者為石夕 或氧化銘（Al2〇3)或玻璃或鍺所製。該黏附層係在低於3〇〇〇c之低溫下 形成。該氧化物為，舉例而言，矽氧化物Si〇2，其一種沉積技術可為 PECVD技術。一前驅氣體，舉例而言，可以是teos (四乙氧基矽院） 或SiH4或N2形態。 該氧化物層具有一厚度el韻厚度舉例而言介於2〇〇nm及4μπι 之間。該底材2含有能提供一項或多項電力或電子或其他功能之裝置， 該些裝置於此統一以編號6表示，例如，一個或多個電子及/或光學元件， 及/或一個或多個MEMS及/或NEMS。 另一黏附層，此處為一薄氧化物層14，形成於一第二底材12上（圖 出）’該底材’舉例而言，為一種半導體材料所製，同前，較有利者為 201218289 矽或玻璃或鍺所製。該黏附層係在低於300°C之低溫下形成《該氧化物 為，舉例而言，矽氧化物Si〇2，其一種沉積技術可為PECVD技術。一 前驅氣體可為上文已指出之氣體之一。該氧化物層具有一厚度e2，該厚 度’舉例而言’介於200nm及4μιη之間。該底材12亦可選擇性地含有 能提供一項或多項電力或電子或其他功能之裝置，該些裝置於此統一以 編號16表示，例如，一個或多個電子及/或光學元件，及/或一個或多個 MEMS 及/或 NEMS。 經沉積獲得之該些黏附層4、14均為多孔，且不是很緻密。 一般而言，在根據本發明之一種製程中，由於元件6、16存在於一 底材及/或另一底材中，因此溫度被保持在低於450〇(：，或甚至低於 400°C。就形成黏附層之步驟而言，此條件得到遵守，因為如上文所指出， 該步驟係在低於250。(：或300°C或350°C的溫度下進行。 該些黏附層4、14均可以沉積方式形成，例如LpcvD或pECVD 形態之沉積。 在組合該一底材前，先對該些黏附層4、14施行第一回火。在此第 -回火期間’該些黏附層4及14承受的溫度至少達到溫度Tr，該溫度將 在底材組合後’接著用於進行黏附界面之強化。由於元件6、16之存在， 此強化溫度Tr本身低於可使用之最高溫度τ眶，例如4〇〇〇c或4默。 例如，溫度按照-溫度斜坡逐漸上升，從環境溫度上升至至少達到 該強化溫度Tr ’或達到高於強化溫度但低於可使用最高溫度 溫度》 圖2A呈現-溫度斜坡範例，其中，溫度非常穩定地攀升，舉例而 吕’以介於l0C/mm及若干〇c/min之間的坡度，例如介於1〇c/min及 5 C/mm t間’達到強化溫度，例如35〇£)(：，然後保持在此溫度丁圹數 小時。 根據-變化作法’即以虛線呈現者，溫度可按照上述坡度增加至— 皿度τ ’該恤雜強化溫度為高，介於強化溫度以最高溫度 6 201218289 之間，而最南溫度τ_，舉例而言，等於4〇〇〇c或45〇〇c。 圖2B呈現;^可能性，其中，溫度迅速增加至強化溫度^後 穩定地保持在此溫度達—小時或更久。根據—變化作法，即讀線呈現 者，溫=速增加至-溫度Τ’，其她t溫度，[為高，介於強化溫度201218289 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to adhesion of a first substrate of a plate or wafer to a second substrate of a plate or wafer at a low temperature. The present invention is intended to achieve adhesion with optimum quality and optimum adhesion energy even at low temperatures. The invention is particularly applicable to the field of composite substrate manufacturing or the 3D integration of components. More generally, the present invention can be applied to form the structure via direct (or "molecular") adhesion when a structure cannot be subjected to high temperature heat treatment due to the presence of the element or due to the nature of the material. The invention is preferably applicable to configurations that cannot withstand high processing temperatures, especially where components or circuits or microelements are present in the components to be combined. [Prior Art] The book "wafer ievei 3-D ICs Process technology" (ρ.197-217) edited by C.S. Tan, presents a review of 3D technology. The book discloses an adhesion process which includes an adhesive layer under the low/dish/small layer and degassing and tempering the oxide at a deposition temperature above the oxide. When the technique is used, it is observed that defects occur in the adhesion interface. These defects may in turn have an adverse effect on adhesion energy. Therefore, the problem of 'finding a novel method to realize the combination of two components via a fine layer at a low temperature' is thus produced. SUMMARY OF THE INVENTION The present invention first relates to a process of combining a first component and a second component, the first component comprising at least one first substrate or at least one wafer, and the second component comprising at least a second Substrate 'The process includes: 201218289 a) Forming a surface adhesion layer on each substrate, at least one of the adhesion layers forming a temperature lower than or equal to 300oC; b) performing the adhesion layers before combining A first tempering, called degassing and tempering, the temperature of at least part of the degassing and tempering is at least equal to the subsequent adhesion interface strengthening temperature (Tr), but less than 450 ° C; c) exposing the adhesion layers The surfaces are in contact with each other to combine the substrates, d) at a temperature below 450. (: The adhesion interface is strengthened at a temperature (Tr), and the combined structure is tempered. At least one of the two adhesion layers may be formed by deposition, for example, deposition in the form of pECVD or LPCVD. One may be in the form of an oxide or nitride, for example, niobium oxide Si〇2 or niobium nitride Si3N4. The tempering step b) may comprise: - generating a temperature ramp 'to gradually increase the temperature from ambient temperature to at least equal The temperature of the temper after combination; - and / or for a period of time, for example between 1 〇 or 3 〇 minutes to 2 or 5 hours, maintaining the temperature at least equal to the subsequent adhesion interface strengthening temperature (Tr), but Below 45〇〇c. A process according to the present invention may additionally comprise the step of preparing one of the surfaces of the porous surface layers prior to step c) or step b) for the combination step. The combination of step c) is, for example, a molecular attachment morphology. At least one of the first substrate or wafer and the second substrate may comprise one or more components. According to the process of the present invention, it may further comprise, prior to combining step c), the step of individually cutting the individual substrates therein to form one or more of the combinations to be combined with another substrate. Wafer. At least some of the substrates or wafers can be made of a semiconductor material, such as tantalum. 4 201218289 The invention is also related to a heterostructure comprising a first component and a second component, the first component comprising at least a first substrate or at least one wafer, the second component comprising at least one second substrate Each component includes a porous surface layer, a lining adhesive layer, and the two components are combined via an adhesive layer, the combination of which has an adhesion energy at least equal to 3/m2. At least one of the adhesion layers may be in the form of an oxide or a nitride, such as an antimony oxide or a niobium nitride. At least one of the substrates or wafers may be made of a semiconductor material, such as a stone alloy. Preferably, the combination of the adhesion layers is a molecular attachment morphology. More preferably, at least one of the first substrate or wafer and the second substrate comprises one or more components. [Embodiment] A first illustrative embodiment of the invention is presented in Figures 1 through 1C. An adhesive layer, here a thin oxide layer 4, formed on the surface of a first substrate 2 (Fig. 1A). The substrate, for example, is made of a semiconductor material, more preferably a stone. Even oxidized (Al2〇3) or made of glass or enamel. The adhesion layer is formed at a low temperature of less than 3 〇〇〇c. The oxide is, for example, cerium oxide Si 〇 2, one of which may be a PECVD technique. A precursor gas, for example, may be teos (tetraethoxy oxime) or SiH4 or N2 form. The oxide layer has a thickness el thick thickness, for example, between 2 〇〇 nm and 4 μπι. The substrate 2 contains means for providing one or more electrical or electronic or other functions, the devices being designated herein by the numeral 6, for example, one or more electronic and/or optical components, and/or one or more MEMS and / or NEMS. Another adhesive layer, here a thin oxide layer 14, formed on a second substrate 12 (illustrated) 'the substrate' is, for example, made of a semiconductor material, as before, more advantageous Made for 201218289 矽 or glass or enamel. The adhesion layer is formed at a low temperature of less than 300 ° C. The oxide is, for example, tantalum oxide Si〇 2, and one of the deposition techniques may be PECVD technology. A precursor gas can be one of the gases already indicated above. The oxide layer has a thickness e2 which is, for example, between 200 nm and 4 μm. The substrate 12 may also optionally include means for providing one or more electrical or electronic or other functions, the devices being uniformly indicated at 16 herein, for example, one or more electronic and/or optical components, and / or one or more MEMS and / or NEMS. The adhesion layers 4, 14 obtained by deposition are all porous and not very dense. In general, in a process according to the invention, since the elements 6, 16 are present in a substrate and/or in another substrate, the temperature is maintained below 450 〇 (:, or even below 400°). C. This condition is followed in terms of the step of forming the adhesion layer because, as indicated above, the step is carried out at a temperature below 250. (: or 300 ° C or 350 ° C. The adhesion layer 4 , 14 can be formed by deposition, such as deposition of LpcvD or pECVD morphology. Before combining the substrates, the first tempering is performed on the adhesion layers 4, 14. During the first tempering period, the adhesions Layers 4 and 14 are subjected to a temperature at least to a temperature Tr which will then be used to strengthen the adhesion interface after the substrate is combined. Due to the presence of elements 6, 16 this strengthening temperature Tr itself is lower than the highest temperature that can be used.眶 , for example 4 〇〇〇 c or 4 默. For example, the temperature gradually rises according to the -temperature ramp, rising from the ambient temperature to at least the strengthening temperature Tr ' or higher than the strengthening temperature but lower than the maximum temperature that can be used. Figure 2A presents an example of a temperature ramp, which In the middle, the temperature rises very steadily. For example, Lu's reaches a strengthening temperature with a gradient between l0C/mm and several 〇c/min, for example between 1〇c/min and 5 C/mm t, for example 35〇£)(:, and then keep it at this temperature for a few hours. According to the -change method, that is, the line is presented by the dotted line, the temperature can be increased according to the above slope to - the degree τ 'the reinforcement temperature is high, between The intensified temperature is between the highest temperature 6 201218289, and the southernmost temperature τ_, for example, equals 4〇〇〇c or 45〇〇c. Figure 2B presents; ^ possibility, where the temperature rapidly increases to the intensified temperature ^ Stable to maintain this temperature for - hour or longer. According to the change method, that is, the line is presented, the temperature = speed increases to - temperature Τ ', the other t temperature, [high, between the intensification temperature

Tr及最高溫度Tmax之間；而最高溫度Tmax，舉例而言，等於鮮c或 450oC。 圖2C呈現又另-可能性，其中，溫度非常穩定地增加，舉例而言， 以介於PC/min及若干。C/min之間的坡度例如介於π/—及5〇·η 之間’達到強化溫度Tr，例如350〇c，然後保持在此溫度I一段相對短 暫的時間’例如介於10分鐘至2小時之間，然後再逐漸降至環境溫度。 根據-變化作法，即以虛線呈現者，溫度如前述按-非常穩定的坡度增 加’達到-高於強化溫度Tr但低於最高溫度U之溫度τ，，然後保^ 在此/皿度τ -段相對短暫的時間，例如介於⑴分鐘至2小時之間然 後再逐漸降至環境溫度。 … 該些黏附層4、14在組合前進行回火，此一步驟之作用如下。由於 在低溫下沉積的每一黏附層均含有許多污染物，舉例而言，污染物可能 .來自叫〇或碳基鏈結雜的氣態前麟。若不預先加崎除，那麼，在 二底材組合後進行後__界面強化蚊侧，這些污祕报有可能 T遷移（除氣）’並在該二底材敝合界面上形成「氣泡」或其他缺陷。 這類氣泡無法清除，而且會使獲得的組合物變得無法使用。 初步的回火步驟，即上文有關圖2A至2C所說明者，可將這些污 染，源從該些黏附層4、14抽取出來’卻不會導致這些黏附層的多二性 顯著降低。因而，此-步驟可同時保存黏附多孔材料的有利性質。馨於 在底材組合前之初步回火步驟期間所達到的回火溫度，係介於最高溫度 丁咖及黏w界面強化溫度之間，這些污_源絕對會從該些黏:層:、 Η被抽取出來@此’這赌染獅便不會在回火步驟期間造成破 201218289 壞，因為其已在一至少等於強化回火溫度之溫度下預先被抽取出來。 接著（圖ic) ’將經過上述處理的二底材經由該些黏附層4、14 的無污染物表面加以組合。在此組合步驟前，可先進行一預處理步驟， 例如化學機械研磨（chemical mechanical polishing，CMP)。 最後，在低於或等於最高溫度Tmax之強化溫度乃下，對依上述方 式組合好的構造施行回火。 根據本發明之該製程可在界面處獲得品質良好及達到數個J/m2等 級的尚黏附能f，例如大於施2或4施2的雜能量。該製程的採用， 確實達到在細界面上沒有「氣泡」形態之缺関結果。其卿能量之 量、·！舉例而s ’可以採用名為「刮刀技術」（biadetecj^ique)(或「雙 懸臂技術」（double cantilever technique))之技術。 相同原理亦可應用於板體上一個或多個晶片之黏附：在根據本發明 之第一回火之前或之後，裁切其中之一的板體，即足以形成一個或多個 晶片。接著，將這些晶片分別組合在第二板體上。 此範例更詳細呈現於圖3A至3C。 一黏附層，此處為一薄氧化物層4ι，形成於一第一底材2，的表面上 (圖3A) ’該底材’舉綱言’為_種轉聽料所製，較有利者為石夕 或玻璃或鍺所製。 該氧化物層4,形成之方式，與上文有關圖1Α所述之氧化物層4形 成之方式相同（尤其是在相同溫度下）。因此，該氧化物層會具備相同特 性’尤其是多孔性之特性。 該底材接著被裁切為個別之晶片22、24、26、28，如圖3Α中以垂 直虛線示意者。每-個別晶片包括一個或多個電路或元件22,、放、加， 281 ’並被黏附層之一部份4’2、4’4、&、4,8所覆蓋。 圖犯呈現-第二底材，其與上文有關圖1Β所述之底材相同，且 其黏附層係、在與先前已提出之同樣條件下獲得。 接著可依照本發明之上述步驟，舉例而言，根據圖2八至2(：任— 8 201218289 圖式所呈現的圖表之一改變溫度，對每一個別晶片22、24、26、28及圖 3B之底材12，進行組合前之回火熱處理。 回火之後，可將依上述方式處理後之個別晶片及底材12，經由黏 附層4、、4%、4、、4’8及14之無污染物表面加以組合。在此組合步驟前， 可先進行一預處理步驟，例如，對每一個別晶片之黏附層及底材12之黏 附層14，施行化學機械研磨（cmp)。 作為一變化作法’在組合前的回火步驟之後，吾人可將底材2，裁切 為個別晶片22、24、26、28。其他操作均與上文所述者相似。 以下提供一說明性質實施例。 提供一第一板體或底材2 ,及一第二板體或底材12，至少其中之一 包括電路或微元件6、16 »因此’其組構即為上文有關圖ία及1B所述 者。 在每一所要組合之表面上，透過PECVD形態之LTO (低溫氧化形 成）技術，形成Si〇2之黏附層4、14，由矽烷及N20或TMS (三曱基 石夕貌）及N20前驅物開始。 該沉積係在低溫下（低於或等於250。〇進行。此形態之低溫沉積 有助於獲得高黏附能量，因為以此方式形成之氧化物相對多孔及/或具有 低密度。此一特性讓黏附層在底材組合之後，能夠接著吸收被捕捉在黏 附界面上的多餘水分。 接著，依循本發明之製程對該些氧化物施行回火：採用介於 0.1 °C/min及5°C/min間之一溫度斜坡（例如：i〇c/min )，以達到介於350oC 及400°C間之一溫度。該回火在此溫度下持續12小時。相對緩慢的溫度 上升’可確保被該些黏附氧化物4、14納入之污染物種源能夠按其不同 活化能連續除氣。 接著，整備該些板體以便進行組合，先進行表面磨平程序，以提供 一與分子黏附相配之粗度（粗度<0.5 nmRMS)，然後清潔板體；板體清 潔可輔以刷洗待組合之板體表面。 201218289 接著，以「分子」黏附方式進行兩板體之組合，然後讓組合物在不 超過除氣回火溫度之一溫度下進行回火，以免引發那些仍存在於氧化物 中之種源，以及在前述處理期間未被清除之種源，遷移至黏附界面。 經此製程後可獲得約為3.6 J/m2 ’且品質良好之黏附能量：明確地 說，可以注意到黏附界面上沒有「氣泡」形態的缺陷。此黏附能量數值 應與一標準的氧化物/氧化物黏附（亦即，非多孔性/緻密氧化物）所獲得 約為2 J/m2之黏附能量比較。 比較試驗係對在不同溫度下整備，不同形態之氧化物進行。 相應之量測結果整理於圖4。有三種形態的Si〇2氧化物可進行比 較。該些氧化物係以PECVD方式沉積： 1) 第一種為TEOS (四乙氧基矽烷）形態之氧化物，沉積溫度 400°C，沉積速率 I4nm/s ; 2) 第一種為「石夕院氧化物」形態之氧化物，沉積溫度21〇。匚，沉 積速率4.5 nm/s ;及 3) 第二種為「石夕烧氧化物」形態之氧化物，沉積溫度4〇〇〇c，沉 積速率10 nm/s。 黏附能量之補充性量測係針對與上述材料相同，但未經任何強化回 火者而進行：這些量測在圓4中以「未經強化回火」表示。其量測值相 當於在尚未進行強化回火的情況下所量測之黏附能量。 從前文所述條件可知，只有第二種氧化物是在低於25*〇〇c的溫度 下沉積。 除以「未經強化回火」表示者外，圖4中其他圖表呈現之γ值（單 位為mJ/m )係等於當黏附能量（γ軸）作為強化回火溫度Tr (X軸） 的函數時’這二種材料獲得之黏雜量的—半。強化回火溫度1在2〇〇〇c 到400°C之間變化。 可以觀察到第二種材料（LTOB，圖表中淺灰色者）的黏附能量比 第-種材料（TEOS，圖表中深灰色者）獲得的黏附能量至少大兩倍，而 201218289 且幾乎是第三種材料（矽烷氧化物，圖表中白色者）所獲得之黏附能量 的三倍。 而且’不論強化回火溫度Tr為何（200oC，350°C或400〇C)，第二 種氧化物所顯示的卓越黏附優勢均明顯可見。只有在「未經強化回火」 的情況下，三種材料的黏附能量沒有差異。 因此，這些試驗顯示，低溫沉積可使沉積氧化物獲得一定程度的多 孔性，比經由高溫pECVD獲得的多孔性為低。 此外，在沒有強化回火的情況下，黏附能量始終很低。 因此’吾人可清楚看到，在低溫下形成黏附層，結合在低於45〇〇c 的強化溫度下施行強化回火，可產生品質良好的高能量黏附。如上文所 指出，黏附能量等於所測得參數γ值的兩倍：因此，此處的黏附能量確 實達到了至少3J/m2。 在圖4這些圖表中，吾人可發現，在溫度4〇〇〇c下沉積之該些材 料，其黏附能量之程度與C.S.Tan等人在2003年發表於期刊AppiiedTr and the highest temperature Tmax; and the highest temperature Tmax, for example, is equal to fresh c or 450oC. Figure 2C presents yet another possibility, in which the temperature increases very steadily, for example, between PC/min and several. The slope between C/min, for example between π/- and 5〇·η, reaches a strengthening temperature Tr, for example 350 〇c, and then remains at this temperature I for a relatively short period of time, for example between 10 minutes and 2 Between hours, then gradually drop to ambient temperature. According to the -variation method, that is, the one presented by the dotted line, the temperature is increased by the - very stable slope as described above - reaching - the temperature τ higher than the strengthening temperature Tr but lower than the highest temperature U, and then maintaining the / degree τ - The relatively short period of time, for example between (1) minutes and 2 hours and then gradually reduced to ambient temperature. ... The adhesion layers 4, 14 are tempered before being combined, and the effect of this step is as follows. Since each of the adhesion layers deposited at low temperatures contains many contaminants, for example, contaminants may be derived from gaseous precursors of sputum or carbon-based chain nodules. If it is not pre-salted, then after the combination of the two substrates, the __ interface strengthens the mosquito side, and these filths may have T migration (degassing) and form a "bubble" at the interface of the two substrates. Or other defects. Such bubbles cannot be removed and the resulting composition becomes unusable. The preliminary tempering step, i.e., as described above with respect to Figures 2A through 2C, extracts the source from the adhesion layers 4, 14 without causing a significant reduction in the polymorphism of the adhesion layers. Thus, this step can simultaneously preserve the advantageous properties of the adherent porous material. The tempering temperature reached during the initial tempering step before the substrate combination is between the maximum temperature and the bonding temperature of the interface, and the source will definitely be from the layer: Η is extracted @本' This gambling lion will not break 201218289 during the tempering step because it has been pre-extracted at a temperature at least equal to the enhanced tempering temperature. Next (Fig. ic), the two substrates subjected to the above treatment are combined via the non-contaminating surfaces of the adhesion layers 4, 14. Prior to this combination step, a pretreatment step, such as chemical mechanical polishing (CMP), may be performed. Finally, at a strengthening temperature lower than or equal to the maximum temperature Tmax, tempering is performed on the structure combined in the above manner. The process according to the present invention achieves an excellent adhesion energy f at the interface and a number of J/m2 levels, for example, greater than the energy of the application 2 or 4 application. The adoption of this process does result in the absence of a "bubble" pattern on the fine interface. The amount of its energy, ·! For example, s ' can use a technique called "biadetecj^ique" (or "double cantilever technique"). The same principle can also be applied to the adhesion of one or more wafers on a panel: before or after the first tempering according to the present invention, one of the panels is cut, i.e., sufficient to form one or more wafers. Next, these wafers are separately combined on the second plate. This example is presented in more detail in Figures 3A through 3C. An adhesive layer, here a thin oxide layer 4ι, formed on the surface of a first substrate 2 (Fig. 3A) 'The substrate' is defined as a type of transliteration material, which is advantageous It is made of Shi Xi or glass or enamel. The oxide layer 4 is formed in the same manner as the oxide layer 4 described above with respect to Figure 1A (especially at the same temperature). Therefore, the oxide layer will have the same characteristics 'especially the characteristics of porosity. The substrate is then cut into individual wafers 22, 24, 26, 28, as indicated by the vertical dashed lines in Figure 3A. Each individual wafer includes one or more circuits or elements 22, which are placed, applied, 281' and covered by one of the portions 4'2, 4'4, &, 4, 8 of the adhesion layer. The figure presents a second substrate which is identical to the substrate described above with respect to Figure 1 and its adhesion layer is obtained under the same conditions as previously proposed. The above steps of the present invention can then be followed, for example, by changing the temperature according to one of the graphs presented in Figures 8-8 (the - 8 201218289 schema, for each individual wafer 22, 24, 26, 28 and The substrate 12 of 3B is subjected to tempering heat treatment before combination. After tempering, the individual wafers and substrates 12 treated in the above manner can be passed through the adhesion layers 4, 4%, 4, 4'8 and 14 The non-contaminant surfaces are combined. Prior to this combination step, a pre-treatment step may be performed, for example, chemical bonding (cmp) is applied to the adhesion layer of each individual wafer and the adhesion layer 14 of the substrate 12. A variant 'after the tempering step before combination, we can cut the substrate 2 into individual wafers 22, 24, 26, 28. Other operations are similar to those described above. Providing a first plate or substrate 2, and a second plate or substrate 12, at least one of which comprises an electrical circuit or a micro-element 6, 16 ... so that its structure is as described above with respect to Figure ία and As described in 1B. On each surface to be combined, through PECVD form LTO (low temperature oxidation formation) technique to form the adhesion layer 4, 14 of Si〇2, starting from decane and N20 or TMS (trimistene) and N20 precursor. The deposition is at low temperature (less than or equal to 250). The low temperature deposition of this form helps to obtain high adhesion energy because the oxide formed in this way is relatively porous and/or has a low density. This property allows the adhesion layer to be absorbed after the substrate is combined. Capturing excess moisture at the adhesion interface. Next, tempering the oxides according to the process of the present invention: using a temperature ramp between 0.1 °C/min and 5 °C/min (eg: i〇c /min) to reach a temperature between 350oC and 400°C. The tempering lasts for 12 hours at this temperature. The relatively slow temperature rise' ensures the contaminant species incorporated by the adhesion oxides 4, 14. The source can be continuously degassed according to its different activation energies. Next, the plates are prepared for combination, and a surface smoothing procedure is first performed to provide a coarseness (thickness < 0.5 nm RMS) matching with molecular adhesion, and then cleaned. Plate body It can be supplemented by brushing the surface of the plate to be combined. 201218289 Next, the combination of the two plates is carried out by "molecular" adhesion, and then the composition is tempered at a temperature not exceeding one of the degassing and tempering temperatures, so as not to cause those The provenance still present in the oxide, and the provenance that was not removed during the previous treatment, migrated to the adhesion interface. After this process, an adhesion energy of about 3.6 J/m2' and good quality was obtained: specifically It can be noted that there is no "bubble" morphology defect on the adhesion interface. This adhesion energy value should be approximately 2 J/m2 with a standard oxide/oxide adhesion (ie, non-porous/compact oxide). The adhesion energy is compared. The comparative test was carried out on oxides of different forms prepared at different temperatures. The corresponding measurement results are summarized in Figure 4. There are three forms of Si〇2 oxide that can be compared. The oxides are deposited by PECVD: 1) The first one is TEOS (tetraethoxy decane) oxide, the deposition temperature is 400 ° C, and the deposition rate is I4 nm / s; 2) The first one is "Shi Xi The oxide of the oxide form has a deposition temperature of 21 〇.匚, the deposition rate is 4.5 nm/s; and 3) The second is the oxide of the form of “Shi Xi Shao Oxide” with a deposition temperature of 4 〇〇〇 c and a deposition rate of 10 nm/s. The complementary measurement of adhesion energy is performed for the same material as described above, but without any enhanced tempering: these measurements are indicated in Round 4 as "unreinforced tempering". The measured value is equivalent to the adhesion energy measured without fortified tempering. It can be seen from the conditions described above that only the second oxide is deposited at a temperature below 25*〇〇c. Divided by the "unreinforced tempering", the gamma values (in mJ/m) of the other graphs in Figure 4 are equal to the adhesion energy (γ-axis) as a function of the enhanced tempering temperature Tr (X-axis). When the 'two materials obtained the amount of sticky - half. The enhanced tempering temperature 1 varies from 2〇〇〇c to 400°C. It can be observed that the adhesion energy of the second material (LTOB, light gray in the chart) is at least twice as high as that of the first material (TEOS, dark gray in the chart), and 201218289 is almost the third The material (decane oxide, white in the chart) is three times the adhesion energy obtained. Moreover, regardless of the enhanced tempering temperature Tr (200oC, 350°C or 400〇C), the superior adhesion advantages exhibited by the second oxide are clearly visible. There is no difference in the adhesion energy of the three materials only in the case of "unreinforced tempering". Therefore, these tests show that low temperature deposition allows the deposited oxide to have a certain degree of porosity, which is lower than that obtained by high temperature pECVD. In addition, the adhesion energy is always low without enhanced tempering. Therefore, it can be clearly seen that the formation of an adhesion layer at a low temperature and the combination of tempering at a strengthening temperature of less than 45 〇〇c can produce high-quality adhesion with good quality. As noted above, the adhesion energy is equal to twice the measured parameter gamma value: therefore, the adhesion energy here is indeed at least 3 J/m2. In the graphs in Figure 4, we can see that the amount of adhesion of these materials deposited at a temperature of 4 °c is reported by C.S. Tan et al. in 2003 in the journal Appiied.

Physics Letters, Vol.82, No· 116, p.2649-265卜題為〈Low temperature thermal oxide to plasma-enhanced chemical vapor deposition oxide wafer bonding for thin film transfer application >文件中圖3所呈現的黏附能量程 度相同。在此文件中，該些氧化物層亦是在400Τ:的溫度下沉積。 因此，圖4所呈現的比較試驗結果，明顯與從習知技術得知之數據 【圖式簡單說明】 圖1Α至1C呈現一根據本發明之一種製程之實施例。 圖2Α至2C呈現依照本發明，在組合前處理黏附層之一步驟期間，不同 溫度變化之示意圖。 圖3Α至3C呈現根據本發明之一種製程之—變化作法。 圖4呈現在比較試驗的情況下進行量測之結果。 11 201218289 【主要元件符號說明】 2、2,、12 底材 4、4,、4’2、4,4、4,6、4’8、14 薄氧化物層 6、16、22’、24,、26,、28， 元件 22、24、26、28 晶片 12Physics Letters, Vol. 82, No. 116, p. 2649-265, entitled "Low temperature thermal oxide to plasma-enhanced chemical vapor deposition oxide wafer bonding for thin film transfer application" The same level. In this document, the oxide layers are also deposited at a temperature of 400 Å:. Therefore, the comparative test results presented in Fig. 4 are apparently related to the data obtained from the prior art. [Schematic description of the drawings] Figs. 1A to 1C show an embodiment of a process according to the present invention. Figures 2A through 2C are schematic illustrations of different temperature variations during the step of combining the pre-treated adhesive layers in accordance with the present invention. Figures 3A through 3C present a variation of a process in accordance with the present invention. Figure 4 presents the results of measurements taken in the case of comparative experiments. 11 201218289 [Explanation of main component symbols] 2, 2, 12 Substrate 4, 4, 4'2, 4, 4, 4, 6, 4'8, 14 Thin oxide layers 6, 16, 22', 24 , 26, 28, component 22, 24, 26, 28 wafer 12

Claims (1)

201218289 七、申請專利範圍： 1. 一種組合一第一組件與一第二組件之贺栽^ •至少一第一底材⑵或至少一晶片（22 2製 至少-第二底材（12)，該製程包括： 28)，該第一組件包括 a) 於每一底材上形成一表面層（4、4,2、4,4、^、4,、Ml， 附層，該些黏附層至少其中之一是在低於或等於j 為黏 b) 在組合前對該些黏附層進行第一回火， 翁^ ’ 4至5^部;分細之溫度至少等於後續之 以組合c=_刪（4、4,2、4’4、4,6、&、⑷之曝露表面互相接觸 .行回火Φ在一低於伙义之黏附界面強化溫度巾）下，對組合後之構造施 謂程’其中，該些軸層至少其中之一係 -為氧3化iStS第1或2項之製程，其中’該些黏嘛少其中之 矽氧^物t申清專利範圍第3項之製程，其中’該些黏附層至少其中之-為 -係程，其中，該些黏附層至少其中之 為低於64〇ti請專利範圍第1至5項之製程，其中，黏附界面強化溫度（το 7.如肀請專利範圍第1至6項其中一Jg夕制如.t ϊίίΞ_ 包減生—_坡，· 造組合8前之製程，其卜步驟b)之構 之間，將溫度保持在至少等於後續之黏匕 9·如申請專利範圍第1至8 jgAtb τΕλΑΙ c)或步驟b)之•，整備該些多孔之^，其額外包括在步驟 印層之表面之一步驟，以便進行組合步驟。 13 201218289 合為分子利範圍第1至9項其中一項之製程，其中，步驟C)之組 或晶片之製程，其中，該第-底材 26,、28，）。-何其中之一包括一個或多個元件（6、16、22,、24,， c)之前，對其項^中一項之製程’其包括在組合步驟 組合之-個或多^固晶片底材進灯個別切割之一步驟，以形成所要與另一底材 少其^該些底材編至 -第-包日H2—tftr，組件，該第—組件包括 二底材（12)，每ΐ組件包28，）’該第二組件包括一第 之一項增構造，射，細嶋至少其中 底材或 16日^範圍第14或15項其中—項之異f構造，其中，兮此 底材戈明片至少其中之-有部分為—種半導體材料所製，例如為^製^ 至16項其中—項之異質構造，其中，該些 一麻=曰如力範圍第14至17項其中一項之異質構造，其中，該第 24^6，H。第二底材至少其中之—包括—個或多個元件(6 以201218289 VII. Patent application scope: 1. A combination of a first component and a second component, at least one first substrate (2) or at least one wafer (22 2 at least - a second substrate (12), The process comprises: 28), the first component comprises a) forming a surface layer (4, 4, 2, 4, 4, ^, 4, M1, an additional layer on each substrate), the adhesion layers being at least One of them is at a level lower than or equal to j. b) The first tempering of the adhesion layers before the combination, Weng ^ '4 to 5 ^; the temperature of the minute is at least equal to the subsequent combination c=_ Delete (4, 4, 2, 4'4, 4, 6, &, (4) the exposed surfaces are in contact with each other. Line tempering Φ at a lower temperature than the bonding interface to strengthen the temperature towel), the combined structure In the process of saying that, at least one of the shaft layers is a process for the first or second item of the oxygen-based iStS, wherein 'these sticks are less than one of the oxygen-based materials The process, wherein the at least one of the adhesion layers is a system, wherein at least one of the adhesion layers is less than 64 〇 ti, and the processes of the first to fifth patent ranges, wherein Adhesion interface strengthening temperature (το 7. For example, please refer to patent range 1 to 6 of which JG eve system such as .t ϊ ίίΞ_ package reduction _ slope, · process before the combination of 8, its step b) In the meantime, the temperature is maintained at least equal to the subsequent adhesion 9· as in the patent application range 1 to 8 jgAtb τΕλΑΙ c) or the step b), and the porous layer is prepared, which is additionally included on the surface of the step printing layer. A step to perform the combining step. 13 201218289 The process of any one of items 1 to 9 of the molecular benefit range, wherein the group of steps C) or the process of the wafer, wherein the first substrate 26, 28,). - if one of the components includes one or more components (6, 16, 22, 24, c), the process of one of its items is included in the combination step - one or more solid wafers The substrate is in a step of individual cutting of the lamp to form less than the other substrate. The substrate is knitted to the first-package day H2-tftr, and the first component comprises two substrates (12). Each component package 28,) 'the second component includes a first addition structure, a shot, a fine structure of at least one of the substrates or a 16th or 14th range of the 14th or 15th item, wherein the structure is different. At least one of the base Geming tablets - some of which are made of a semiconductor material, for example, a heterogeneous structure of -1 to 16 items, wherein the hemp = 曰 如 force range items 14 to 17 One of the heterostructures, of which the 24th, 6th, H. At least one of the second substrate - including one or more components (6
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2963982B1 (en) * 2010-08-20 2012-09-28 Soitec Silicon On Insulator LOW TEMPERATURE BONDING PROCESS
JP6095903B2 (en) * 2012-06-15 2017-03-15 浜松ホトニクス株式会社 Solid-state imaging device manufacturing method and solid-state imaging device
KR101947165B1 (en) 2012-10-16 2019-02-13 삼성디스플레이 주식회사 Organic light emitting diode display, manufacturing method thereof, and rotating device for circuit film
US10236282B2 (en) 2013-12-18 2019-03-19 Intel Corporation Partial layer transfer system and method
CN104934292A (en) * 2014-03-17 2015-09-23 中芯国际集成电路制造(上海)有限公司 Method for improving bonding intensity of wafers
EP3024019A1 (en) 2014-11-24 2016-05-25 IMEC vzw Method for direct bonding of semiconductor substrates.
CN104891430B (en) * 2015-04-17 2016-09-28 上海华虹宏力半导体制造有限公司 Wafer bonding method
CN104925749B (en) * 2015-04-17 2017-01-25 上海华虹宏力半导体制造有限公司 Silicon wafer bonding method
CN105185720B (en) * 2015-08-03 2018-05-08 武汉新芯集成电路制造有限公司 A kind of ultra-thin thermal oxide wafer bonding technique for strengthening bond strength
CN105206536B (en) * 2015-08-17 2018-03-09 武汉新芯集成电路制造有限公司 A kind of wafer bonding method and structure for strengthening bond strength
CN105261586B (en) * 2015-08-25 2018-05-25 上海新傲科技股份有限公司 Preparation method with charge trap and insulating buried layer substrate
US9725312B1 (en) * 2016-02-05 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Preconditioning to enhance hydrophilic fusion bonding
CN107346746B (en) * 2016-05-05 2020-09-08 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method thereof and electronic device
CN107633997B (en) * 2017-08-10 2019-01-29 长江存储科技有限责任公司 A kind of wafer bonding method
CN108383080B (en) * 2018-03-06 2020-04-10 苏州大学 Composite anodic bonding method for in-situ activation of nano-gap
CN112635299A (en) * 2020-12-17 2021-04-09 武汉新芯集成电路制造有限公司 Low-temperature deposition method, bonding method of semiconductor device and chip
CN113380639A (en) * 2021-05-26 2021-09-10 西安交通大学 Atomic-level ion cleaning activation low-temperature bonding device and method
US20230026052A1 (en) * 2021-07-22 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition bonding layer for joining two semiconductor devices
CN114420549B (en) * 2022-03-31 2022-11-18 深圳新声半导体有限公司 Method for bonding silicon dioxide surface and silicon surface at low temperature
CN114927538B (en) * 2022-07-20 2022-11-11 合肥晶合集成电路股份有限公司 Wafer bonding method and method for forming backside illuminated image sensor

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090687A (en) 1998-07-29 2000-07-18 Agilent Technolgies, Inc. System and method for bonding and sealing microfabricated wafers to form a single structure having a vacuum chamber therein
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
CN102250141B (en) 2000-05-22 2014-10-01 孟山都技术有限责任公司 Reaction systems for making n-(phosphonomethyl)glycine compounds
US6475072B1 (en) 2000-09-29 2002-11-05 International Business Machines Corporation Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP)
US20040126993A1 (en) * 2002-12-30 2004-07-01 Chan Kevin K. Low temperature fusion bonding with high surface energy using a wet chemical treatment
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
FR2860249B1 (en) 2003-09-30 2005-12-09 Michel Bruel METHOD FOR MANUFACTURING PLATE-LIKE STRUCTURE, ESPECIALLY SILICON, PROCESS APPLICATION, AND PLATE-LIKE STRUCTURE, PARTICULARLY SILICON
US7235812B2 (en) 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
US8101498B2 (en) * 2005-04-21 2012-01-24 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
FR2895420B1 (en) 2005-12-27 2008-02-22 Tracit Technologies Sa METHOD FOR MANUFACTURING A PLATE - BASED DISMANTLING STRUCTURE, ESPECIALLY SILICON, AND APPLICATION THEREOF
US7485539B2 (en) * 2006-01-13 2009-02-03 International Business Machines Corporation Strained semiconductor-on-insulator (sSOI) by a simox method
FR2913528B1 (en) 2007-03-06 2009-07-03 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE HAVING A BONE OXIDE LAYER FOR PRODUCING ELECTRONIC OR SIMILAR COMPONENTS
US7795111B2 (en) * 2007-06-27 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
FR2923079B1 (en) * 2007-10-26 2017-10-27 S O I Tec Silicon On Insulator Tech SUBSTRATES SOI WITH INSULATED FINE LAYER ENTERREE
EP2091071B1 (en) * 2008-02-15 2012-12-12 Soitec Process for bonding two substrates
JP4947316B2 (en) 2008-08-15 2012-06-06 信越化学工業株式会社 Substrate bonding method and three-dimensional semiconductor device
US8173518B2 (en) * 2009-03-31 2012-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of wafer bonding
FR2963982B1 (en) 2010-08-20 2012-09-28 Soitec Silicon On Insulator LOW TEMPERATURE BONDING PROCESS

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