CN104925749B - Silicon wafer bonding method - Google Patents
Silicon wafer bonding method Download PDFInfo
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- CN104925749B CN104925749B CN201510187464.2A CN201510187464A CN104925749B CN 104925749 B CN104925749 B CN 104925749B CN 201510187464 A CN201510187464 A CN 201510187464A CN 104925749 B CN104925749 B CN 104925749B
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- oxide layer
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- wafer bonding
- island structure
- bonding method
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Abstract
The invention discloses a silicon wafer bonding method. The method comprises the following steps: providing a first silicon wafer, and forming an island structure in the first silicon wafer; forming a first oxide layer on the first silicon wafer with a thermal oxidation process, wherein the oxide layer is thicker than a central region on the edge of the island structure; forming a second oxide layer on the first oxide layer with a high-density plasma vapor deposition process, and performing rapid thermal annealing treatment, wherein the oxide layer is thinner than the central region on the edge of the island structure, and the first oxide layer and the second oxide layer are taken as bonding oxide layers; and providing a second silicon wafer, wherein the second silicon wafer is bonded with the first silicon wafer through the island structure. According to the characteristics of different processes, the thicknesses of the first oxide layer and the second oxide layer on the island structure compensate with each other, and high surface microcosmic flatness is achieved, so that a large bonding area is achieved when the first silicon wafer and the second silicon wafer are bonded together, and the bonding strength is enhanced.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of wafer bonding method.
Background technology
In recent years, sending out with MEMS (micro-electrico-mechanical-system, mems) technology
Exhibition, various microelectromechanicdevices devices, comprising: microsensor, micro-actuator etc. achieve microminaturization, microminaturization is conducive to improving device
Part integrated level, therefore mems become one of main developing direction.
The Common fabrication processes of mems include body silicon manufacturing process and in particular to the bonding of silicon chip.Turn next to as figure
The schematic diagram of the device architecture during wafer bonding in the prior art shown in 1-5.
As shown in figure 1, first, provide the first silicon chip 1, and mask layer 2 is formed on the first silicon chip 1.Then, cover to described
Film layer 2 is patterned, and etches described first silicon chip 1 with the mask layer 2 of patterning, forms the first cavity 3, as shown in Figure 2.Connect
, as shown in figure 3, continuing to etch described first silicon chip 1, form the second cavity 4, and the side wall of described second cavity 4 is orphan
Island structure 5.Afterwards, refer to Fig. 4, the mask layer in isolated island structure 5 is removed, and using thermal oxidation technology in the first silicon chip 1
Upper formation layer of oxide layer 6.Next according to way of the prior art, it is exactly as shown in figure 5, by the second silicon chip 7 and first
Silicon chip 1 is bonded.
But, refer to Fig. 4 and Fig. 5, in the forming process of oxide layer 6, pars intermedia is compared in the marginal portion of isolated island structure 5
Divide strong reaction, therefore oxide layer 6 defines projection 61 in the marginal portion of isolated island structure 5.So as shown in figure 5, being bonded
Afterwards, actually bonding is to occur in projection 61, rather than whole isolated island structure (on oxide layer) all with the second silicon chip 7 key
It is combined.It will be apparent that such bond strength is very low, it is easily caused and is partially disengaged or even integrally comes off, have a strong impact on
The reliability of device.
Content of the invention
It is an object of the invention to, a kind of wafer bonding method is provided, improves bond strength, prevent from departing between silicon chip.
For solving above-mentioned technical problem, the present invention provides a kind of wafer bonding method, comprising:
First silicon chip is provided, and forms isolated island structure in described first silicon chip；
Described first silicon chip utilize thermal oxidation technology form the first oxide layer, described first oxide layer is in isolated island structure
Edge be thicker than middle section；
Described first oxide layer utilize high density plasma CVD technique form the second oxide layer, and
Carry out quick thermal annealing process, described second oxide layer is thinner than middle section at the edge of isolated island structure, described first oxide layer
With the second oxide layer as bonding oxide layer；
There is provided the second silicon chip, described second silicon chip passes through isolated island structure and the first wafer bonding.
Optionally, for described wafer bonding method, described offer first silicon chip, and formed in described first silicon chip
Isolated island structure includes following process:
Mask layer is formed on described first silicon chip；
Pattern described mask layer；
Carry out etching for the first time, form the first cavity；
Carry out second etching, form the second cavity, described second cavity sidewalls are described isolated island structure；
Remove described mask layer.
Optionally, for described wafer bonding method, the depth of described first cavity is 1-5 μm.
Optionally, for described wafer bonding method, the depth of described second cavity is 30-80 μm.
Optionally, for described wafer bonding method, in described second cavity, it is formed with buffer stopper.
Optionally, for described wafer bonding method, described first oxide layer is formed using thermal oxidation technology.
Optionally, for described wafer bonding method, the thickness of described first oxide layer is 0.2-1.0 μm.
Optionally, for described wafer bonding method, formed using high density plasma CVD technique
Described second oxide layer.
Optionally, for described wafer bonding method, the thickness of described second oxide layer is 0.4-1.5 μm.
Optionally, for described wafer bonding method, after described second silicon chip and the first wafer bonding, also include:
Thinning described second silicon chip.
Optionally, for described wafer bonding method, the thickness after described second wafer thinning is 20-70 μm.
In the wafer bonding method that the present invention provides, the first oxide layer is formed on the first silicon chip, then first first
Second oxide layer is formed on oxide layer, the first oxide layer and the second oxide layer are collectively as bonding oxide layer, and upper surface is smooth,
Then the first silicon chip and the second wafer bonding.Compared to existing technology, utilize the feature of different process in the present invention so that isolated island is tied
The thickness of the ground floor oxide layer on structure and second layer oxide layer compensates mutually, obtains good surface microscopic flatness, from
And make to have larger bonding area when the first silicon chip and the second wafer bonding, improve bond strength.
Brief description
Fig. 1-5 is the schematic diagram of the device architecture during wafer bonding in prior art；
Fig. 6 is the flow chart of wafer bonding method in the embodiment of the present invention；
Fig. 7-Figure 12 is the schematic diagram of the device architecture during wafer bonding method in the embodiment of the present invention.
Specific embodiment
Below in conjunction with schematic diagram, the wafer bonding method of the present invention is described in more detail, which show this
Bright preferred embodiment is it should be appreciated that those skilled in the art can change invention described herein, and still realizes this
Bright advantageous effects.Therefore, description below is appreciated that widely known for those skilled in the art, and is not intended as
Limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
It is necessary to make a large amount of implementation details to realize the specific objective of developer in sending out, such as according to relevant system or relevant business
Limit, another embodiment is changed into by an embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Seek book, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all in the form of very simplification and all using non-
Accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
The core concept of the present invention is, provides a kind of wafer bonding method, using different process feature so that formed
The thickness of the ground floor oxide layer in isolated island structure and second layer oxide layer compensates mutually, obtains good surface microscopic and puts down
Whole degree, thus to improve bond strength.
The method includes:
Step s101, provides the first silicon chip, and forms isolated island structure in described first silicon chip；
Step s102, utilizes thermal oxidation technology to form the first oxide layer, described first oxide layer on described first silicon chip
It is thicker than middle section at the edge of isolated island structure；
Step s103, utilizes high density plasma CVD technique to form second in described first oxide layer
Oxide layer, and carry out quick thermal annealing process, described second oxide layer is thinner than middle section at the edge of isolated island structure, and described
One oxide layer and the second oxide layer are as bonding oxide layer；
Step s104, provides the second silicon chip, and described second silicon chip passes through isolated island structure and the first wafer bonding.
Be exemplified below the preferred embodiment of described wafer bonding method, with clear explanation present disclosure it should be clearly that
, present disclosure is not restricted to following examples, and other pass through the routine techniquess handss of those of ordinary skill in the art
The improvement of section is also within the thought range of the present invention.
Refer to Fig. 6, and combine Fig. 7-Figure 12, wherein Fig. 6 is the flow chart of wafer bonding method in the embodiment of the present invention；
Fig. 7～Figure 12 is the schematic diagram of the device architecture during wafer bonding method in the embodiment of the present invention.
As shown in fig. 6, in the present embodiment, described wafer bonding method includes:
First, refer to Fig. 7-Fig. 9, execution step s101, the first silicon chip is provided, and formed lonely in described first silicon chip
Island structure.Specifically, the selection of described first silicon chip 10 can be conventional silicon chip, including through processes such as prerinse, first
After silicon chip 10 chooses, carry out the formation of mask layer 11.As shown in fig. 7, described mask layer is preferably silicon oxide layer, can pass through
Thermally grown formation or silicon nitride layer, are formed by cvd technique.The thickness of described mask layer 11 can be 0.5-1.5 μ
M, for example, 0.5 μm, 0.8 μm, 1 μm etc..Certainly, the thickness of described mask layer 11 is not confined entirely to this scope, other thickness
Mask layer 11 also possible.
Refer to Fig. 8, after mask layer 11 is formed, mask layer 11 is patterned, for example, pass through lithographic etch process
Some regions of mask layer 11 are removed, the mask layer 11 after to pattern, as mask, carries out the first of the first silicon chip 10 afterwards
Secondary etching, forms the first cavity 12.Preferably, the depth of described first cavity 12 is 1-5 μm, such as 2 μm, 3 μm, 5 μm etc..So
Afterwards, refer to Fig. 9, proceed second etching, form the second cavity 13.The side wall of described second cavity 13 is isolated island knot
Structure 14.The depth of described second cavity 13 is 30-80 μm, such as 40 μm, 50 μm, 60 μm etc..Wherein, carrying out second etching
When, it is formed with buffer stopper 131 in the second cavity 13.The height of described buffer stopper 131 can be chosen as the depth of the second cavity 13
Degree and the difference of the depth of the first cavity 12 are it is also possible to be less than.Then, remove mask layer 11.
Then, carry out step s102: utilize thermal oxidation technology to form the first oxide layer 15, institute on described first silicon chip 10
State the first oxide layer 15 and be thicker than middle section at the edge of isolated island structure 14.The thickness of described first oxide layer 15 can be 0.2-
1.0μm.As shown in Figure 10, after thermal oxide, in the edge of isolated island structure 14 upper end, the thickness of the first oxide layer 15 is greater than
The thickness of first oxide layer 15 in isolated island structure 14 upper-center region, that is, as described in prior art, can form projection
151.Then, then carry out next step.
Afterwards, carry out step s103, refer to Figure 11, high-density plasma is utilized on described first oxide layer 15
Learn gas-phase deposition (hdp cvd) and form the second oxide layer 16, and carry out quick thermal annealing process, described second oxide layer 16
It is thinner than middle section at the edge of isolated island structure 14, described first oxide layer 15 and the second oxide layer 16 are as bonding oxide layer.
Second oxide layer 16 is formed on the first oxide layer 15, carries out rapid thermal annealing (rta) after formation of deposits and process, described rta
It is to continue the time of 10～120 seconds at 950～1100 DEG C so that this second oxide layer 16 is finer and close and stress is little.Preferably
, the thickness of described second oxide layer 16 is 0.4-1.5 μm, such as 0.6 μm, 1 μm, 1.2 μm etc..As seen from Figure 11, by
It is thicker than middle section in the first oxide layer 15 at isolated island structure 14 edge, and the second oxide layer 16 is thinner than at the edge of isolated island structure
Middle section, the ground floor oxide layer 15 and second therefore after the formation of this two-layer oxide layer so that in isolated island structure 14
The thickness of layer oxide layer 16 compensates mutually, obtains good surface microscopic flatness, thus the bonding oxide layer upper table obtaining
Face is smooth.
Afterwards, carry out step s104, refer to Figure 12, the second silicon chip 20 is provided, described second silicon chip 20 is tied by isolated island
Structure 14 is bonded with the first silicon chip 10.As seen from Figure 12, the first silicon chip 10 and the second silicon chip 20 have larger bonding area, and not
It is as being only bonded in edge in prior art, this improves bond strength.
After described second silicon chip 20 is bonded with the first silicon chip 10, also include: thinning described second silicon chip.For example described
Thickness after two wafer thinnings is 20-70 μm, according to different process requirements, can select different thickness, such as 30 μm, 40
μm, 50 μm etc..
Compared to existing technology, (i.e. the first oxide layer is thick in isolated island structural edge to utilize the feature of different process in the present invention
In middle section, and the second oxide layer is thinner than middle section at the edge of isolated island structure) so that ground floor oxygen in isolated island structure
The thickness changing layer and second layer oxide layer compensates mutually, obtains good surface microscopic flatness so that the first silicon chip with
There is larger bonding area during the second wafer bonding, improve bond strength.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (9)
1. a kind of wafer bonding method, comprising:
First silicon chip is provided, and forms isolated island structure in described first silicon chip；
Described first silicon chip utilize thermal oxidation technology form the first oxide layer, described first oxide layer is on the side of isolated island structure
Edge is thicker than middle section；
Described first oxide layer utilizes high density plasma CVD technique form the second oxide layer, and carry out
Quick thermal annealing process, described second oxide layer is thinner than middle section at the edge of isolated island structure, described first oxide layer and
Dioxide layer, as bonding oxide layer, improves surface microscopic flatness, thus improving bond strength；
There is provided the second silicon chip, described second silicon chip passes through isolated island structure and the first wafer bonding.
2. wafer bonding method as claimed in claim 1 is it is characterised in that described offer first silicon chip, and described first
Form isolated island structure in silicon chip and include following process:
Mask layer is formed on described first silicon chip；
Pattern described mask layer；
Carry out etching for the first time, form the first cavity；
Carry out second etching, form the second cavity, described second cavity sidewalls are described isolated island structure；
Remove described mask layer.
3. wafer bonding method as claimed in claim 2 is it is characterised in that the depth of described first cavity is 1-5 μm.
4. wafer bonding method as claimed in claim 3 is it is characterised in that the depth of described second cavity is 30-80 μm.
5. wafer bonding method as claimed in claim 4 is it is characterised in that be formed with buffer stopper in described second cavity.
6. wafer bonding method as claimed in claim 1 is it is characterised in that the thickness of described first oxide layer is 0.2～1.0
μm.
7. wafer bonding method as claimed in claim 1 is it is characterised in that the thickness of described second oxide layer is 0.4-1.5 μ
m.
8. wafer bonding method as claimed in claim 1 is it is characterised in that in described second silicon chip and the first wafer bonding
Afterwards, also include:
Thinning described second silicon chip.
9. wafer bonding method as claimed in claim 8 is it is characterised in that the thickness after described second wafer thinning is 20-
70μm.
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| CN108695231A (en) * | 2017-04-08 | 2018-10-23 | 沈阳硅基科技有限公司 | The preparation method of super thick soi wafer oxide layer |
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| CN109913880A (en) * | 2017-12-13 | 2019-06-21 | 南京机器人研究院有限公司 | A kind of weldment method for protecting surface |
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| JP2006173568A (en) * | 2004-12-14 | 2006-06-29 | Korea Electronics Telecommun | Method of manufacturing soi substrate |
| FR2963982B1 (en) * | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | LOW TEMPERATURE BONDING PROCESS |
| CN102130039B (en) * | 2010-12-27 | 2013-04-10 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process |
| FR2981940B1 (en) * | 2011-10-26 | 2014-06-06 | Commissariat Energie Atomique | PROCESS FOR DIRECTLY BONDING A SILICON OXIDE LAYER |
| CN104167372A (en) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | Mixed bonding method |
| CN104409411B (en) * | 2014-11-24 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and forming method thereof |
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| CN108695231A (en) * | 2017-04-08 | 2018-10-23 | 沈阳硅基科技有限公司 | The preparation method of super thick soi wafer oxide layer |
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