CN107658323B - A kind of deep via forming method - Google Patents
A kind of deep via forming method Download PDFInfo
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- CN107658323B CN107658323B CN201711009812.2A CN201711009812A CN107658323B CN 107658323 B CN107658323 B CN 107658323B CN 201711009812 A CN201711009812 A CN 201711009812A CN 107658323 B CN107658323 B CN 107658323B
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 168
- 239000002131 composite material Substances 0.000 claims description 54
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 32
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 31
- 229910052799 carbon Inorganic materials 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000010276 construction Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 150000002148 esters Chemical class 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005286 illumination Methods 0.000 abstract description 4
- 238000005457 optimization Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The present invention provides a kind of deep via forming method, belongs to back side illumination image sensor field, by stop-layer being arranged in buffer layer to form upper buffer layer, stop-layer and bottom breaker, passes through main etching twice and the deep via of over etching formation twice.Beneficial effects of the present invention: the present invention can increase buffer layer thickness uniformity by adding stop-layer, the etch process time is reduced, the influence of each deep via rate difference of center wafer and Waffer edge is reduced, to reduce center to edge load effect, optimization technique improves yield.
Description
Technical field
The present invention relates to back side illumination image sensor technical field more particularly to a kind of deep via forming methods.
Background technique
In back side illumination image sensor (Back Side Illumination, BSI) manufacture, need device die
(Device wafer) and signal operation wafer (Logic wafer) two panels wafer carries out bonding together to form composite construction, then right
Composite construction performs etching to form deep via, and two panels wafer is connected using the deep via.
As shown in Figure 1, being from top to bottom followed successively by teos layer to form schematic diagram when deep via in the prior art
(TEOS), upper oxidation silicon buffer layer (BFOX), metal oxide layer (Hik), silicon layer (Si), silicon oxide dielectric interlayer
(ILDOX), carbon containing silicon nitride layer (NDC), carbon containing silica (BD), carbon containing silicon nitride layer (NDC), carbon containing silica
(BD), carbon containing silicon nitride layer (NDC), carbon containing silica (BD), in middle silicon nitride layer (MSIN), upper oxidation silicon buffer layer
(TPEOX), SiClx layer (BSIN), lower oxidation silicon buffer layer (BPEOX), carbon containing silicon nitride layer (NDC) under nitrogen.Wherein, MSIN
TPEOX between BSIN is adhesive layer (Bonding layers), and adhesive layer is the oxide of 20k.
With continued reference to Fig. 1, from top to bottom TEOS, BFOX, Hik, Si constitute the first composite layer, from top to bottom ILDOX, NDC,
BD, NDC, BD, NDC, BD constitute the second composite layer, and the first composite layer, the second composite layer, MSIN and TPEOX are device die portion
Point, i.e. TPEOX and its above are device dies；From top to bottom BFEOS, NDC constitute third composite layer, TPEOX, BSIN and third
Composite layer is signal operation wafer, i.e. TPEOX and its following are signal operation wafers；Have below BSIN and in third composite layer
Metal top layer (TM).
One is etched in advance in the first composite layer when carrying out deep via technique based on above-mentioned composite construction with continued reference to Fig. 1
Groove terminates in the upper surface of the ILDOX in the second composite layer under groove, then to the second composite layer, MSIN, TPEOX, part
BSIN is performed etching to be formed deep via (DV), is terminated in the BSIN above TM under deep via, and mastering hole depth is about
3.7um。
Specific steps are as follows: photoresist layer (PR) is deposited first, in the lower and side wall and the first composite layer of PR covering groove
TEOS upper surface, PR is equipped with etching window, the corresponding DV finally needed to form of the etching window, then using PR as exposure mask
A main etching (ME) is carried out to etch the second composite layer, MSIN and part TPEOX and terminate in TPEOX, continues with PR to be to cover
Film carries out an over etching (OE) to etch residue TPEOX, part BSIN and terminate in the BSIN above TM, masters to be formed
Hole carries out primary cleaning finally to remove PR.
As shown in Fig. 2, current techniques form DV by the way of ME+OE+ cleaning, during main etching and over etching,
Due to the TPEOX difference in thickness in center wafer (or crystal circle center) and Waffer edge etch-rate difference, different composite structure,
Cause the BSIN of Waffer edge to be first etched to penetrate, and be etched and penetrate after the BSIN of center wafer, to be formed in deep via
Center is generated in the process to edge load effect (center-to-edge loadingeffect), and the BSIN of Waffer edge is first
Being etched to penetrate causes Waffer edge first to expose TM, causes production loss so as to cause bond failure, and then influence wafer acceptance
Test (waferacceptance testing, WAT) and yield (yield).
Summary of the invention
Aiming at the problems existing in the prior art, the present invention relates to backside-illuminated sensor manufacturing technology field, one is provided
Kind is suitable for the deep via forming method of composite construction.
The present invention adopts the following technical scheme:
A kind of deep via forming method, is suitable for composite construction, and the composite construction is brilliant by device die and signal operation
It is constituted after member bonding, the device die includes the first composite layer, the second composite layer, middle silicon nitride from top to bottom set gradually
Layer and buffer layer, the signal operation wafer include the buffer layer, lower silicon nitride layer and third from top to bottom set gradually
Composite layer, a groove is equipped in first composite layer, and the upper surface of the channel bottom exposure second composite layer is described
A top-level metallic is equipped in lower silicon nitride layer and the third composite layer；The buffer layer include upper buffer layer, stop-layer and under
Buffer layer；
The deep via forming method includes:
Step S1, a photoresist layer is deposited, the upper surface of the first composite layer described in the photoresist overlay, the groove
The bottom of side wall and the groove, setting is used to form the etching window of deep via to cover as etching on Yu Suoshu photoresist layer
Film；
Step S2, first time main etching is carried out, to etch second composite layer and a part of upper buffer layer and stop
In the upper buffer layer；
Step S3, first time over etching is carried out, to etch upper buffer layer and the stop-layer described in another part and terminate in
The upper surface of the bottom breaker；
Step S4, second of main etching is carried out, to etch a part of bottom breaker and terminate in the bottom breaker；
Step S5, second of over etching is carried out, to etch bottom breaker described in another part and a part of lower nitridation
Silicon layer simultaneously terminates in another above the top-level metallic lower silicon nitride layer, to form the deep via.
Preferably, the buffer layer is oxidation silicon buffer layer.
Preferably, the first composite layer includes the teos layer from top to bottom set gradually, upper oxidation silicon buffer layer, gold
Belong to oxide skin(coating) and silicon layer.
Preferably, the second composite layer includes the silicon oxide dielectric interlayer from top to bottom set gradually, carbon containing upper nitridation
It is silicon layer, carbon containing upper silicon oxide layer, carbon containing middle silicon nitride layer, carbon containing middle silicon oxide layer, carbon containing upper silicon oxide layer, carbon containing
Lower silicon nitride layer, carbon containing lower silicon oxide layer.
Preferably, the third composite layer includes the lower oxidation silicon buffer layer from top to bottom set gradually and carbon containing bottom
Silicon nitride layer.
Preferably, the deep via forming method further include:
Step S6, first dressing is carried out, to remove the photoresist layer.
Preferably, in the step S2, when carrying out first time main etching, etch rate 4K/min.
Preferably, in the step S3, when carrying out first time over etching, etch rate 2.5K/min.
Preferably, in the step S4, when carrying out second of main etching, etch rate 4K/min.
Preferably, in the step S5, when carrying out second of over etching, etch rate is greater than 2.5K/min.
Preferably, in the step S5, carry out second of over etching after, the lower silicon nitride layer with a thickness of
Beneficial effects of the present invention: the present invention can increase buffer layer thickness uniformity by adding stop-layer, reduce erosion
The carving technology time reduces the influence of each deep via rate difference of center wafer and Waffer edge, to reduce center to side
Edge load effect, optimization technique improve yield.
Detailed description of the invention
Fig. 1 is the flow diagram of deep via forming method in the prior art；
Fig. 2 is the chip schematic diagram after forming deep via in the prior art；
Fig. 3 is the flow chart of deep via forming method in a preferred embodiment of the present invention；
Fig. 4 is the flow diagram of deep via forming method in a preferred embodiment of the present invention.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals be can be combined with each other between technical characteristic.
A specific embodiment of the invention is further described with reference to the accompanying drawing:
As shown in Figure 3-4, a kind of deep via forming method is suitable for composite construction, and above-mentioned composite construction is by device die
It is constituted with after the bonding of signal operation wafer, above-mentioned device die includes the first composite layer from top to bottom set gradually, second multiple
Closing layer, middle silicon nitride layer and buffer layer, above-mentioned signal operation wafer includes the above-mentioned buffer layer from top to bottom set gradually, lower nitrogen
SiClx layer and third composite layer are equipped with a groove, above-mentioned second composite layer of above-mentioned channel bottom exposure in above-mentioned first composite layer
Upper surface, a top-level metallic is equipped in above-mentioned lower silicon nitride layer and above-mentioned third composite layer；Above-mentioned buffer layer includes upper buffering
Layer 13, stop-layer 14 and bottom breaker 15；
Above-mentioned deep via forming method includes:
Step S1, a photoresist layer 20 is deposited, above-mentioned photoresist 20 covers the upper surface of above-mentioned first composite layer, above-mentioned ditch
The bottom of the side wall of slot and above-mentioned groove, on Yu Shangshu photoresist layer 20 setting be used to form the etching window of deep via using as
Etch mask；
Step S2, first time main etching ME1 is carried out, to etch above-mentioned second composite layer and a part of above-mentioned upper buffer layer 13
And it terminates in above-mentioned upper buffer layer 13；
Step S3, first time over etching OE1 is carried out, to etch the above-mentioned upper buffer layer 13 of another part and above-mentioned stop-layer 14
And terminate in the upper surface of above-mentioned bottom breaker 15；
Step S4, second of main etching ME2 is carried out, to etch a part of above-mentioned bottom breaker 15 and terminate in above-mentioned lower buffering
In layer 15；
Step S5, carry out second of over etching OE2, with etch the above-mentioned bottom breaker 15 of another part and it is a part of it is above-mentioned under
Silicon nitride layer 16 simultaneously terminates in another above above-mentioned top-level metallic 19 above-mentioned lower silicon nitride layer 16, to form above-mentioned depth
Through-hole.
In the present embodiment, buffer layer thickness uniformity can be increased by adding stop-layer, reduces the etch process time,
The influence of each deep via rate difference of center wafer and Waffer edge is reduced, thus reduce center to edge load effect,
Optimization technique improves yield.
ME1+OE1 stops in intermediate SIN, and balanced load, OE2 is dropped to down using high oxide/SIN selectivity formula
SIN。
Addition buffer area SIN can increase OX the thickness uniformity, reduce the etch process time, reduce center wafer and edge
Each rate difference influence.Therefore, load effect of the reduction center to edge.Optimization technique improves yield.
In a specific embodiment, when carrying out first time main etching ME1, retain about 5K oxide layer, Pattern ER (figure
Case etch rate) about 4K/min；
After carrying out first time over etching OE1, remaining 5K oxide layer is removed, Pattern ER is greater than 2.5K/min；
When carrying out second of main etching ME2, retain about 5K oxide layer, Pattern ER about 4K/min；
After carrying out second of over etching OE2, removes remaining 5K oxide layer and stop atSIN on,
Pattern ER is greater than 2.5K/min.
In preferred embodiment, above-mentioned buffer layer is oxidation silicon buffer layer.
In preferred embodiment, the first composite layer includes the teos layer 1 from top to bottom set gradually, upper silica
Buffer layer 2, metal oxide layer 3 and silicon layer 4.
In preferred embodiment, the second composite layer includes the silicon oxide dielectric interlayer 5 from top to bottom set gradually, carbon containing
Upper silicon nitride layer 6, carbon containing upper silicon oxide layer 7, carbon containing middle silicon nitride layer 8, carbon containing middle silicon oxide layer 9, carbon containing upper
Silicon oxide layer 10, carbon containing lower silicon nitride layer 11, carbon containing lower silicon oxide layer 12.
In preferred embodiment, above-mentioned third composite layer include the lower oxidation silicon buffer layer 17 from top to bottom set gradually and
Carbon containing base silicon nitride layer 18.
In preferred embodiment, above-mentioned deep via forming method further include:
Step S6, first dressing is carried out, to remove above-mentioned photoresist layer 20.
In preferred embodiment, in above-mentioned steps S2, when carrying out first time main etching, etch rate 4K/min.
In preferred embodiment, in above-mentioned steps S3, when carrying out first time over etching, etch rate 2.5K/min.
In preferred embodiment, when carrying out second of main etching, etch rate 4K/min.
In preferred embodiment, when carrying out second of over etching, etch rate is greater than 2.5K/min.
In preferred embodiment, after carrying out second of over etching, the thickness of above-mentioned lower silicon nitride layer
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, based on present invention essence
Mind can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (11)
1. a kind of deep via forming method is suitable for composite construction, the composite construction is by device die and signal operation wafer
It is constituted after bonding, the device die includes the first composite layer, the second composite layer, middle silicon nitride layer from top to bottom set gradually
And buffer layer, the signal operation wafer include that the buffer layer, lower silicon nitride layer and third from top to bottom set gradually is answered
Layer is closed, a groove, the upper surface of the channel bottom exposure second composite layer, under described are equipped in first composite layer
A top-level metallic is equipped in silicon nitride layer and the third composite layer；It is characterized in that, the buffer layer includes upper buffer layer, stops
Only layer and bottom breaker；
The deep via forming method includes:
Step S1, deposit a photoresist layer, the upper surface of the first composite layer described in the photoresist overlay, the groove side wall
And the bottom of the groove, setting is used to form the etching window of deep via using as etch mask on Yu Suoshu photoresist layer；
Step S2, first time main etching is carried out, to etch second composite layer and a part of upper buffer layer and terminate in institute
It states in buffer layer；
Step S3, first time over etching is carried out, to etch upper buffer layer and the stop-layer described in another part and terminate in described
The upper surface of bottom breaker；
Step S4, second of main etching is carried out, to etch a part of bottom breaker and terminate in the bottom breaker；
Step S5, second of over etching is carried out, to etch bottom breaker described in another part and a part of lower silicon nitride layer
And terminate in another above the top-level metallic lower silicon nitride layer, to form the deep via.
2. the method according to claim 1, which is characterized in that the buffer layer is oxidation silicon buffer layer.
3. the method according to claim 1, which is characterized in that the first composite layer includes the positive silicic acid second from top to bottom set gradually
Ester layer, upper oxidation silicon buffer layer, metal oxide layer and silicon layer.
4. the method according to claim 1, which is characterized in that the second composite layer includes the silica electricity from top to bottom set gradually
Medium interlayer, carbon containing upper silicon nitride layer, carbon containing upper silicon oxide layer, carbon containing middle silicon nitride layer, carbon containing middle silicon oxide layer,
Carbon containing upper silicon oxide layer, carbon containing lower silicon nitride layer, carbon containing lower silicon oxide layer.
5. the method according to claim 1, which is characterized in that the third composite layer includes the lower oxygen from top to bottom set gradually
SiClx buffer layer and carbon containing base silicon nitride layer.
6. the method according to claim 1, which is characterized in that the deep via forming method further include:
Step S6, first dressing is carried out, to remove the photoresist layer.
7. the method according to claim 1, which is characterized in that in the step S2, when carrying out first time main etching, etch rate
For 4K/min.
8. the method according to claim 1, which is characterized in that in the step S3, when carrying out first time over etching, etch rate
For 2.5K/min.
9. the method according to claim 1, which is characterized in that in the step S4, when carrying out second of main etching, etch rate
For 4K/min.
10. the method according to claim 1, which is characterized in that in the step S5, when carrying out second of over etching, etching speed
Rate is greater than 2.5K/min.
11. the method according to claim 1, which is characterized in that in the step S5, after carrying out second of over etching, under described
Silicon nitride layer with a thickness of
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|---|---|---|---|---|
| CN102931133A (en) * | 2012-11-12 | 2013-02-13 | 中微半导体设备(上海)有限公司 | Method for improving etching uniformity in silicon piercing process |
| CN103107178A (en) * | 2013-01-14 | 2013-05-15 | 陆伟 | Method for manufacturing back-illuminated image sensor deep groove by using negative photoresist |
| CN103972257A (en) * | 2014-05-29 | 2014-08-06 | 豪威科技(上海)有限公司 | Stack type image sensor manufacturing method |
| CN106298502A (en) * | 2015-05-18 | 2017-01-04 | 中微半导体设备(上海)有限公司 | A kind of method utilizing plasma that multilayer material is etched |
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| US7704869B2 (en) * | 2007-09-11 | 2010-04-27 | International Business Machines Corporation | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
| US9984967B2 (en) * | 2015-12-21 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931133A (en) * | 2012-11-12 | 2013-02-13 | 中微半导体设备(上海)有限公司 | Method for improving etching uniformity in silicon piercing process |
| CN103107178A (en) * | 2013-01-14 | 2013-05-15 | 陆伟 | Method for manufacturing back-illuminated image sensor deep groove by using negative photoresist |
| CN103972257A (en) * | 2014-05-29 | 2014-08-06 | 豪威科技(上海)有限公司 | Stack type image sensor manufacturing method |
| CN106298502A (en) * | 2015-05-18 | 2017-01-04 | 中微半导体设备(上海)有限公司 | A kind of method utilizing plasma that multilayer material is etched |
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