CN107658323A - A kind of deep via forming method - Google Patents
A kind of deep via forming method Download PDFInfo
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- CN107658323A CN107658323A CN201711009812.2A CN201711009812A CN107658323A CN 107658323 A CN107658323 A CN 107658323A CN 201711009812 A CN201711009812 A CN 201711009812A CN 107658323 A CN107658323 A CN 107658323A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 106
- 239000002131 composite material Substances 0.000 claims description 45
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 32
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 31
- 229910052799 carbon Inorganic materials 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000010276 construction Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 150000002148 esters Chemical class 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 238000005286 illumination Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Abstract
The present invention provides a kind of deep via forming method, belongs to back side illumination image sensor field, by setting stop-layer in cushion to form cushion, stop-layer and bottom breaker, passes through main etching twice and the deep via of over etching formation twice.Beneficial effects of the present invention：The present invention can increase buffer layer thickness uniformity by adding stop-layer, reduce the etch process time, reduce the influence of center wafer and each deep via speed difference of Waffer edge, so as to the center of reducing to edge load effect, optimize technique, improve yield.
Description
Technical field
The present invention relates to back side illumination image sensor technical field, more particularly to a kind of deep via forming method.
Background technology
, it is necessary to by device die in back side illumination image sensor (Back Side Illumination, BSI) manufacture
(Device wafer) and signal operation wafer (Logic wafer) two panels wafer carries out bonding together to form composite construction, then right
Composite construction performs etching to form deep via, turns on two panels wafer using the deep via.
As shown in figure 1, to form schematic diagram during deep via in the prior art, teos layer is from top to bottom followed successively by
(TEOS), upper oxidation silicon buffer layer (BFOX), metal oxide layer (Hik), silicon layer (Si), silicon oxide dielectric interlayer
(ILDOX), carbon containing silicon nitride layer (NDC), carbon containing silica (BD), carbon containing silicon nitride layer (NDC), carbon containing silica
(BD), carbon containing silicon nitride layer (NDC), carbon containing silica (BD), in middle silicon nitride layer (MSIN), upper oxidation silicon buffer layer
(TPEOX), SiClx layer (BSIN), lower oxidation silicon buffer layer (BPEOX), carbon containing silicon nitride layer (NDC) under nitrogen.Wherein, MSIN
TPEOX between BSIN is tack coat (Bonding layers), and tack coat is 20k oxide.
With continued reference to Fig. 1, from top to bottom TEOS, BFOX, Hik, Si form the first composite bed, from top to bottom ILDOX, NDC,
BD, NDC, BD, NDC, BD form the second composite bed, and the first composite bed, the second composite bed, MSIN and TPEOX are device die portion
Point, i.e. TPEOX and its above are device die；From top to bottom BFEOS, NDC form triplex layer, TPEOX, BSIN and the 3rd
Composite bed is signal operation wafer, i.e. TPEOX and its it is following be signal operation wafer；Have below BSIN and in triplex layer
Metal top layer (TM).
With continued reference to Fig. 1, when carrying out deep via technique based on above-mentioned composite construction, one is etched in advance in the first composite bed
Groove, the ILDOX terminated under groove in the second composite bed upper surface, then to the second composite bed, MSIN, TPEOX, part
BSIN is performed etching to form deep via (DV), is terminated under deep via in the BSIN above TM, mastering hole depth is about
3.7um。
Concretely comprise the following steps：Photoresist layer (PR) is deposited first, in the lower and side wall of PR covering grooves and the first composite bed
TEOS upper surface, PR is provided with etching window, the corresponding DV for finally needing to be formed of the etching window, then using PR as mask
A main etching (ME) is carried out to etch the second composite bed, MSIN and part TPEOX and terminate in TPEOX, is continued using PR to cover
Film carries out an over etching (OE) to etch remaining TPEOX, part BSIN and terminate in the BSIN above TM, is mastered so as to be formed
Hole, finally once cleared up to remove PR.
As shown in Fig. 2 current techniques form DV by the way of ME+OE+ cleanings, during main etching and over etching,
Due to the TPEOX difference in thickness in center wafer (or crystal circle center) and Waffer edge etch-rate difference, different composite structure,
Cause the BSIN of Waffer edge to be first etched to penetrate, and be etched and penetrate after the BSIN of center wafer, so as to be formed in deep via
During produce center to edge load effect (center-to-edge loading effect), and the BSIN of Waffer edge
First being etched to penetrate causes Waffer edge first to expose TM, so as to cause bond failure to cause production loss, and then influences wafer and tests
Acceptance Tests (wafer acceptance testing, WAT) and yield (yield).
The content of the invention
For problems of the prior art, the present invention relates to backside-illuminated sensor manufacturing technology field, there is provided one
Deep via forming method of the kind suitable for composite construction.
The present invention adopts the following technical scheme that：
A kind of deep via forming method, suitable for composite construction, the composite construction is brilliant by device die and signal operation
Formed after member bonding, the device die includes the first composite bed, the second composite bed, the middle silicon nitride from top to bottom set gradually
Layer and cushion, the signal operation wafer include the cushion, the lower silicon nitride layer and the 3rd from top to bottom set gradually
Composite bed, a groove is provided with first composite bed, the channel bottom exposes the upper surface of second composite bed, described
A top-level metallic is provided with lower silicon nitride layer and the triplex layer；The cushion include upper cushion, stop-layer and under
Cushion；
The deep via forming method includes：
Step S1, a photoresist layer is deposited, the photoresist covers the upper surface of first composite bed, the groove
The bottom of side wall and the groove, in being provided for being formed the etching window of deep via on the photoresist layer to be covered as etching
Film；
Step S2, first time main etching is carried out, to etch second composite bed and a part of upper cushion and stop
In the upper cushion；
Step S3, first time over etching is carried out, to etch upper cushion and the stop-layer described in another part and terminate in
The upper surface of the bottom breaker；
Step S4, second of main etching is carried out, to etch a part of bottom breaker and terminate in the bottom breaker；
Step S5, second of over etching is carried out, to etch bottom breaker described in another part and a part of lower nitridation
Silicon layer is simultaneously terminated in another above the top metal lower silicon nitride layer, to form the deep via.
Preferably, the cushion is oxidation silicon buffer layer.
Preferably, the first composite bed includes the teos layer, upper oxidation silicon buffer layer, gold from top to bottom set gradually
Belong to oxide skin(coating) and silicon layer.
Preferably, the second composite bed include from top to bottom set gradually silicon oxide dielectric interlayer, carbon containing upper nitridation
It is silicon layer, carbon containing upper silicon oxide layer, carbon containing middle silicon nitride layer, carbon containing middle silicon oxide layer, carbon containing upper silicon oxide layer, carbon containing
Lower silicon nitride layer, carbon containing lower silicon oxide layer.
Preferably, the triplex layer includes the lower oxidation silicon buffer layer from top to bottom set gradually and carbon containing bottom
Silicon nitride layer.
Preferably, the deep via forming method also includes：
Step S6, first dressing is carried out, to remove the photoresist layer.
Preferably, in the step S2, when carrying out first time main etching, etch rate 4K/min.
Preferably, in the step S3, when carrying out first time over etching, etch rate 2.5K/min.
Preferably, in the step S4, when carrying out second of main etching, etch rate 4K/min.
Preferably, in the step S5, when carrying out second of over etching, etch rate is more than 2.5K/min.
Preferably, in the step S5, after carrying out second of over etching, the thickness of the lower silicon nitride layer is 2500A.
Beneficial effects of the present invention：The present invention can increase buffer layer thickness uniformity by adding stop-layer, reduce erosion
The carving technology time, the influence of center wafer and each deep via speed difference of Waffer edge is reduced, so as to the center of reducing to side
Edge load effect, optimize technique, improve yield.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of deep via forming method in the prior art；
Fig. 2 is the chip schematic diagram formed after deep via in the prior art；
Fig. 3 is the flow chart of deep via forming method in a preferred embodiment of the present invention；
Fig. 4 is the schematic flow sheet of deep via forming method in a preferred embodiment of the present invention.
Embodiment
It should be noted that in the case where not conflicting, following technical proposals, can be mutually combined between technical characteristic.
The embodiment of the present invention is further described below in conjunction with the accompanying drawings：
As shown in Figure 3-4, a kind of deep via forming method, suitable for composite construction, above-mentioned composite construction is by device die
Formed after being bonded with signal operation wafer, it is the first composite bed that above-mentioned device die includes from top to bottom setting gradually, second multiple
Layer, middle silicon nitride layer and cushion are closed, above-mentioned signal operation wafer includes above-mentioned cushion, the lower nitrogen from top to bottom set gradually
SiClx layer and triplex layer, a groove is provided with above-mentioned first composite bed, and above-mentioned channel bottom exposes above-mentioned second composite bed
Upper surface, be provided with a top-level metallic in above-mentioned lower silicon nitride layer and above-mentioned triplex layer；Above-mentioned cushion includes upper buffering
Layer 13, stop-layer 14 and bottom breaker 15；
Above-mentioned deep via forming method includes：
Step S1, a photoresist layer 20 is deposited, above-mentioned photoresist 20 covers the upper surface of above-mentioned first composite bed, above-mentioned ditch
The bottom of the side wall of groove and above-mentioned groove, in be provided for being formed on above-mentioned photoresist layer 20 etching window of deep via using as
Etch mask；
Step S2, first time main etching ME1 is carried out, to etch above-mentioned second composite bed and a part of above-mentioned upper cushion 13
And terminate in above-mentioned upper cushion 13；
Step S3, first time over etching OE1 is carried out, to etch the above-mentioned upper cushion 13 of another part and above-mentioned stop-layer 14
And terminate in the upper surface of above-mentioned bottom breaker 15；
Step S4, second of main etching ME2 is carried out, to etch a part of above-mentioned bottom breaker 15 and terminate in above-mentioned lower buffering
In layer 15；
Step S5, carry out second of over etching OE2, with etch the above-mentioned bottom breaker 15 of another part and it is a part of it is above-mentioned under
Silicon nitride layer 16 is simultaneously terminated in another above above-mentioned top metal 19 above-mentioned lower silicon nitride layer 16, to form above-mentioned depth
Through hole.
In the present embodiment, buffer layer thickness uniformity can be increased by adding stop-layer, reduce the etch process time,
The influence of each deep via speed difference of center wafer and Waffer edge is reduced, so as to the center of reducing to edge load effect,
Optimize technique, improve yield.
ME1+OE1 stops in middle SIN, balanced load, and OE2 is selectively dropped to down using high oxide/SIN with cube
SIN。
Addition buffering area SIN can increase OX thickness evenness, reduce the etch process time, reduce center wafer and edge
Each speed difference influence.Therefore, center is reduced to the load effect at edge.Optimize technique, improve yield.
In a specific embodiment, when carrying out first time main etching ME1, about 5K oxide layers, Pattern ER (figures are retained
Case etch rate) about 4K/min；
After carrying out first time over etching OE1, the 5K oxide layers of residual are removed, Pattern ER are more than 2.5K/min；
When carrying out second of main etching ME2, retain about 5K oxide layers, Pattern ER about 4K/min；
After carrying out second of over etching OE2, remove the 5K oxide layers of residual and stop on 2500A SIN, Pattern
ER is more than 2.5K/min.
In preferred embodiment, above-mentioned cushion is oxidation silicon buffer layer.
In preferred embodiment, the first composite bed includes teos layer 1, the upper silica from top to bottom set gradually
Cushion 2, metal oxide layer 3 and silicon layer 4.
In preferred embodiment, the second composite bed includes the silicon oxide dielectric interlayer 5, carbon containing from top to bottom set gradually
Upper silicon nitride layer 6, carbon containing upper silicon oxide layer 7, carbon containing middle silicon nitride layer 8, carbon containing middle silicon oxide layer 9, carbon containing upper
Silicon oxide layer 10, carbon containing lower silicon nitride layer 11, carbon containing lower silicon oxide layer 12.
In preferred embodiment, above-mentioned triplex layer include the lower oxidation silicon buffer layer 17 that from top to bottom sets gradually and
Carbon containing base silicon nitride layer 18.
In preferred embodiment, above-mentioned deep via forming method also includes：
Step S6, first dressing is carried out, to remove above-mentioned photoresist layer 20.
In preferred embodiment, in above-mentioned steps S2, when carrying out first time main etching, etch rate 4K/min.
In preferred embodiment, in above-mentioned steps S3, when carrying out first time over etching, etch rate 2.5K/min.
In preferred embodiment, when carrying out second of main etching, etch rate 4K/min.
In preferred embodiment, when carrying out second of over etching, etch rate is more than 2.5K/min.
In preferred embodiment, after carrying out second of over etching, the 2500A of the thickness of above-mentioned lower silicon nitride layer.
By explanation and accompanying drawing, the exemplary embodiments of the specific structure of embodiment are given, it is smart based on the present invention
God, it can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading described above, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.Weighing
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (11)
1. a kind of deep via forming method, suitable for composite construction, the composite construction is by device die and signal operation wafer
Formed after bonding, the device die includes the first composite bed, the second composite bed, the middle silicon nitride layer from top to bottom set gradually
And cushion, the cushion that the signal operation wafer includes from top to bottom setting gradually, lower silicon nitride layer and the 3rd are multiple
Layer is closed, a groove is provided with first composite bed, the channel bottom exposes the upper surface of second composite bed, under described
A top-level metallic is provided with silicon nitride layer and the triplex layer；Characterized in that, the cushion includes upper cushion, stopped
Only layer and bottom breaker；
The deep via forming method includes：
Step S1, a photoresist layer is deposited, the photoresist covers the upper surface of first composite bed, the side wall of the groove
And the bottom of the groove, in being provided for being formed the etching window of deep via on the photoresist layer to be used as etch mask；
Step S2, first time main etching is carried out, to etch second composite bed and a part of upper cushion and terminate in institute
State in cushion；
Step S3, first time over etching is carried out, to etch upper cushion and the stop-layer described in another part and terminate in described
The upper surface of bottom breaker；
Step S4, second of main etching is carried out, to etch a part of bottom breaker and terminate in the bottom breaker；
Step S5, second of over etching is carried out, to etch bottom breaker described in another part and a part of lower silicon nitride layer
And terminate in another above the top metal lower silicon nitride layer, to form the deep via.
2. method according to claim 1, it is characterised in that the cushion is oxidation silicon buffer layer.
3. method according to claim 1, it is characterised in that the first composite bed includes the positive silicic acid second from top to bottom set gradually
Ester layer, upper oxidation silicon buffer layer, metal oxide layer and silicon layer.
4. method according to claim 1, it is characterised in that the second composite bed includes the silica electricity from top to bottom set gradually
Medium interlayer, carbon containing upper silicon nitride layer, carbon containing upper silicon oxide layer, carbon containing middle silicon nitride layer, carbon containing middle silicon oxide layer,
Carbon containing upper silicon oxide layer, carbon containing lower silicon nitride layer, carbon containing lower silicon oxide layer.
5. method according to claim 1, it is characterised in that the triplex layer includes the lower oxygen from top to bottom set gradually
SiClx cushion and carbon containing base silicon nitride layer.
6. method according to claim 1, it is characterised in that the deep via forming method also includes：
Step S6, first dressing is carried out, to remove the photoresist layer.
7. method according to claim 1, it is characterised in that in the step S2, when carrying out first time main etching, etch rate
For 4K/min.
8. method according to claim 1, it is characterised in that in the step S3, when carrying out first time over etching, etch rate
For 2.5K/min.
9. method according to claim 1, it is characterised in that in the step S4, when carrying out second of main etching, etch rate
For 4K/min.
10. method according to claim 1, it is characterised in that in the step S5, when carrying out second of over etching, etching speed
Rate is more than 2.5K/min.
11. method according to claim 1, it is characterised in that in the step S5, after carrying out second of over etching, under described
The thickness of silicon nitride layer is 2500A.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111599793A (en) * | 2020-05-25 | 2020-08-28 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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