CN111326426A - Method for filling groove and controlling warping degree of silicon wafer and semiconductor device - Google Patents

Method for filling groove and controlling warping degree of silicon wafer and semiconductor device Download PDF

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Publication number
CN111326426A
CN111326426A CN201811544857.4A CN201811544857A CN111326426A CN 111326426 A CN111326426 A CN 111326426A CN 201811544857 A CN201811544857 A CN 201811544857A CN 111326426 A CN111326426 A CN 111326426A
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dielectric layer
silicon wafer
layer
metal layer
groove
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颜毅林
刘龙平
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Advanced Semiconductor Manufacturing Co ltd
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Advanced Semiconductor Manufacturing Co ltd
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Priority to CN201811544857.4A priority Critical patent/CN111326426A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a method for filling a groove and controlling the warping degree of a silicon wafer and a semiconductor device, wherein the method is used for manufacturing the semiconductor device with a groove structure and comprises the following steps: manufacturing a back seal on the back of the silicon wafer; forming a stress buffer layer, wherein the stress buffer layer covers the bottom surface and the side wall of the first groove and covers the upper surface of the first metal layer; performing HDP deposition on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer; PETEOS deposition is carried out on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer; the stress buffer layer, the first intermetallic dielectric layer and the second intermetallic dielectric layer form an intermetallic dielectric layer. The method can effectively reduce the warping degree of the silicon wafer, ensure the complete filling of the groove, avoid the risk of wafer transmission, slip sheets and even fragments, and improve the yield of semiconductor device manufacturing.

Description

Method for filling groove and controlling warping degree of silicon wafer and semiconductor device
Technical Field
The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a method for filling a groove and controlling the warping degree of a silicon wafer and a semiconductor device.
Background
In the manufacturing process of a semiconductor device having a trench structure, a silicon wafer is easily warped. Fig. 1-6 illustrate the fabrication flow of a 0.35 micron BiCMOS (a semiconductor device process) device. Fig. 1 shows a silicon wafer 101 as a substrate. As shown in fig. 2, an interlayer dielectric layer 102 is formed on the front surface of the silicon wafer 101, and the interlayer dielectric layer 102 is silicon dioxide. Then, referring to fig. 3, a first metal layer 103 is formed, and the first metal layer 103 is patterned and etched to form a first trench 104. Then, HDP (high density plasma) deposition is performed, PETEOS (plasma enhanced orthosilicate) deposition is performed, CMP (Chemical Mechanical Polishing) is performed, as shown in fig. 4, an inter-metal dielectric layer 105 is formed, and the inter-metal dielectric layer 105 fills the first trench 104. Next, as shown in fig. 5, a second metal layer 106 is formed, and the second metal layer 106 is patterned and etched to form a second trench 107. Finally, referring to fig. 6, a passivation layer 108 is fabricated. Fig. 1-6 are merely schematic representations of how the wafer 101 may warp upward as shown in fig. 7 during actual fabrication. The warpage of the silicon wafer 101 is related to the thicknesses of the interlayer dielectric layer 102, the first metal layer 103, the intermetal dielectric layer 105, the second metal layer 106 and the passivation layer 108. The greater the thicknesses of the interlayer dielectric layer 102, the first metal layer 103, the intermetallic dielectric layer 105, the second metal layer 106 and the passivation layer 108 are, the greater the warpage of the silicon wafer 101 is. The warping degree refers to the difference between the maximum distance and the minimum distance between the central plane and the reference plane of the silicon wafer in an unclamped state. Warp is measured according to ASTM Std F-657-80, a standard test method of the American society for testing and materials.
The power device generally requires relatively thick interlayer dielectric layers, inter-metal dielectric layers, metal layers and passivation layers, for example, the thickness of the interlayer dielectric layers is up to 3 microns, and the thickness of the metal layers is up to 2 microns. The problem caused by the thick dielectric layer is that the warping degree of the silicon wafer is large, so that subsequent processes such as photoetching, etching, thin film deposition and the like are influenced. Moreover, the thicker metal layer can cause gaps to easily appear when the HDP layer is deposited and the trench is filled.
That is, the thick interlevel dielectric and metal layers cause the following problems when HDP layer deposition is performed:
first, the thick interlayer dielectric layer and the metal layer are easy to generate large stress, so that the warping degree of the silicon wafer is large. In the film deposition process, especially the process with high requirements on warpage of the silicon wafer and particles (particles) on the back of the silicon wafer like HDP, the risk of alarming, sliding of the silicon wafer and even chipping of the silicon wafer is easy to occur in the processes of wafer transmission and HDP. The warping of the silicon wafer also tends to result in uneven or insufficient backside cooling during HDP and thus melting of the metal layer.
Second, a thick metal layer results in a corresponding increase in the thickness of the intermetal dielectric layer, which also makes trench filling more difficult.
Disclosure of Invention
The invention aims to overcome the defects that in the prior art, when a semiconductor device with a groove structure is manufactured, the warping of a silicon wafer is serious, the groove filling is difficult, and the yield of the semiconductor device is influenced, and provides a method for filling the groove and controlling the warping degree of the silicon wafer and the semiconductor device.
The invention solves the technical problems through the following technical scheme:
a method for filling a groove and controlling the warping degree of a silicon wafer is used for manufacturing a semiconductor device with a groove structure, the semiconductor device comprises a first metal layer, a second metal layer and an intermetallic dielectric layer, the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, the intermetallic dielectric layer comprises a first filling part, and the first filling part fills the first groove;
the method comprises the following steps:
manufacturing a back seal on the back of the silicon wafer;
forming a stress buffer layer, wherein the stress buffer layer covers the bottom surface and the side wall of the first groove and covers the upper surface of the first metal layer; performing HDP deposition on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer; PETEOS deposition is carried out on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer; the stress buffer layer, the first intermetallic dielectric layer and the second intermetallic dielectric layer form an intermetallic dielectric layer.
Preferably, after the stress buffer layer is formed, the bending degree of the silicon wafer has an absolute value of not more than 100 micrometers. The curvature refers to the degree of concavity or convexity of the whole silicon wafer in a state that the silicon wafer is not clamped or placed on a vacuum chuck. The tortuosity is in microns and can be measured according to ASTM Std F-534-84, a Standard test method of the American society for testing and materials.
Preferably, the step of forming the stress buffer layer includes: PETEOS deposition was performed to form a stress buffer layer.
Preferably, the back seal is a composite film of oxide and nitride.
Preferably, the thickness of the composite film layer is no greater than 10 microns.
Preferably, after the step of forming the back seal on the back side of the silicon wafer, the method further comprises the steps of:
manufacturing an interlayer dielectric layer on the front side of the silicon wafer;
and manufacturing a first metal layer on the upper surface of the interlayer dielectric layer.
Preferably, the thickness of the interlayer dielectric layer is 2-5 microns; the thickness of the first metal layer is 1-3 microns.
Preferably, after forming the second intermetal dielectric layer, the method further includes the steps of:
and carrying out chemical mechanical polishing on the second intermetallic dielectric layer.
Preferably, after the step of chemically and mechanically polishing the second intermetal dielectric layer, the method further comprises the steps of:
manufacturing a second metal layer, wherein the second metal layer comprises a second groove;
and manufacturing a passivation layer, wherein the passivation layer comprises a second filling part, and the second filling part fills the second groove.
The invention also provides a semiconductor device, which comprises a first metal layer, a second metal layer and an intermetallic dielectric layer, wherein the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, the intermetallic dielectric layer comprises a first filling part, and the first filling part fills the first groove;
the semiconductor device is manufactured by the method for filling the groove and controlling the warping degree of the silicon wafer.
The positive progress effects of the invention are as follows: the method can effectively reduce the warping degree of the silicon wafer, ensure the complete filling of the groove, avoid the risk of wafer transmission, slip sheets and even fragments, and improve the yield of semiconductor device manufacturing.
Drawings
Fig. 1 is a schematic diagram of a silicon wafer in a process for manufacturing a semiconductor device having a trench structure according to the prior art.
Fig. 2 is a schematic diagram of a step of forming an interlayer dielectric layer in a process for forming a semiconductor device having a trench structure according to the prior art.
Fig. 3 is a schematic diagram of a step of manufacturing a first metal layer in a flow for manufacturing a semiconductor device having a trench structure according to the prior art.
Fig. 4 is a schematic diagram of a step of fabricating an intermetal dielectric layer in a process flow for fabricating a semiconductor device having a trench structure according to the prior art.
Fig. 5 is a schematic diagram of a step of manufacturing a second metal layer in a flow for manufacturing a semiconductor device having a trench structure according to the prior art.
Fig. 6 is a schematic diagram of a step of fabricating a passivation layer in a flow for fabricating a semiconductor device having a trench structure according to the prior art.
Fig. 7 is a schematic diagram of a warp state of a silicon wafer of a semiconductor device manufactured by a process for manufacturing a semiconductor device having a trench structure according to the prior art.
Fig. 8 is a flowchart of a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the present invention.
Fig. 9 is a schematic diagram illustrating a step of fabricating a back seal according to a method for trench filling and controlling warpage of a silicon wafer in accordance with a preferred embodiment of the present invention.
Fig. 10 is a schematic diagram of the warpage state of the silicon wafer after the step of fabricating the back seal of the method for trench filling and controlling the warpage of the silicon wafer according to the preferred embodiment of the invention.
Fig. 11 is a schematic diagram illustrating a step of fabricating an interlayer dielectric layer in a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Fig. 12 is a schematic diagram illustrating a step of manufacturing a first metal layer in a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Fig. 13 is a schematic diagram illustrating a step of fabricating a stress buffer layer in a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Fig. 14 is a schematic diagram illustrating a step of fabricating a first intermetal dielectric layer in a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Fig. 15 is a schematic diagram illustrating a step of fabricating a second intermetal dielectric layer in a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Fig. 16 is a schematic diagram illustrating a step of manufacturing a second metal layer in the method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Fig. 17 is a schematic diagram illustrating a step of fabricating a passivation layer in a method for trench filling and controlling warpage of a silicon wafer according to a preferred embodiment of the invention.
Detailed Description
The present invention is further illustrated by the following preferred embodiments, but is not intended to be limited thereby.
The present embodiment provides a method for trench filling and controlling warpage of a silicon wafer, the method being used for manufacturing a semiconductor device having a trench structure, and referring to fig. 8, the method for trench filling and controlling warpage of a silicon wafer of the present embodiment includes the following steps:
step S301, manufacturing a back seal on the back of the silicon wafer. Fig. 9 shows a state where a back seal 201 is formed on the back surface of the silicon wafer 101. Fig. 9 is merely an illustration, and after forming the finished back seal 201, the silicon chip 101 actually warps downward as shown in fig. 10. The degree of downward warpage of the silicon die 101 is related to the thickness of the back seal 201. In the present embodiment, the back seal 201 is a composite film of oxide and nitride. The thickness of the composite film layer is not more than 10 microns. The silicon wafer 101 is warped downward in this step, and the degree of upward warping of the silicon wafer 101 at the time of completion of fabrication of the semiconductor device can be reduced.
Step S302, an interlayer dielectric layer is manufactured on the front side of the silicon wafer. Referring to fig. 11, an interlayer dielectric layer 102 is formed on the front surface of a silicon wafer 101. The thickness of the interlayer dielectric layer is 2-5 microns.
Step 303, a first metal layer is formed on the upper surface of the interlayer dielectric layer. Referring to fig. 12, a metal layer is formed on the top surface of the interlayer dielectric layer 102, patterned, and etched to form a first trench 104, so as to form a first metal layer 103. The thickness of the first metal layer is 1-3 microns.
Step S304, forming a stress buffer layer, wherein the stress buffer layer covers the bottom surface and the side wall of the first groove and covers the upper surface of the first metal layer. Referring to fig. 13, PETEOS deposition is performed to form a stress buffer layer 202. After the stress buffer layer 202 is formed, the degree of downward warping of the silicon wafer 101 is reduced, so that the subsequent manufacturing of the intermetallic dielectric layer can be facilitated, and the filling part of the first trench 104 is prevented from being completed and forming a gap. In other optional embodiments of this embodiment, after forming the stress buffer layer, the silicon wafer has a bow with an absolute value of not more than 100 μm, that is, the silicon wafer is in a state of slight downward warpage, flatness, and slight upward warpage.
Step S305, performing HDP deposition on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer. Referring to fig. 14, HDP deposition is performed on the upper surface of the stress buffer layer 202 to form a first intermetal dielectric layer 203.
Step S306, PETEOS deposition is carried out on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer. As shown in fig. 15, PETEOS deposition is performed on the upper surface of the first intermetal dielectric layer 203 to form a second intermetal dielectric layer 204.
And S307, performing chemical mechanical polishing on the second intermetallic dielectric layer. The stress buffer layer 202, the first intermetal dielectric layer 203 and the second intermetal dielectric layer 204 form an optimized intermetal dielectric layer 205. The optimized intermetal dielectric layer 205 includes a first filling portion that fills the first trench 104.
Step S308, a second metal layer is fabricated, wherein the second metal layer includes a second trench. As shown in fig. 16, a metal layer is deposited on the upper surface of the optimized intermetal dielectric layer 205, patterned, and etched to form a second trench 107, so as to form a second metal layer 106.
Step S309, fabricating a passivation layer, where the passivation layer includes a second filling portion, and the second filling portion fills the second trench. As shown in fig. 17, a passivation layer 108 is formed, and the passivation layer 108 includes a second filling portion, and the second filling portion fills the second trench 107.
The method for filling the groove and controlling the warping degree of the silicon wafer can effectively reduce the warping degree of the silicon wafer, ensures that the groove is completely filled, avoids the risk of transmitting wafers, sliding blades and even fragments, and improves the yield of semiconductor device manufacturing.
The present embodiment further provides a semiconductor device, as shown in fig. 17, the semiconductor device sequentially includes, from bottom to top, a back seal 201, a silicon wafer 101, an interlayer dielectric layer 102, a first metal layer 103, an optimized inter-metal dielectric layer 205, a second metal layer 106, and a passivation layer 108.
A first trench 104 is disposed on the first metal layer 103. The optimized intermetal dielectric layer 205 is composed of a stress buffer layer 202, a first intermetal dielectric layer 203 and a second intermetal dielectric layer 204. The optimized intermetal dielectric layer 205 includes a first filling portion that fills the first trench 104.
A second trench 107 is disposed on the second metal layer 106. The passivation layer 108 includes a second filling portion filling the second trench 107.
The semiconductor device of this embodiment is manufactured by the method for filling the trench and controlling the warpage of the silicon wafer of this embodiment, and detailed description is omitted.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (10)

1. The method for filling the groove and controlling the warping degree of the silicon wafer is characterized by being used for manufacturing a semiconductor device with a groove structure, wherein the semiconductor device comprises a first metal layer, a second metal layer and an intermetallic dielectric layer, the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, the intermetallic dielectric layer comprises a first filling part, and the first filling part fills the first groove;
the method comprises the following steps:
manufacturing a back seal on the back of the silicon wafer;
forming a stress buffer layer, wherein the stress buffer layer covers the bottom surface and the side wall of the first groove and covers the upper surface of the first metal layer; performing HDP deposition on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer; PETEOS deposition is carried out on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer; the stress buffer layer, the first intermetallic dielectric layer and the second intermetallic dielectric layer form the intermetallic dielectric layer.
2. The method for trench filling and controlling the warp of a silicon wafer as claimed in claim 1, wherein the bow of the silicon wafer after forming the stress buffer layer has an absolute value of no more than 100 microns.
3. The method for trench filling and controlling warpage in a silicon wafer of claim 1, wherein the step of forming a stress buffer layer comprises: PETEOS deposition is performed to form the stress buffer layer.
4. The method for trench filling and controlling warpage in a silicon wafer of claim 1, wherein the back seal is a composite film of oxide and nitride.
5. The method for trench filling and controlling warpage of a silicon wafer of claim 4, wherein the thickness of the composite film layer is not greater than 10 microns.
6. The method for trench filling and controlling warpage of a silicon die of claim 1, wherein after the step of forming a back seal on the back side of the silicon die, the method further comprises the steps of:
manufacturing an interlayer dielectric layer on the front side of the silicon wafer;
and manufacturing the first metal layer on the upper surface of the interlayer dielectric layer.
7. The method for trench filling and controlling warpage of a silicon wafer as claimed in claim 6, wherein the thickness of the interlevel dielectric layer is 2-5 μm; the thickness of the first metal layer is 1-3 microns.
8. The method for trench filling and controlling warpage of a silicon wafer of claim 1, wherein after forming the second intermetal dielectric layer, the method further comprises:
and carrying out chemical mechanical polishing on the second intermetallic dielectric layer.
9. The method for trench filling and silicon wafer warp control as claimed in claim 8 wherein after the step of chemical mechanical polishing the second intermetal dielectric layer, the method further comprises the steps of:
manufacturing the second metal layer, wherein the second metal layer comprises a second groove;
and manufacturing a passivation layer, wherein the passivation layer comprises a second filling part, and the second filling part fills the second groove.
10. The semiconductor device is characterized by comprising a first metal layer, a second metal layer and an intermetallic dielectric layer, wherein the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, the intermetallic dielectric layer comprises a first filling part, and the first filling part fills the first groove;
the semiconductor device is manufactured by the method for filling the groove and controlling the warping degree of the silicon wafer according to any one of claims 1 to 9.
CN201811544857.4A 2018-12-17 2018-12-17 Method for filling groove and controlling warping degree of silicon wafer and semiconductor device Pending CN111326426A (en)

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CN103633012A (en) * 2012-08-13 2014-03-12 上海华虹宏力半导体制造有限公司 Method for improving silicon chip warping degree
CN106548941A (en) * 2015-09-18 2017-03-29 北大方正集团有限公司 A kind of semiconductor device and preparation method thereof

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US8030172B1 (en) * 2000-09-12 2011-10-04 Cypress Semiconductor Corporation Isolation technology for submicron semiconductor devices
CN101030567A (en) * 2007-04-06 2007-09-05 上海集成电路研发中心有限公司 Construction of rear-channel connected medium stacked layer
CN101183661A (en) * 2007-12-13 2008-05-21 上海集成电路研发中心有限公司 Post-channel interconnection implementing method for balancing stress of silicon chip
CN101226895A (en) * 2007-12-21 2008-07-23 上海宏力半导体制造有限公司 Method for manufacturing shallow groove isolation structure
CN102354664A (en) * 2011-09-28 2012-02-15 上海宏力半导体制造有限公司 Intermetallic dielectric layer forming method and semiconductor device
CN103035520A (en) * 2012-08-13 2013-04-10 上海华虹Nec电子有限公司 Manufacture method for insulated gate bipolar transistor (IGBT) device
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