TW201218289A - Low-temperature bonding process - Google Patents

Low-temperature bonding process Download PDF

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Publication number
TW201218289A
TW201218289A TW100118741A TW100118741A TW201218289A TW 201218289 A TW201218289 A TW 201218289A TW 100118741 A TW100118741 A TW 100118741A TW 100118741 A TW100118741 A TW 100118741A TW 201218289 A TW201218289 A TW 201218289A
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Taiwan
Prior art keywords
temperature
substrate
adhesion
combination
tempering
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TW100118741A
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English (en)
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TWI459480B (zh
Inventor
Gweltaz Gaudin
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Soitec Silicon On Insulator
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Publication of TW201218289A publication Critical patent/TW201218289A/zh
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    • H01L2924/1461—MEMS

Description

201218289 六、發明說明： 【發明所屬之技術領域】 本發明係關於在低溫下一板體或晶片之第一底材與一板體或晶片 之第二底材之黏附。本發明欲獲取即使在低溫下仍具有最佳品質及最佳 黏附能量之黏附。 本發明尤其可以應用於複合底材製造之領域或元件之三度空間集 積（3D integration)。更一般而言，當一構造因元件之存在或因材料之本 質，而無法施以高溫熱處理時，本發明可應用於經由直接（或「分子」） 黏附而形成該構造。 本發明優先適用於無法耐受高處理溫度之構造，尤其是因待組合之 組件中有元件或電路或微元件存在者。 【先前技術】 C.S. Tan 專人所編者之《wafer ievei 3-D ICs Process technology》一 書（ρ.197-217)提出了對3D科技的回顧。該書揭示一黏附製程其包 括在低/皿下/儿積一黏附層，以及在一高於此氧化物之沉積溫度下，對此 氧化物進行除氣回火。 該技術使用時’可觀察到黏附界面出現缺陷。這些缺陷可能轉而對 黏附能量有不利影響。 因此’找出-種新穎方法，以實現在低溫下經由細層組合兩個組 件之問題’便由此而產生。 【發明内容】 本發明首先與-種將一第一組件與一第二組件組合之製程有關唭 中第、件匕括至少一第一底材或至少一晶片，第二組件包括至少一第 二底材’該製程包括： 201218289 a) 於每一底材上形成一表面黏附層，該些黏附層至少其中之一形成 的溫度低於或等於300oC ; b) 在組合前對該些黏附層進行一第一回火，稱為除氣回火，除氣回 火至少部分期間之溫度至少等於後續之黏附界面強化溫度（Tr)，但低於 450°C ； c) 將該些黏附層之曝露表面互相接觸以組合底材， d) 在一低於450。(：之黏附界面強化溫度（Tr)下，對組合後之構造 施行回火。 該二黏附層至少其中之一可以應用沉積方式形成，例如，pECVD 或LPCVD形態之沉積。 該些黏附層至少其中之一可為氧化物或氮化物形態，例如，矽氧化 物Si〇2或矽氮化物Si3N4。 回火步驟b)可以包括： -產生一溫度斜坡’以便將溫度自環境溫度逐漸提高到至少等於組 合後回火之溫度； -及/或在一段時間内，例如介於1〇或3〇分鐘至2或5小時之間， 將溫度保持在至少等於後續之黏附界面強化溫度（Tr)，但低於45〇〇c。 根據本發明之一種製程可以額外包括，在步驟c)或步驟b)之前整 備該些多孔表面層之表面之一步驟，以便進行組合步驟。 、 步驟c)之組合，舉例而言，為分子附著形態。 該第-底材或晶片及該第二底材至少其中之__可以包括一個或多 個元件。 根據本發明之-種製程，其可以更另亦包括在組合步驟c)之前，對 其中之-的底材進订個別切割之一步驟，以形成所要與另一底材組合之 一個或多個晶片。 該些底材或晶片’至少其中之—有部分可為—種半導體材料所製， 例如為矽製。 4 201218289 本發明亦與-異質構造有關，其包括一第_組件及—第二組件，該 第組件包括至少-第一底材或至少一晶片，該第二組件包括至少一第 二底材’每—組件包括—多孔表面層，麟黏附層，該二組件係經由黏 附層而組合，其組合具有至少等於3 了/m2之—黏附能量。 該些黏附層至少其中之—可為氧化物或氮化物形態 ，例如，矽氧化 物或矽氮化物。 該些底材或晶片，至少其中之一有部分可為一種半導體材料所製， 例如為石夕製。 較佳情況者為，該些黏附層間之組合為分子附著形態。 更佳情況者為’該第一底材或晶片及該第二底材至少其中之一包括 一個或多個元件。 【實施方式】 本發明之第一個說明性質實施例呈現於圖1入至1C。 一黏附層，此處為一薄氧化物層4，形成於一第一底材2的表面上 (圖1A) ’該底材，舉例而言，為一種半導體材料所製，較有利者為石夕 或氧化銘（Al2〇3)或玻璃或鍺所製。該黏附層係在低於3〇〇〇c之低溫下 形成。該氧化物為，舉例而言，矽氧化物Si〇2，其一種沉積技術可為 PECVD技術。一前驅氣體，舉例而言，可以是teos (四乙氧基矽院） 或SiH4或N2形態。 該氧化物層具有一厚度el韻厚度舉例而言介於2〇〇nm及4μπι 之間。該底材2含有能提供一項或多項電力或電子或其他功能之裝置， 該些裝置於此統一以編號6表示，例如，一個或多個電子及/或光學元件， 及/或一個或多個MEMS及/或NEMS。 另一黏附層，此處為一薄氧化物層14，形成於一第二底材12上（圖 出）’該底材’舉例而言，為一種半導體材料所製，同前，較有利者為 201218289 矽或玻璃或鍺所製。該黏附層係在低於300°C之低溫下形成《該氧化物 為，舉例而言，矽氧化物Si〇2，其一種沉積技術可為PECVD技術。一 前驅氣體可為上文已指出之氣體之一。該氧化物層具有一厚度e2，該厚 度’舉例而言’介於200nm及4μιη之間。該底材12亦可選擇性地含有 能提供一項或多項電力或電子或其他功能之裝置，該些裝置於此統一以 編號16表示，例如，一個或多個電子及/或光學元件，及/或一個或多個 MEMS 及/或 NEMS。 經沉積獲得之該些黏附層4、14均為多孔，且不是很緻密。 一般而言，在根據本發明之一種製程中，由於元件6、16存在於一 底材及/或另一底材中，因此溫度被保持在低於450〇(：，或甚至低於 400°C。就形成黏附層之步驟而言，此條件得到遵守，因為如上文所指出， 該步驟係在低於250。(：或300°C或350°C的溫度下進行。 該些黏附層4、14均可以沉積方式形成，例如LpcvD或pECVD 形態之沉積。 在組合該一底材前，先對該些黏附層4、14施行第一回火。在此第 -回火期間’該些黏附層4及14承受的溫度至少達到溫度Tr，該溫度將 在底材組合後’接著用於進行黏附界面之強化。由於元件6、16之存在， 此強化溫度Tr本身低於可使用之最高溫度τ眶，例如4〇〇〇c或4默。 例如，溫度按照-溫度斜坡逐漸上升，從環境溫度上升至至少達到 該強化溫度Tr ’或達到高於強化溫度但低於可使用最高溫度 溫度》 圖2A呈現-溫度斜坡範例，其中，溫度非常穩定地攀升，舉例而 吕’以介於l0C/mm及若干〇c/min之間的坡度，例如介於1〇c/min及 5 C/mm t間’達到強化溫度，例如35〇£)(：，然後保持在此溫度丁圹數 小時。 根據-變化作法’即以虛線呈現者，溫度可按照上述坡度增加至— 皿度τ ’該恤雜強化溫度為高，介於強化溫度以最高溫度 6 201218289 之間，而最南溫度τ_，舉例而言，等於4〇〇〇c或45〇〇c。 圖2B呈現;^可能性，其中，溫度迅速增加至強化溫度^後 穩定地保持在此溫度達—小時或更久。根據—變化作法，即讀線呈現 者，溫=速增加至-溫度Τ’，其她t溫度，[為高，介於強化溫度
Tr及最高溫度Tmax之間；而最高溫度Tmax，舉例而言，等於鮮c或 450oC。 圖2C呈現又另-可能性，其中，溫度非常穩定地增加，舉例而言， 以介於PC/min及若干。C/min之間的坡度例如介於π/—及5〇·η 之間’達到強化溫度Tr，例如350〇c，然後保持在此溫度I一段相對短 暫的時間’例如介於10分鐘至2小時之間，然後再逐漸降至環境溫度。 根據-變化作法，即以虛線呈現者，溫度如前述按-非常穩定的坡度增 加’達到-高於強化溫度Tr但低於最高溫度U之溫度τ，，然後保^ 在此/皿度τ -段相對短暫的時間，例如介於⑴分鐘至2小時之間然 後再逐漸降至環境溫度。 … 該些黏附層4、14在組合前進行回火，此一步驟之作用如下。由於 在低溫下沉積的每一黏附層均含有許多污染物，舉例而言，污染物可能 .來自叫〇或碳基鏈結雜的氣態前麟。若不預先加崎除，那麼，在 二底材組合後進行後__界面強化蚊侧，這些污祕报有可能 T遷移（除氣）’並在該二底材敝合界面上形成「氣泡」或其他缺陷。 這類氣泡無法清除，而且會使獲得的組合物變得無法使用。 初步的回火步驟，即上文有關圖2A至2C所說明者，可將這些污 染，源從該些黏附層4、14抽取出來’卻不會導致這些黏附層的多二性 顯著降低。因而，此-步驟可同時保存黏附多孔材料的有利性質。馨於 在底材組合前之初步回火步驟期間所達到的回火溫度，係介於最高溫度 丁咖及黏w界面強化溫度之間，這些污_源絕對會從該些黏:層:、 Η被抽取出來@此’這赌染獅便不會在回火步驟期間造成破 201218289 壞，因為其已在一至少等於強化回火溫度之溫度下預先被抽取出來。 接著（圖ic) ’將經過上述處理的二底材經由該些黏附層4、14 的無污染物表面加以組合。在此組合步驟前，可先進行一預處理步驟， 例如化學機械研磨（chemical mechanical polishing，CMP)。 最後，在低於或等於最高溫度Tmax之強化溫度乃下，對依上述方 式組合好的構造施行回火。 根據本發明之該製程可在界面處獲得品質良好及達到數個J/m2等 級的尚黏附能f，例如大於施2或4施2的雜能量。該製程的採用， 確實達到在細界面上沒有「氣泡」形態之缺関結果。其卿能量之 量、·！舉例而s ’可以採用名為「刮刀技術」（biadetecj^ique)(或「雙 懸臂技術」（double cantilever technique))之技術。 相同原理亦可應用於板體上一個或多個晶片之黏附：在根據本發明 之第一回火之前或之後，裁切其中之一的板體，即足以形成一個或多個 晶片。接著，將這些晶片分別組合在第二板體上。 此範例更詳細呈現於圖3A至3C。 一黏附層，此處為一薄氧化物層4ι，形成於一第一底材2，的表面上 (圖3A) ’該底材’舉綱言’為_種轉聽料所製，較有利者為石夕 或玻璃或鍺所製。 該氧化物層4,形成之方式，與上文有關圖1Α所述之氧化物層4形 成之方式相同（尤其是在相同溫度下）。因此，該氧化物層會具備相同特 性’尤其是多孔性之特性。 該底材接著被裁切為個別之晶片22、24、26、28，如圖3Α中以垂 直虛線示意者。每-個別晶片包括一個或多個電路或元件22,、放、加， 281 ’並被黏附層之一部份4’2、4’4、&、4,8所覆蓋。 圖犯呈現-第二底材，其與上文有關圖1Β所述之底材相同，且 其黏附層係、在與先前已提出之同樣條件下獲得。 接著可依照本發明之上述步驟，舉例而言，根據圖2八至2(：任— 8 201218289 圖式所呈現的圖表之一改變溫度，對每一個別晶片22、24、26、28及圖 3B之底材12，進行組合前之回火熱處理。 回火之後，可將依上述方式處理後之個別晶片及底材12，經由黏 附層4、、4%、4、、4’8及14之無污染物表面加以組合。在此組合步驟前， 可先進行一預處理步驟，例如，對每一個別晶片之黏附層及底材12之黏 附層14，施行化學機械研磨（cmp)。 作為一變化作法’在組合前的回火步驟之後，吾人可將底材2，裁切 為個別晶片22、24、26、28。其他操作均與上文所述者相似。 以下提供一說明性質實施例。 提供一第一板體或底材2 ,及一第二板體或底材12，至少其中之一 包括電路或微元件6、16 »因此’其組構即為上文有關圖ία及1B所述 者。 在每一所要組合之表面上，透過PECVD形態之LTO (低溫氧化形 成）技術，形成Si〇2之黏附層4、14，由矽烷及N20或TMS (三曱基 石夕貌）及N20前驅物開始。 該沉積係在低溫下（低於或等於250。〇進行。此形態之低溫沉積 有助於獲得高黏附能量，因為以此方式形成之氧化物相對多孔及/或具有 低密度。此一特性讓黏附層在底材組合之後，能夠接著吸收被捕捉在黏 附界面上的多餘水分。 接著，依循本發明之製程對該些氧化物施行回火：採用介於 0.1 °C/min及5°C/min間之一溫度斜坡（例如：i〇c/min )，以達到介於350oC 及400°C間之一溫度。該回火在此溫度下持續12小時。相對緩慢的溫度 上升’可確保被該些黏附氧化物4、14納入之污染物種源能夠按其不同 活化能連續除氣。 接著，整備該些板體以便進行組合，先進行表面磨平程序，以提供 一與分子黏附相配之粗度（粗度<0.5 nmRMS)，然後清潔板體；板體清 潔可輔以刷洗待組合之板體表面。 201218289 接著，以「分子」黏附方式進行兩板體之組合，然後讓組合物在不 超過除氣回火溫度之一溫度下進行回火，以免引發那些仍存在於氧化物 中之種源，以及在前述處理期間未被清除之種源，遷移至黏附界面。 經此製程後可獲得約為3.6 J/m2 ’且品質良好之黏附能量：明確地 說，可以注意到黏附界面上沒有「氣泡」形態的缺陷。此黏附能量數值 應與一標準的氧化物/氧化物黏附（亦即，非多孔性/緻密氧化物）所獲得 約為2 J/m2之黏附能量比較。 比較試驗係對在不同溫度下整備，不同形態之氧化物進行。 相應之量測結果整理於圖4。有三種形態的Si〇2氧化物可進行比 較。該些氧化物係以PECVD方式沉積： 1) 第一種為TEOS (四乙氧基矽烷）形態之氧化物，沉積溫度 400°C，沉積速率 I4nm/s ; 2) 第一種為「石夕院氧化物」形態之氧化物，沉積溫度21〇。匚，沉 積速率4.5 nm/s ;及 3) 第二種為「石夕烧氧化物」形態之氧化物，沉積溫度4〇〇〇c，沉 積速率10 nm/s。 黏附能量之補充性量測係針對與上述材料相同，但未經任何強化回 火者而進行：這些量測在圓4中以「未經強化回火」表示。其量測值相 當於在尚未進行強化回火的情況下所量測之黏附能量。 從前文所述條件可知，只有第二種氧化物是在低於25*〇〇c的溫度 下沉積。 除以「未經強化回火」表示者外，圖4中其他圖表呈現之γ值（單 位為mJ/m )係等於當黏附能量（γ軸）作為強化回火溫度Tr (X軸） 的函數時’這二種材料獲得之黏雜量的—半。強化回火溫度1在2〇〇〇c 到400°C之間變化。 可以觀察到第二種材料（LTOB，圖表中淺灰色者）的黏附能量比 第-種材料（TEOS，圖表中深灰色者）獲得的黏附能量至少大兩倍，而 201218289 且幾乎是第三種材料（矽烷氧化物，圖表中白色者）所獲得之黏附能量 的三倍。 而且’不論強化回火溫度Tr為何（200oC，350°C或400〇C)，第二 種氧化物所顯示的卓越黏附優勢均明顯可見。只有在「未經強化回火」 的情況下，三種材料的黏附能量沒有差異。 因此，這些試驗顯示，低溫沉積可使沉積氧化物獲得一定程度的多 孔性，比經由高溫pECVD獲得的多孔性為低。 此外，在沒有強化回火的情況下，黏附能量始終很低。 因此’吾人可清楚看到，在低溫下形成黏附層，結合在低於45〇〇c 的強化溫度下施行強化回火，可產生品質良好的高能量黏附。如上文所 指出，黏附能量等於所測得參數γ值的兩倍：因此，此處的黏附能量確 實達到了至少3J/m2。 在圖4這些圖表中，吾人可發現，在溫度4〇〇〇c下沉積之該些材 料，其黏附能量之程度與C.S.Tan等人在2003年發表於期刊Appiied
Physics Letters, Vol.82, No· 116, p.2649-265卜題為〈Low temperature thermal oxide to plasma-enhanced chemical vapor deposition oxide wafer bonding for thin film transfer application >文件中圖3所呈現的黏附能量程 度相同。在此文件中，該些氧化物層亦是在400Τ:的溫度下沉積。 因此，圖4所呈現的比較試驗結果，明顯與從習知技術得知之數據 【圖式簡單說明】 圖1Α至1C呈現一根據本發明之一種製程之實施例。 圖2Α至2C呈現依照本發明，在組合前處理黏附層之一步驟期間，不同 溫度變化之示意圖。 圖3Α至3C呈現根據本發明之一種製程之—變化作法。 圖4呈現在比較試驗的情況下進行量測之結果。 11 201218289 【主要元件符號說明】 2、2,、12 底材 4、4,、4’2、4,4、4,6、4’8、14 薄氧化物層 6、16、22’、24,、26,、28， 元件 22、24、26、28 晶片 12

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  1. 201218289 七、申請專利範圍： 1. 一種組合一第一組件與一第二組件之贺栽^ •至少一第一底材⑵或至少一晶片（22 2製 至少-第二底材（12)，該製程包括： 28)，該第一組件包括 a) 於每一底材上形成一表面層（4、4,2、4,4、^、4,、Ml， 附層，該些黏附層至少其中之一是在低於或等於j 為黏 b) 在組合前對該些黏附層進行第一回火， 翁^ ’ 4至5^部;分細之溫度至少等於後續之 以組合c=_刪（4、4,2、4’4、4,6、&、⑷之曝露表面互相接觸 .行回火Φ在一低於伙义之黏附界面強化溫度巾）下，對組合後之構造施 謂程’其中，該些軸層至少其中之一係 -為氧3化iStS第1或2項之製程，其中’該些黏嘛少其中之 矽氧^物t申清專利範圍第3項之製程，其中’該些黏附層至少其中之-為 -係程，其中，該些黏附層至少其中之 為低於64〇ti請專利範圍第1至5項之製程，其中，黏附界面強化溫度（το 7.如肀請專利範圍第1至6項其中一Jg夕制如.t ϊίίΞ_ 包減生—_坡，· 造組合8前之製程，其卜步驟b)之構 之間，將溫度保持在至少等於後續之黏匕 9·如申請專利範圍第1至8 jgAtb τΕλΑΙ c)或步驟b)之•，整備該些多孔之^，其額外包括在步驟 印層之表面之一步驟，以便進行組合步驟。 13 201218289 合為分子利範圍第1至9項其中一項之製程，其中，步驟C)之組 或晶片之製程，其中，該第-底材 26,、28，）。-何其中之一包括一個或多個元件（6、16、22,、24,， c)之前，對其項^中一項之製程’其包括在組合步驟 組合之-個或多^固晶片底材進灯個別切割之一步驟，以形成所要與另一底材 少其^該些底材編至 -第-包日H2—tftr，組件，該第—組件包括 二底材（12)，每ΐ組件包28，）’該第二組件包括一第 之一項增構造，射，細嶋至少其中 底材或 16日^範圍第14或15項其中—項之異f構造，其中，兮此 底材戈明片至少其中之-有部分為—種半導體材料所製，例如為^製^ 至16項其中—項之異質構造，其中，該些 一麻=曰如力範圍第14至17項其中一項之異質構造，其中，該第 24^6，H。第二底材至少其中之—包括—個或多個元件(6 以
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DE102011076845A1 (de) 2012-04-12
KR20120018063A (ko) 2012-02-29
CN102376653A (zh) 2012-03-14
US20120043647A1 (en) 2012-02-23
US9117686B2 (en) 2015-08-25
JP2012044146A (ja) 2012-03-01
KR101272675B1 (ko) 2013-06-11
SG178688A1 (en) 2012-03-29
TWI459480B (zh) 2014-11-01
CN105742258A (zh) 2016-07-06
FR2963982B1 (fr) 2012-09-28
DE102011076845B4 (de) 2020-02-06
US8790992B2 (en) 2014-07-29
FR2963982A1 (fr) 2012-02-24
JP5555957B2 (ja) 2014-07-23
US20140327113A1 (en) 2014-11-06

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