TWI459480B - 低溫黏附製程 - Google Patents

低溫黏附製程 Download PDF

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TWI459480B
TWI459480B TW100118741A TW100118741A TWI459480B TW I459480 B TWI459480 B TW I459480B TW 100118741 A TW100118741 A TW 100118741A TW 100118741 A TW100118741 A TW 100118741A TW I459480 B TWI459480 B TW I459480B
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temperature
adhesion
substrate
component
tempering
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TW201218289A (en
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Gweltaz Gaudin
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Soitec Silicon On Insulator
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Description

低溫黏附製程
本發明係關於在低溫下一板體或晶片之第一底材與一板體或晶片之第二底材之黏附。本發明欲獲取即使在低溫下仍具有最佳品質及最佳黏附能量之黏附。
本發明尤其可以應用於複合底材製造之領域或元件之三度空間集積(3D integration)。更一般而言,當一構造因元件之存在或因材料之本質,而無法施以高溫熱處理時,本發明可應用於經由直接(或「分子」)黏附而形成該構造。
本發明優先適用於無法耐受高處理溫度之構造,尤其是因待組合之組件中有元件或電路或微元件存在者。
C.S. Tan等人所編著之《Wafer level 3-D ICs Process technology》一書(p.197-217)提出了對3D科技的回顧。該書揭示一黏附製程,其包括在低溫下沉積一黏附層,以及在一高於此氧化物之沉積溫度下,對此氧化物進行除氣回火。
該技術使用時,可觀察到黏附界面出現缺陷。這些缺陷可能轉而對黏附能量有不利影響。
因此,找出一種新穎方法,以實現在低溫下經由黏附層組合兩個組件之問題,便由此而產生。
本發明首先與一種將一第一組件與一第二組件組合之製程有關,其中第一組件包括至少一第一底材或至少一晶片,第二組件包括至少一第二底材,該製程包括:
a)於每一底材上形成一表面黏附層,該些黏附層至少其中之一形成的溫度低於或等於300℃;
b)在組合前對該些黏附層進行一第一回火,稱為除氣回火,除氣回火至少部分期間之溫度至少等於後續之黏附界面強化溫度(Tr),但低於450℃;
c)將該些黏附層之曝露表面互相接觸以組合底材,
d)在一低於450℃之黏附界面強化溫度(Tr)下,對組合後之構造施行回火。
該二黏附層至少其中之一可以應用沉積方式形成,例如,PECVD或LPCVD形態之沉積。
該些黏附層至少其中之一可為氧化物或氮化物形態,例如,矽氧化物SiO2 或矽氮化物Si3 N4
回火步驟b)可以包括:
-產生一溫度斜坡,以便將溫度自環境溫度逐漸提高到至少等於組合後回火之溫度;
-及/或在一段時間內,例如介於10或30分鐘至2或5小時之間,將溫度保持在至少等於後續之黏附界面強化溫度(Tr),但低於450℃。
根據本發明之一種製程可以額外包括,在步驟c)或步驟b)之前整備該些多孔表面層之表面之一步驟,以便進行組合步驟。
步驟c)之組合,舉例而言,為分子附著形態。
該第一底材或晶片及該第二底材至少其中之一可以包括一個或多個元件。
根據本發明之一種製程,其可以更另亦包括在組合步驟c)之前,對其中之一的底材進行個別切割之一步驟,以形成所要與另一底材組合之一個或多個晶片。
該些底材或晶片,至少其中之一有部分可為一種半導體材料所製,例如為矽製。
本發明亦與一異質構造有關,其包括一第一組件及一第二組件,該第一組件包括至少一第一底材或至少一晶片,該第二組件包括至少一第二底材,每一組件包括一多孔表面層,稱為黏附層,該二組件係經由黏附層而組合,其組合具有至少等於3 J/m2 之一黏附能量。
該些黏附層至少其中之一可為氧化物或氮化物形態,例如,矽氧化物或矽氮化物。
該些底材或晶片,至少其中之一有部分可為一種半導體材料所製,例如為矽製。
較佳情況者為,該些黏附層間之組合為分子附著形態。
更佳情況者為,該第一底材或晶片及該第二底材至少其中之一包括一個或多個元件。
本發明之第一個說明性質實施例呈現於圖1A至1C。
一黏附層,此處為一薄氧化物層4,形成於一第一底材2的表面上(圖1A),該底材,舉例而言,為一種半導體材料所製,較有利者為矽或氧化鋁(Al2 O3 )或玻璃或鍺所製。該黏附層係在低於300℃之低溫下形成。該氧化物為,舉例而言,矽氧化物SiO2 ,其一種沉積技術可為PECVD技術。一前驅氣體,舉例而言,可以是TEOS(四乙氧基矽烷)或SiH4 或N2 形態。
該氧化物層具有一厚度e1,該厚度,舉例而言,介於200 nm及4 μm之間。該底材2含有能提供一項或多項電力或電子或其他功能之裝置,該些裝置於此統一以編號6表示,例如,一個或多個電子及/或光學元件,及/或一個或多個MEMS及/或NEMS。
另一黏附層,此處為一薄氧化物層14,形成於一第二底材12上(圖1B),該底材,舉例而言,為一種半導體材料所製,同前,較有利者為矽或玻璃或鍺所製。該黏附層係在低於300℃之低溫下形成。該氧化物為,舉例而言,矽氧化物SiO2 ,其一種沉積技術可為PECVD技術。一前驅氣體可為上文已指出之氣體之一。該氧化物層具有一厚度e2,該厚度,舉例而言,介於200nm及4μm之間。該底材12亦可選擇性地含有能提供一項或多項電力或電子或其他功能之裝置,該些裝置於此統一以編號16表示,例如,一個或多個電子及/或光學元件,及/或一個或多個MEMS及/或NEMS。
經沉積獲得之該些黏附層4、14均為多孔,且不是很緻密。
一般而言,在根據本發明之一種製程中,由於元件6、16存在於一底材及/或另一底材中,因此溫度被保持在低於450℃,或甚至低於400℃。就形成黏附層之步驟而言,此條件得到遵守,因為如上文所指出,該步驟係在低於250℃或300℃或350℃的溫度下進行。
該些黏附層4、14均可以沉積方式形成,例如LPCVD或PECVD形態之沉積。
在組合該二底材前,先對該些黏附層4、14施行第一回火。在此第一回火期間,該些黏附層4及14承受的溫度至少達到溫度Tr ,該溫度將在底材組合後,接著用於進行黏附界面之強化。由於元件6、16之存在,此強化溫度Tr 本身低於可使用之最高溫度Tmax ,例如400℃或450℃。
例如,溫度按照一溫度斜坡逐漸上升,從環境溫度上升至至少達到該強化溫度Tr ,或達到高於強化溫度Tr 但低於可使用最高溫度Tmax 之一溫度。
圖2A呈現一溫度斜坡範例,其中,溫度非常穩定地攀升,舉例而言,以介於1℃/min及若干℃/min之間的坡度,例如介於1℃/min及5℃/min之間,達到強化溫度Tr ,例如350℃,然後保持在此溫度Tr 數小時。
根據一變化作法,即以虛線呈現者,溫度可按照上述坡度增加至一溫度T’,該溫度較強化溫度Tr 為高,介於強化溫度Tr 及最高溫度Tmax 之間;而最高溫度Tmax ,舉例而言,等於400℃或450℃。
圖2B呈現另一可能性,其中,溫度迅速增加至強化溫度Tr ,然後穩定地保持在此溫度達一小時或更久。根據一變化作法,即以虛線呈現者,溫度迅速增加至一溫度T’,其較強化溫度Tr 為高,介於強化溫度Tr 及最高溫度Tmax 之間;而最高溫度Tmax ,舉例而言,等於400℃或450℃。
圖2C呈現又另一可能性,其中,溫度非常穩定地增加,舉例而言,以介於1℃/min及若干℃/min之間的坡度,例如介於1℃/min及5℃/min之間,達到強化溫度Tr ,例如350℃,然後保持在此溫度Tr 一段相對短暫的時間,例如介於10分鐘至2小時之間,然後再逐漸降至環境溫度。根據一變化作法,即以虛線呈現者,溫度如前述按一非常穩定的坡度增加,達到一高於強化溫度Tr 但低於最高溫度Tmax 之溫度T’,然後保持在此溫度T’一段相對短暫的時間,例如介於10分鐘至2小時之間,然後再逐漸降至環境溫度。
該些黏附層4、14在組合前進行回火,此一步驟之作用如下。由於在低溫下沉積的每一黏附層均含有許多污染物,舉例而言,污染物可能來自N2 O或碳基鏈結形態的氣態前驅物。若不預先加以清除,那麼,在二底材組合後進行後續的黏附界面強化回火期間,這些污染物很有可能會遷移(除氣),並在該二底材的組合界面上形成「氣泡」或其他缺陷。這類氣泡無法清除,而且會使獲得的組合物變得無法使用。
初步的回火步驟,即上文有關圖2A至2C所說明者,可將這些污染種源從該些黏附層4、14抽取出來,卻不會導致這些黏附層的多孔性顯著降低。因而,此一步驟可同時保存黏附多孔材料的有利性質。鑒於在底材組合前之初步回火步驟期間所達到的回火溫度,係介於最高溫度Tmax 及黏附界面強化溫度Tr 之間,這些污染種源絕對會從該些黏附層4、14被抽取出來。因此,這些污染種源便不會在強化回火步驟期間造成破壞,因為其已在一至少等於強化回火溫度之溫度下預先被抽取出來。
接著(圖1C),將經過上述處理的二底材經由該些黏附層4、14的無污染物表面加以組合。在此組合步驟前,可先進行一預處理步驟,例如化學機械研磨(chemical mechanical polishing,CMP)。
最後,在低於或等於最高溫度Tmax 之強化溫度Tr 下,對依上述方式組合好的構造施行回火。
根據本發明之該製程可在界面處獲得品質良好及達到數個J/m2 等級的高黏附能量,例如大於3J/m2 或4J/m2 的黏附能量。該製程的採用,確實達到在黏附界面上沒有「氣泡」形態之缺陷的結果。其黏附能量之量測,舉例而言,可以採用名為「刮刀技術」(blade technique)(或「雙懸臂技術」(double cantilever technique))之技術。
相同原理亦可應用於板體上一個或多個晶片之黏附:在根據本發明之第一回火之前或之後,裁切其中之一的板體,即足以形成一個或多個晶片。接著,將這些晶片分別組合在第二板體上。
此範例更詳細呈現於圖3A至3C。
一黏附層,此處為一薄氧化物層4',形成於一第一底材2'的表面上(圖3A),該底材,舉例而言,為一種半導體材料所製,較有利者為矽或玻璃或鍺所製。
該氧化物層4'形成之方式,與上文有關圖1A所述之氧化物層4形成之方式相同(尤其是在相同溫度下)。因此,該氧化物層會具備相同特性,尤其是多孔性之特性。
該底材接著被裁切為個別之晶片22、24、26、28,如圖3A中以垂直虛線示意者。每一個別晶片包括一個或多個電路或元件22'、24'、26',28',並被黏附層之一部份4’2 、4’4 、4’6 、4’8 所覆蓋。
圖3B呈現一第二底材,其與上文有關圖1B所述之底材相同,且其黏附層係在與先前已提出之同樣條件下獲得。
接著可依照本發明之上述步驟,舉例而言,根據圖2A至2C任一圖式所呈現的圖表之一改變溫度,對每一個別晶片22、24、26、28及圖3B之底材12,進行組合前之回火熱處理。
回火之後,可將依上述方式處理後之個別晶片及底材12,經由黏附層4’2 、4’4 、4’6 、4’8 及14之無污染物表面加以組合。在此組合步驟前,可先進行一預處理步驟,例如,對每一個別晶片之黏附層及底材12之黏附層14,施行化學機械研磨(CMP)。
作為一變化作法,在組合前的回火步驟之後,吾人可將底材2裁切為個別晶片22、24、26、28。其他操作均與上文所述者相似。
以下提供一說明性質實施例。
提供一第一板體或底材2,及一第二板體或底材12,至少其中之一包括電路或微元件6、16。因此,其組構即為上文有關圖1A及1B所述者。
在每一所要組合之表面上,透過PECVD形態之LTO(低溫氧化形成)技術,形成SiO2 之黏附層4、14,由矽烷及N2 O或TMS(三甲基矽烷)及N2 O前驅物開始。
該沉積係在低溫下(低於或等於250℃)進行。此形態之低溫沉積有助於獲得高黏附能量,因為以此方式形成之氧化物相對多孔及/或具有低密度。此一特性讓黏附層在底材組合之後,能夠接著吸收被捕捉在黏附界面上的多餘水分。
接著,依循本發明之製程對該些氧化物施行回火:採用介於0.1℃/min及5℃/min間之一溫度斜坡(例如:1℃/min),以達到介於350℃及400℃間之一溫度。該回火在此溫度下持續12小時。相對緩慢的溫度上升,可確保被該些黏附氧化物4、14納入之污染物種源能夠按其不同活化能連續除氣。
接著,整備該些板體以便進行組合,先進行表面磨平程序,以提供一與分子黏附相配之粗度(粗度<0.5 nm RMS),然後清潔板體;板體清潔可輔以刷洗待組合之板體表面。
接著,以「分子」黏附方式進行兩板體之組合,然後讓組合物在不超過除氣回火溫度之一溫度下進行回火,以免引發那些仍存在於氧化物中之種源,以及在前述處理期間未被清除之種源,遷移至黏附界面。
經此製程後可獲得約為3.6 J/m2 ,且品質良好之黏附能量:明確地說,可以注意到黏附界面上沒有「氣泡」形態的缺陷。此黏附能量數值應與一標準的氧化物/氧化物黏附(亦即,非多孔性/緻密氧化物)所獲得約為2 J/m2 之黏附能量比較。
比較試驗係對在不同溫度下整備,不同形態之氧化物進行。
相應之量測結果整理於圖4。有三種形態的SiO2 氧化物可進行比較。該些氧化物係以PECVD方式沉積:
1) 第一種為TEOS(四乙氧基矽烷)形態之氧化物,沉積溫度400℃,沉積速率14 nm/s;
2) 第二種為「矽烷氧化物」形態之氧化物,沉積溫度210℃,沉積速率4.5 nm/s;及
3) 第三種為「矽烷氧化物」形態之氧化物,沉積溫度400℃,沉積速率10 nm/s。
黏附能量之補充性量測係針對與上述材料相同,但未經任何強化回火者而進行:這些量測在圖4中以「未經強化回火」表示。其量測值相當於在尚未進行強化回火的情況下所量測之黏附能量。
從前文所述條件可知,只有第二種氧化物是在低於250℃的溫度下沉積。
除以「未經強化回火」表示者外,圖4中其他圖表呈現之γ值(單位為mJ/m2 )係等於當黏附能量(Y軸)作為強化回火溫度Tr(X軸)的函數時,這三種材料獲得之黏附能量的一半。強化回火溫度Tr 在200℃到400℃之間變化。
可以觀察到第二種材料(LTOB,圖表中淺灰色者)的黏附能量比第一種材料(TEOS,圖表中深灰色者)獲得的黏附能量至少大兩倍,而且幾乎是第三種材料(矽烷氧化物,圖表中白色者)所獲得之黏附能量的三倍。
而且,不論強化回火溫度Tr 為何(200℃,350℃或400℃),第二種氧化物所顯示的卓越黏附優勢均明顯可見。只有在「未經強化回火」的情況下,三種材料的黏附能量沒有差異。
因此,這些試驗顯示,低溫沉積可使沉積氧化物獲得一定程度的多孔性,比經由高溫PECVD獲得的多孔性為高。
此外,在沒有強化回火的情況下,黏附能量始終很低。
因此,吾人可清楚看到,在低溫下形成黏附層,結合在低於450℃的強化溫度下施行強化回火,可產生品質良好的高能量黏附。如上文所指出,黏附能量等於所測得參數γ值的兩倍:因此,此處的黏附能量確實達到了至少3J/m2
在圖4這些圖表中,吾人可發現,在溫度400℃下沉積之該些材料,其黏附能量之程度與C.S.Tan等人在2003年發表於期刊Applied Physics Letters,Vol.82,No.116,p.2649-2651,題為〈Low temperature thermal oxide to plasma-enhanced chemical vapor deposition oxide wafer bonding for thin film transfer application〉文件中圖3所呈現的黏附能量程度相同。在此文件中,該些氧化物層亦是在400℃的溫度下沉積。
因此,圖4所呈現的比較試驗結果,明顯與從習知技術得知之數據一致。
2、2’、12...底材
4、4’、4’2 、4’4 、4’6 、4’8 、14...薄氧化物層
6、16、22’、24’、26’、28’...元件
22、24、26、28...晶片
圖1A至1C呈現一根據本發明之一種製程之實施例。
圖2A至2C呈現依照本發明,在組合前處理黏附層之一步驟期間,不同溫度變化之示意圖。
圖3A至3C呈現根據本發明之一種製程之一變化作法。
圖4呈現在比較試驗的情況下進行量測之結果。
2、12...底材
4、14...薄氧化物層
6、16...元件

Claims (18)

  1. 一種組合一第一組件與一第二組件之製程,其中,該第一組件包括至少一第一底材(2)或至少一晶片(22、24、26、28),該第二組件包括至少一第二底材(12),該製程包括:a)於每一底材上形成一表面層(4、4’2 、4’4 、4’6 、4’8 、14),稱為黏附層,該些黏附層至少其中之一是在低於或等於300℃的溫度下形成;b)在組合前對該些黏附層進行第一回火,稱為除氣回火,除氣回火至少部分期間之溫度至少等於後續之黏附界面強化溫度(Tr),但低於450℃;c)將該些黏附層(4、4’2 、4’4 、4’6 、4’8 、14)之曝露表面互相接觸以組合底材,d)在一低於450℃之黏附界面強化溫度(Tr)下,對組合後之構造施行回火。
  2. 如申請專利範圍第1項之製程,其中,該些黏附層至少其中之一係以PECVD或LPCVD沉積方式獲得。
  3. 如申請專利範圍第1項之製程,其中,該些黏附層至少其中之一為氧化物或氮化物形態。
  4. 如申請專利範圍第3項之製程,其中,該些黏附層至少其中之一為矽氧化物。
  5. 如申請專利範圍第1項之製程,其中,該些黏附層至少其中之一係在低於或等於250℃之溫度下形成。
  6. 如申請專利範圍第1項之製程,其中,黏附界面強化溫度(Tr)為低於400℃。
  7. 如申請專利範圍第1項之製程,其中,步驟b)之構造組合前之回火包括產生一溫度斜坡,例如,介於1℃/min及5℃/min間之溫度斜坡。
  8. 如申請專利範圍第1項之製程,其中,步驟b)之構造組合前之回火包括在一段時間內,例如介於10或30分鐘至2或5小時之間,將溫度保持在至少等於後續之黏附界面強化溫度(Tr),但 低於450℃。
  9. 如申請專利範圍第1項之製程,其額外包括在步驟c)或步驟b)之前,整備該些多孔表面層之表面之一步驟,以便進行組合步驟。
  10. 如申請專利範圍第1項之製程,其中,步驟c)之組合為分子附著形態。
  11. 如申請專利範圍第1項之製程,其中,該第一底材或晶片及該第二底材至少其中之一包括一個或多個元件(6、16、22’、24’,26’、28’)。
  12. 如申請專利範圍第1項之製程,其包括在組合步驟c)之前,對其中之一的底材進行個別切割之一步驟,以形成所要與另一底材組合之一個或多個晶片。
  13. 如以上申請專利範圍中任一項之製程,其中,該些底材或晶片至少其中之一有部分為一種半導體材料所製,例如為矽製。
  14. 一異質構造,其包括一第一組件及一第二組件,該第一組件包括一第一底材(2)或至少一晶片(22、24、26、28),該第二組件包括一第二底材(12),每一組件包括一多孔表面層(4、4’2 、4’4 、4’6 、4’8 、14),稱為黏附層,該二組件經由黏附層而組合,其組合具有至少等於3J/m2 或4J/m2 之一黏附能量。
  15. 如申請專利範圍第14項之異質構造,其中,該些黏附層至少其中之一為氧化物或氮化物形態。
  16. 如申請專利範圍第14項之異質構造,其中,該些底材或晶片至少其中之一有部分為一種半導體材料所製,例如為矽製。
  17. 如申請專利範圍第14項之異質構造,其中,該些黏附層間之組合為分子附著形態。
  18. 如申請專利範圍第14至17項其中一項之異質構造,其中,該第一底材或晶片及該第二底材至少其中之一包括一個或多個元件(6、16、22’、24’,26’、28’)。
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