FR2923079B1 - Substrats soi avec couche fine isolante enterree - Google Patents
Substrats soi avec couche fine isolante enterreeInfo
- Publication number
- FR2923079B1 FR2923079B1 FR0707535A FR0707535A FR2923079B1 FR 2923079 B1 FR2923079 B1 FR 2923079B1 FR 0707535 A FR0707535 A FR 0707535A FR 0707535 A FR0707535 A FR 0707535A FR 2923079 B1 FR2923079 B1 FR 2923079B1
- Authority
- FR
- France
- Prior art keywords
- enterree
- soi
- substrates
- fine layer
- insulated fine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0707535A FR2923079B1 (fr) | 2007-10-26 | 2007-10-26 | Substrats soi avec couche fine isolante enterree |
TW097135225A TW200919630A (en) | 2007-10-26 | 2008-09-12 | SOI substrates with a fine buried insulating layer |
US12/237,000 US7892951B2 (en) | 2007-10-26 | 2008-09-24 | SOI substrates with a fine buried insulating layer |
SG200807231-6A SG152141A1 (en) | 2007-10-26 | 2008-09-26 | Soi substrates with a fine buried insulating layer |
KR1020080098313A KR101057140B1 (ko) | 2007-10-26 | 2008-10-07 | 미세 매립 절연층을 가지는 실리콘-온-절연물 기판들 |
DE102008051494.2A DE102008051494B4 (de) | 2007-10-26 | 2008-10-13 | Verfahren zum Herstellen der SOI-Substrate mit einer feinen vergrabenen Isolationsschicht |
JP2008272387A JP2009111381A (ja) | 2007-10-26 | 2008-10-22 | 微細な埋め込み絶縁層を有するsoi基板 |
CN2008101667695A CN101419911B (zh) | 2007-10-26 | 2008-10-27 | 具有精细隐埋绝缘层的soi衬底 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0707535A FR2923079B1 (fr) | 2007-10-26 | 2007-10-26 | Substrats soi avec couche fine isolante enterree |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2923079A1 FR2923079A1 (fr) | 2009-05-01 |
FR2923079B1 true FR2923079B1 (fr) | 2017-10-27 |
Family
ID=39628741
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0707535A Active FR2923079B1 (fr) | 2007-10-26 | 2007-10-26 | Substrats soi avec couche fine isolante enterree |
Country Status (8)
Country | Link |
---|---|
US (1) | US7892951B2 (fr) |
JP (1) | JP2009111381A (fr) |
KR (1) | KR101057140B1 (fr) |
CN (1) | CN101419911B (fr) |
DE (1) | DE102008051494B4 (fr) |
FR (1) | FR2923079B1 (fr) |
SG (1) | SG152141A1 (fr) |
TW (1) | TW200919630A (fr) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011077504A (ja) * | 2009-09-02 | 2011-04-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
TWI484622B (zh) * | 2009-09-08 | 2015-05-11 | Soitec Silicon On Insulator | 用以製造基材的方法 |
FR2963982B1 (fr) | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | Procede de collage a basse temperature |
US9252042B2 (en) | 2011-01-25 | 2016-02-02 | Ev Group E. Thallner Gmbh | Method for permanent bonding of wafers |
EP2500933A1 (fr) * | 2011-03-11 | 2012-09-19 | S.O.I. TEC Silicon | Structure multicouche et procédé de fabrication de dispositifs semi-conducteurs |
KR101550121B1 (ko) | 2011-04-08 | 2015-09-03 | 에베 그룹 에. 탈너 게엠베하 | 웨이퍼 영구 결합 방법 |
CN103477420B (zh) | 2011-04-08 | 2016-11-16 | Ev集团E·索尔纳有限责任公司 | 永久性粘合晶片的方法 |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
CN102431961A (zh) * | 2011-12-07 | 2012-05-02 | 华中科技大学 | 一种低温等离子体活化直接键合的三维硅模具制备方法 |
FR2995447B1 (fr) | 2012-09-07 | 2014-09-05 | Soitec Silicon On Insulator | Procede de separation d'au moins deux substrats selon une interface choisie |
FR2995445B1 (fr) | 2012-09-07 | 2016-01-08 | Soitec Silicon On Insulator | Procede de fabrication d'une structure en vue d'une separation ulterieure |
CN103035654B (zh) * | 2012-12-21 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | 绝缘体上硅射频器件及其绝缘体上硅衬底 |
CN103117235A (zh) * | 2013-01-31 | 2013-05-22 | 上海新傲科技股份有限公司 | 等离子体辅助键合方法 |
CN104766788A (zh) * | 2014-01-06 | 2015-07-08 | 无锡华润上华半导体有限公司 | 绝缘体上硅及其制备方法 |
CN104934292A (zh) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | 一种提高晶圆间键合强度的方法 |
CN105097823A (zh) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | 双垂直窗三埋层soi高压器件结构 |
CN106206334B (zh) * | 2015-05-07 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | 监测晶圆以及金属污染的监测方法 |
JP6106239B2 (ja) * | 2015-09-30 | 2017-03-29 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ウェハを恒久的にボンディングするための方法 |
FR3094559B1 (fr) * | 2019-03-29 | 2024-06-21 | Soitec Silicon On Insulator | Procédé de transfert de paves d’un substrat donneur sur un substrat receveur |
CN110491827B (zh) * | 2019-08-13 | 2021-02-12 | 北京工业大学 | 一种半导体薄膜层的转移方法及复合晶圆的制备方法 |
CN112259678B (zh) * | 2020-10-19 | 2022-07-19 | 济南晶正电子科技有限公司 | 一种用于改善薄膜层炸裂的方法及薄膜材料 |
CN113035695A (zh) * | 2021-02-25 | 2021-06-25 | 泉芯集成电路制造(济南)有限公司 | 一种掩膜结构的制备方法、半导体器件及其制备方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5383993A (en) | 1989-09-01 | 1995-01-24 | Nippon Soken Inc. | Method of bonding semiconductor substrates |
JPH0391227A (ja) * | 1989-09-01 | 1991-04-16 | Nippon Soken Inc | 半導体基板の接着方法 |
JP3618105B2 (ja) * | 1991-03-07 | 2005-02-09 | 株式会社日本自動車部品総合研究所 | 半導体基板の製造方法 |
JPH05218364A (ja) * | 1992-01-31 | 1993-08-27 | Canon Inc | 半導体基体の形成方法 |
JPH09252100A (ja) | 1996-03-18 | 1997-09-22 | Shin Etsu Handotai Co Ltd | 結合ウェーハの製造方法及びこの方法により製造される結合ウェーハ |
WO1999010927A1 (fr) | 1997-08-29 | 1999-03-04 | Farrens Sharon N | Procede de soudage de tranches in situ par plasma |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US6870276B1 (en) | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
US20030134486A1 (en) | 2002-01-16 | 2003-07-17 | Zhongze Wang | Semiconductor-on-insulator comprising integrated circuitry |
US6995427B2 (en) * | 2003-01-29 | 2006-02-07 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same |
JP2004259970A (ja) * | 2003-02-26 | 2004-09-16 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
JP2004335642A (ja) | 2003-05-06 | 2004-11-25 | Canon Inc | 基板およびその製造方法 |
JP2005079389A (ja) * | 2003-09-01 | 2005-03-24 | Sumitomo Mitsubishi Silicon Corp | 貼り合わせウェーハの分離方法及びその分離用ボート |
US20050067377A1 (en) | 2003-09-25 | 2005-03-31 | Ryan Lei | Germanium-on-insulator fabrication utilizing wafer bonding |
FR2867310B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
FR2867307B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
EP1659623B1 (fr) | 2004-11-19 | 2008-04-16 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Méthode de fabrication d'une plaquette de type germanium sur isolant (GeOI) |
JP4594121B2 (ja) * | 2005-02-03 | 2010-12-08 | 信越化学工業株式会社 | Soiウエーハの製造方法及びsoiウエーハ |
CN100481345C (zh) | 2005-02-24 | 2009-04-22 | 硅绝缘体技术有限公司 | SiGe层的热氧化及其应用 |
FR2888663B1 (fr) * | 2005-07-13 | 2008-04-18 | Soitec Silicon On Insulator | Procede de diminution de la rugosite d'une couche epaisse d'isolant |
FR2892230B1 (fr) * | 2005-10-19 | 2008-07-04 | Soitec Silicon On Insulator | Traitement d'une couche de germamium |
US7531392B2 (en) * | 2006-02-27 | 2009-05-12 | International Business Machines Corporation | Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same |
JP5109287B2 (ja) * | 2006-05-09 | 2012-12-26 | 株式会社Sumco | 半導体基板の製造方法 |
EP1858071A1 (fr) * | 2006-05-18 | 2007-11-21 | S.O.I.TEC. Silicon on Insulator Technologies S.A. | Procédé de fabrication d'une plaquette de type semi-conducteur sur isolant, et plaquette de type semi-conducteur sur isolant |
JP2008004900A (ja) * | 2006-06-26 | 2008-01-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
US7575988B2 (en) * | 2006-07-11 | 2009-08-18 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating a hybrid substrate |
-
2007
- 2007-10-26 FR FR0707535A patent/FR2923079B1/fr active Active
-
2008
- 2008-09-12 TW TW097135225A patent/TW200919630A/zh unknown
- 2008-09-24 US US12/237,000 patent/US7892951B2/en active Active
- 2008-09-26 SG SG200807231-6A patent/SG152141A1/en unknown
- 2008-10-07 KR KR1020080098313A patent/KR101057140B1/ko active IP Right Grant
- 2008-10-13 DE DE102008051494.2A patent/DE102008051494B4/de active Active
- 2008-10-22 JP JP2008272387A patent/JP2009111381A/ja active Pending
- 2008-10-27 CN CN2008101667695A patent/CN101419911B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
KR20090042712A (ko) | 2009-04-30 |
CN101419911A (zh) | 2009-04-29 |
KR101057140B1 (ko) | 2011-08-16 |
DE102008051494A1 (de) | 2009-05-07 |
JP2009111381A (ja) | 2009-05-21 |
SG152141A1 (en) | 2009-05-29 |
FR2923079A1 (fr) | 2009-05-01 |
US20090111243A1 (en) | 2009-04-30 |
TW200919630A (en) | 2009-05-01 |
US7892951B2 (en) | 2011-02-22 |
CN101419911B (zh) | 2011-04-06 |
DE102008051494B4 (de) | 2019-06-19 |
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Legal Events
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