JP5555957B2 - 低温結合プロセス - Google Patents
低温結合プロセス Download PDFInfo
- Publication number
- JP5555957B2 JP5555957B2 JP2011120794A JP2011120794A JP5555957B2 JP 5555957 B2 JP5555957 B2 JP 5555957B2 JP 2011120794 A JP2011120794 A JP 2011120794A JP 2011120794 A JP2011120794 A JP 2011120794A JP 5555957 B2 JP5555957 B2 JP 5555957B2
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- substrate
- annealing
- bonding
- bonding layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 36
- 230000008569 process Effects 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 54
- 238000000137 annealing Methods 0.000 claims description 39
- 238000005728 strengthening Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000007872 degassing Methods 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000010408 film Substances 0.000 description 11
- 238000005496 tempering Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 239000000356 contaminant Substances 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 101100460147 Sarcophaga bullata NEMS gene Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000010070 molecular adhesion Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/03—Bonding two components
- B81C2203/033—Thermal bonding
- B81C2203/036—Fusion bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
- H01L2224/27452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/276—Manufacturing methods by patterning a pre-deposited material
- H01L2224/2761—Physical or chemical etching
- H01L2224/27616—Chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/278—Post-treatment of the layer connector
- H01L2224/2781—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/278—Post-treatment of the layer connector
- H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/279—Methods of manufacturing layer connectors involving a specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/29187—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
- H01L2224/83014—Thermal cleaning, e.g. decomposition, sublimation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Description
a)表面結合層をそれぞれの基板上に形成し、表面結合層の少なくとも1つは、300℃以下の温度を有するステップと、
b)組み立てる前に、その後の結合界面強化温度(Tr)に少なくとも等しいが450℃未満の温度で結合層を少なくとも部分的にアニーリングする、脱ガス・アニーリングと呼ばれる第1のアニーリングを実行するステップと、
c)結合層の露出面を接触させることによって、基板を組み立てるステップと、
d)組み立てられた構造を450℃未満の結合界面強化温度(Tr)でアニーリングするステップと、
を備える。
・周囲温度から緩やかに組み立て後のアニーリング温度に少なくとも等しい温度にするために、温度勾配を生成すること、
・および/または、例えば、10分または30分から2時間または5時間までの範囲に存在する期間にわたって、温度を少なくともその後の結合界面強化温度(Tr)に等しいが450℃未満の温度に維持すること、
を備えてもよい。
Claims (11)
- 第1の基板(2)と、第2の基板(12)とを組み立てるためのプロセスであって、
a)結合層と呼ばれる表面層(4、4’2、4’4、4’6、4’8、14)をそれぞれの前記基板上に形成し、前記結合層の少なくとも1つが、300℃以下の温度で形成されるステップと、
b)組み立てる前に、その後の結合界面強化温度(Tr)に少なくとも等しいが450℃未満の温度で前記結合層を少なくとも部分的にアニーリングする脱ガス・アニーリングと呼ばれる第1のアニーリングを実行するステップと、
c)前記結合層(4、4’2、4’4、4’6、4’8、14)の露出面を接触させることによって、前記基板を組み立てるステップと、
d)組み立てられた構造を450℃未満の前記結合界面強化温度(Tr)でアニーリングするステップと、
を備え、
前記第1の基板上の前記結合層及び前記第2の基板上の前記結合層が、PECVD成膜またはLPCVD成膜によって得られ、
前記第1の基板上の前記結合層及び前記第2の基板上の前記結合層が、酸化物型または窒化物型である、プロセス。 - 前記結合層の少なくとも1つが、酸化ケイ素である請求項1に記載のプロセス。
- 前記結合層の少なくとも1つが、250℃以下の温度で形成される請求項1又は2に記載のプロセス。
- 前記結合界面強化温度(Tr)が、400℃未満である請求項1〜3のいずれか一項に記載のプロセス。
- 組み立てる前に前記構造をアニーリングするステップb)が、例えば、1℃/分から5℃/分までの範囲に存在する温度勾配を生成することを備えた請求項1〜4のいずれか一項に記載のプロセス。
- 組み立てる前に前記構造をアニーリングするステップb)が、例えば、10分または30分から2時間または5時間までの範囲の期間にわたって、温度を少なくともその後の結合界面強化温度(Tr)に等しいが450℃未満の温度に維持する、請求項1〜5のいずれか一項に記載のプロセス。
- ステップc)の前に、あるいは、ステップb)の前に、前記組立ステップのために多孔質表面層の表面を準備するステップをさらに備えた、請求項1〜6のいずれか一項に記載のプロセス。
- ステップc)の組立が、分子付着型である請求項1〜7のいずれか一項に記載のプロセス。
- 前記第1の基板、および、前記第2の基板の少なくとも1つが、1つ以上のコンポーネント(6、16、22’、24’、26’、28’)を備えた請求項1〜8のいずれか一項に記載のプロセス。
- 組み立てるステップc)の前に、一方の前記基板と組み立てられるべき1つ以上のチップを形成するために、他方の前記基板を個別に切断するステップを備えた、請求項1〜9のいずれか一項に記載のプロセス。
- 前記基板またはチップの少なくとも1つが半導体材料、例えば、シリコンから少なくとも部分的に作られる請求項1〜10のいずれか一項に記載のプロセス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1056696 | 2010-08-20 | ||
FR1056696A FR2963982B1 (fr) | 2010-08-20 | 2010-08-20 | Procede de collage a basse temperature |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012044146A JP2012044146A (ja) | 2012-03-01 |
JP5555957B2 true JP5555957B2 (ja) | 2014-07-23 |
Family
ID=43827267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011120794A Active JP5555957B2 (ja) | 2010-08-20 | 2011-05-30 | 低温結合プロセス |
Country Status (8)
Country | Link |
---|---|
US (2) | US8790992B2 (ja) |
JP (1) | JP5555957B2 (ja) |
KR (1) | KR101272675B1 (ja) |
CN (2) | CN105742258B (ja) |
DE (1) | DE102011076845B4 (ja) |
FR (1) | FR2963982B1 (ja) |
SG (1) | SG178688A1 (ja) |
TW (1) | TWI459480B (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2963982B1 (fr) * | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | Procede de collage a basse temperature |
JP6095903B2 (ja) * | 2012-06-15 | 2017-03-15 | 浜松ホトニクス株式会社 | 固体撮像装置の製造方法及び固体撮像装置 |
KR101947165B1 (ko) | 2012-10-16 | 2019-02-13 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치와 이의 제조 방법 및 회로 필름의 회전 장치 |
CN105874571B (zh) * | 2013-12-18 | 2019-12-17 | 英特尔公司 | 局部层转移的系统和方法 |
CN104934292A (zh) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | 一种提高晶圆间键合强度的方法 |
EP3024019A1 (en) | 2014-11-24 | 2016-05-25 | IMEC vzw | Method for direct bonding of semiconductor substrates. |
CN104891430B (zh) * | 2015-04-17 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | 硅片键合方法 |
CN104925749B (zh) * | 2015-04-17 | 2017-01-25 | 上海华虹宏力半导体制造有限公司 | 硅片键合方法 |
CN105185720B (zh) * | 2015-08-03 | 2018-05-08 | 武汉新芯集成电路制造有限公司 | 一种增强键合强度的超薄热氧化晶圆键合工艺 |
CN105206536B (zh) * | 2015-08-17 | 2018-03-09 | 武汉新芯集成电路制造有限公司 | 一种增强键合强度的晶圆键合方法及结构 |
CN105261586B (zh) * | 2015-08-25 | 2018-05-25 | 上海新傲科技股份有限公司 | 带有电荷陷阱和绝缘埋层衬底的制备方法 |
US9725312B1 (en) * | 2016-02-05 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Preconditioning to enhance hydrophilic fusion bonding |
CN107346746B (zh) * | 2016-05-05 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN107633997B (zh) | 2017-08-10 | 2019-01-29 | 长江存储科技有限责任公司 | 一种晶圆键合方法 |
CN108383080B (zh) * | 2018-03-06 | 2020-04-10 | 苏州大学 | 纳米间隙原位活化的复合阳极键合方法 |
CN112635299A (zh) * | 2020-12-17 | 2021-04-09 | 武汉新芯集成电路制造有限公司 | 低温沉积方法、半导体器件的键合方法和芯片 |
CN113380639A (zh) * | 2021-05-26 | 2021-09-10 | 西安交通大学 | 一种原子级离子清洁活化低温键合装置及方法 |
US20230026052A1 (en) * | 2021-07-22 | 2023-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Atomic layer deposition bonding layer for joining two semiconductor devices |
CN114420549B (zh) * | 2022-03-31 | 2022-11-18 | 深圳新声半导体有限公司 | 一种二氧化硅表面与硅表面低温键合的方法 |
CN114927538B (zh) * | 2022-07-20 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | 晶圆键合方法以及背照式图像传感器的形成方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6090687A (en) | 1998-07-29 | 2000-07-18 | Agilent Technolgies, Inc. | System and method for bonding and sealing microfabricated wafers to form a single structure having a vacuum chamber therein |
US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
CA2409745A1 (en) | 2000-05-22 | 2001-12-06 | Monsanto Technology, Llc | Reaction systems for making n-(phosphonomethyl)glycine compounds |
US6475072B1 (en) | 2000-09-29 | 2002-11-05 | International Business Machines Corporation | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) |
US20040126993A1 (en) * | 2002-12-30 | 2004-07-01 | Chan Kevin K. | Low temperature fusion bonding with high surface energy using a wet chemical treatment |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
FR2860249B1 (fr) | 2003-09-30 | 2005-12-09 | Michel Bruel | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
US7235812B2 (en) | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
JP5364368B2 (ja) * | 2005-04-21 | 2013-12-11 | エイオーネックス・テクノロジーズ・インコーポレイテッド | 基板の製造方法 |
FR2895420B1 (fr) | 2005-12-27 | 2008-02-22 | Tracit Technologies Sa | Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. |
US7485539B2 (en) * | 2006-01-13 | 2009-02-03 | International Business Machines Corporation | Strained semiconductor-on-insulator (sSOI) by a simox method |
FR2913528B1 (fr) | 2007-03-06 | 2009-07-03 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche d'oxyde enterree pour la realisation de composants electroniques ou analogues. |
US7795111B2 (en) * | 2007-06-27 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate and manufacturing method of semiconductor device |
FR2923079B1 (fr) * | 2007-10-26 | 2017-10-27 | S O I Tec Silicon On Insulator Tech | Substrats soi avec couche fine isolante enterree |
EP2091071B1 (en) * | 2008-02-15 | 2012-12-12 | Soitec | Process for bonding two substrates |
JP4947316B2 (ja) | 2008-08-15 | 2012-06-06 | 信越化学工業株式会社 | 基板の接合方法並びに3次元半導体装置 |
US8173518B2 (en) * | 2009-03-31 | 2012-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of wafer bonding |
FR2963982B1 (fr) * | 2010-08-20 | 2012-09-28 | Soitec Silicon On Insulator | Procede de collage a basse temperature |
-
2010
- 2010-08-20 FR FR1056696A patent/FR2963982B1/fr active Active
- 2010-10-14 US US12/904,744 patent/US8790992B2/en active Active
-
2011
- 2011-05-27 TW TW100118741A patent/TWI459480B/zh active
- 2011-05-30 JP JP2011120794A patent/JP5555957B2/ja active Active
- 2011-06-01 DE DE102011076845.9A patent/DE102011076845B4/de active Active
- 2011-07-04 KR KR1020110065872A patent/KR101272675B1/ko active IP Right Grant
- 2011-07-12 CN CN201610091145.6A patent/CN105742258B/zh active Active
- 2011-07-12 CN CN2011101994542A patent/CN102376653A/zh active Pending
- 2011-08-18 SG SG2011059490A patent/SG178688A1/en unknown
-
2014
- 2014-07-17 US US14/334,370 patent/US9117686B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN105742258A (zh) | 2016-07-06 |
FR2963982A1 (fr) | 2012-02-24 |
KR101272675B1 (ko) | 2013-06-11 |
SG178688A1 (en) | 2012-03-29 |
TWI459480B (zh) | 2014-11-01 |
FR2963982B1 (fr) | 2012-09-28 |
CN102376653A (zh) | 2012-03-14 |
US8790992B2 (en) | 2014-07-29 |
DE102011076845A1 (de) | 2012-04-12 |
US9117686B2 (en) | 2015-08-25 |
US20120043647A1 (en) | 2012-02-23 |
CN105742258B (zh) | 2020-09-29 |
JP2012044146A (ja) | 2012-03-01 |
DE102011076845B4 (de) | 2020-02-06 |
KR20120018063A (ko) | 2012-02-29 |
TW201218289A (en) | 2012-05-01 |
US20140327113A1 (en) | 2014-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5555957B2 (ja) | 低温結合プロセス | |
JP4855015B2 (ja) | 二枚のウエハを結合する前の熱処理 | |
KR101623655B1 (ko) | 고온 내성 접착제 조성물, 기판의 접착 방법 및 3차원 반도체 장치 | |
CN106133899B (zh) | 用于半导体和插入物加工的载体粘结方法和制品 | |
US6429094B1 (en) | Treatment process for molecular bonding and unbonding of two structures | |
Dragoi et al. | Adhesive wafer bonding for MEMS applications | |
KR20100096129A (ko) | 폴리머를 갖는 기판의 열처리에 의한 자립 고체상태 층의 제조 | |
KR20120052160A (ko) | 복합 기판 및 복합 기판의 제조 방법 | |
JP6208646B2 (ja) | 貼り合わせ基板とその製造方法、および貼り合わせ用支持基板 | |
CN102341900A (zh) | 制造热膨胀系数局部适应的异质结构的方法 | |
JP2009500819A (ja) | 酸化物もしくは窒化物の薄い結合層を堆積することによる基板の組み立て方法 | |
JP2024022682A (ja) | ハイブリッド構造 | |
US20130237032A1 (en) | Method of Manufacturing Silicon-On-Insulator Wafers | |
KR102055933B1 (ko) | 열산화 이종 복합 기판 및 그 제조 방법 | |
EP3335239A1 (fr) | Procédé de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse | |
US7807548B2 (en) | Process of forming and controlling rough interfaces | |
JP5053252B2 (ja) | 半導体材料の少なくとも1つの厚い層を含むヘテロ構造の製造方法 | |
JP6851033B2 (ja) | 接合体の製造方法および接合体 | |
JP2007513512A (ja) | ポリマー膜上にエレクトロニクス構成部品を分子架橋する方法 | |
TWI762755B (zh) | 可分離結構及應用所述結構之分離方法 | |
CN109678107B (zh) | 一种粘接单晶硅和蓝宝石的方法 | |
JP2021506122A (ja) | ドナー基板の残余部分を整えるための方法、その方法によって製造された基板、およびそのような基板の使用 | |
JP2023519166A (ja) | 積層構造を製造するための方法 | |
TW202349454A (zh) | 複合結構及其製作方法 | |
FR2962848A1 (fr) | Substrat temporaire, procede de transfert et procede de fabrication |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130321 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130507 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130807 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130812 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130827 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140128 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140417 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140507 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140516 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5555957 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |