JP2001217430A - Method of manufacturing semiconductor substrate and semiconductor substrate manufactured thereby - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate and its forming method wherein, in a strain layer/stain-applied crystal layer structure, the crystallinity deterioration of the strain layer due to crystal defects caused in the starin-applied crystal layer structure is reduced and the strain layer/strain-applied crystal layer structure is formed with a thin film on an insulation layer. SOLUTION: An insulation layer on a Si substrate and an SiGe layer on another Si substrate are bonded, using the semiconductor laminating technique, and the Si substrate at the SiGe layer side is removed by polishing, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, a semiconductor substrate, and more particularly to a semiconductor device having a strained Si layer as an active region, a method of manufacturing a semiconductor device, and a semiconductor substrate.

[0002]

2. Description of the Related Art Si semiconductor devices, especially MOSFETs
The performance of transistors is improving year by year with the progress of large-scale integrated circuits (LSIs). However, in recent years, limitations on miniaturization of lithography technology, approach of carrier mobility to theoretical mobility of Si, etc. have been pointed out, and MOSFETs have been pointed out.
The difficulty of further improving the performance of the system is increasing.

In general, as a measure for improving the performance of a semiconductor device, for example, GaAs having a theoretical mobility higher than that of Si is used.
A method of achieving higher performance by using a crystal different from Si, such as an s semiconductor crystal or a SiC semiconductor crystal, is being studied.

However, GaAs semiconductor crystals and SiC
Since it is difficult to mix a crystal with a Si device manufacturing process that is currently widely used in crystal, a great deal of time and effort is required for element development. Review and replacement are required.

Therefore, there is a keen need for the development of a high-performance Si-based semiconductor device that can be realized with a shorter development period and lower investment efficiency while utilizing the know-how of the Si device manufacturing process technology and the manufacturing apparatus that are widely used at present. I have.

[0006] For this purpose, research has been conducted to improve the electron mobility of Si and to improve the performance of Si-MOSFET. One of the methods for improving the mobility of Si is Si
A technique for applying a strain to a layer has attracted attention. In general, when strain is applied to a semiconductor layer, its band structure changes, and scattering of carriers in a channel is suppressed, so that an improvement in electron mobility can be expected.

Specifically, a mixed crystal layer made of a material having a larger lattice constant than Si, for example, Ge
When a SiGe mixed crystal layer (hereinafter simply referred to as a SiGe layer) is formed thick (several μm) so as to relax the lattice, and a thin Si layer (several nm) is formed on the relaxed SiGe layer,
A strained strained Si layer is formed due to the difference in lattice constant between SiGe and Si.

It has been reported that when such a strained Si layer is used for a channel of a MOSFET, a significant improvement in electron mobility can be achieved, which is about 1.76 times that when a strainless Si layer is used for a channel. (J. Welser, J. et al.
L. Hoyl, S .; Tagkagi, and J.M.
F. Gibbons, IEDM 94-373).

As another method for improving the electron mobility of Si, there is a method of shortening the channel length of the MOSFET by shortening the channel length. However, if the channel length is reduced, the effect of the stray capacitance increases, and it becomes difficult to improve the electron mobility as expected.

In order to solve this problem, an SOI (silicon oxide) in which a Si layer is formed on a Si substrate via an insulating film.
Attention has been paid to a structure in which a channel layer is provided in a (n insulator) layer. In this structure, since the isolation is completely achieved by the insulating film, it is expected that the stray capacitance can be reduced and the element can be easily separated, and further lower power consumption and higher integration can be realized.

Therefore, the strain S, which can be expected to improve the electron mobility,
SOI that reduces the stray capacitance and facilitates element isolation
Attempts have been made to apply the structure to a semiconductor device structure. This structure will be described with reference to FIG.

First, as shown in FIG. 1A, an SiO ₂ insulating film 2 and a 10 nm to 30 nm SOI
An SOI substrate on which the layer 3 is formed is prepared, and on this SOI substrate, SiG having a lattice constant larger than that of Si and having a Ge concentration of 20% is provided.
The e layer 4 is formed sufficiently thicker than the SOI layer 3.

Next, as shown in FIG. 1B, annealing at 1100 ° C. for 1 hour in a nitrogen atmosphere
The tensile strain (S) applied from the Ge layer 4 to the SOI layer 3
TRAIN), the SOI layer 3 is plastically deformed and lattice-relaxed. At the same time, the lattice relaxation of the SiGe layer 4 also occurs. Due to this plastic deformation, dislocations 33 such as threading dislocations and misfit dislocations are generated in the SOI layer 3.

Next, on the lattice-relaxed SiGe layer 4, a thin S
By forming i, the strain S having tensile strain
An i layer 5 can be formed.

Most of the dislocations 33 generated in the conventional SOI layer 3 are considered to be generated in the lattice-relaxed SOI layer 3 and confined in this layer, so that they do not propagate into the lattice-relaxed SiGe layer 4. Have been.

However, when annealing is performed at 1100 ° C. for 1 hour in a nitrogen atmosphere to relax the lattice, the lattice is propagated to the surface of the SiGe layer 4 at a density of about 1/10 μm ² , and this defect is distorted in the strained Si. It was found that the crystallinity of the layer 5 was deteriorated. After that, a semiconductor element such as a MOSFET is formed on the strained Si layer 5. However, deterioration of the crystallinity of the strained Si layer 5 may greatly deteriorate the characteristics of the semiconductor element. This is expected to become more remarkable as the size of the semiconductor element is reduced.

Defects generated when the SiGe layer 4 is lattice-relaxed may be amplified even in a subsequent process of forming gates and electrodes, and in a high-temperature treatment process such as crystallinity recovery annealing after ion doping. Further, the crystallinity of the strained Si layer 5 may be degraded.

In order to prevent the dislocations 33 generated in the SOI layer 3 for lattice relaxation from propagating to the SiGe surface, the SiG
The e-layer 4 has to be formed several micrometers or more.

However, in order to sufficiently exert the effect of the SOI substrate structure such as suppressing the influence of the stray capacitance, S
It is necessary to minimize the thickness from the iO ₂ insulating layer 2 to the strained Si layer 5 as the channel layer. Therefore several μm
In this method, in which the SiGe layer 4 must be formed, the effect of the SOI substrate structure cannot be sufficiently exhibited.

[0020]

As described above, according to the conventional method, a semiconductor device having a strained Si layer serving as a channel layer formed on an SOI substrate requires an SOI substrate insulating film to suppress defects. There is a problem in that if the film thickness on the SOI substrate insulating film becomes thinner if the film thickness on the SOI substrate insulating film becomes thinner, the defects are amplified.

Accordingly, the present invention provides both a thinner film on the insulating layer of the SOI substrate and a reduction in the defects of the strained layer serving as the channel layer, and by applying a sufficient strain to the channel layer to obtain a higher performance semiconductor device. It is an object of the present invention to provide a semiconductor device, a method of manufacturing a semiconductor substrate, and a semiconductor substrate which can be formed at low cost.

[0022]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a substrate, an insulating film formed on the substrate, and a lattice relaxation formed substantially in contact with the insulating film. An undoped first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer and having a lattice constant smaller than that of the first semiconductor layer and having a tensile lattice strain, A gate insulating film selectively formed on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a channel region formed on the surface of the second semiconductor layer immediately below the gate insulating film. And a source / drain region provided at least in the second semiconductor region and separated from each other via the channel region.

Further, the present invention provides a process for forming an insulating film on a substrate surface, a process for forming a laminated substrate having a laminated layer in which a first semiconductor layer is formed on a second semiconductor layer, And bonding the laminated substrate to the insulating film and the first semiconductor layer, and the laminated substrate so that at least a part of the first semiconductor layer and the second semiconductor layer remain. Forming a stacked structure of the lattice-relaxed first semiconductor layer and the second semiconductor layer to which a tensile lattice strain has been applied, and forming a transistor in the stacked structure. Of the semiconductor device.

The present invention also relates to a method for forming an insulating film on a surface of a substrate, forming a first semiconductor layer on a surface of a semiconductor substrate, and combining the insulating film and the first semiconductor layer. Laminating the substrate and the semiconductor substrate, removing the semiconductor substrate so that at least the first semiconductor layer remains, and relaxing the lattice of the first semiconductor layer; Forming a stacked structure by laminating a second semiconductor layer on the second semiconductor layer and applying a tensile lattice strain to the second semiconductor layer; and forming a transistor in the stacked structure. is there.

The present invention also provides a substrate, an insulating film formed on the substrate, an undoped first semiconductor layer with a lattice relaxed formed on the insulating film, and an insulating film on the first semiconductor layer. And a second semiconductor layer having tensile lattice distortion formed on the substrate.

In the present invention, the lattice constant of the second semiconductor layer is smaller than that of the first semiconductor layer. A typical material for the first semiconductor layer is SiG
e, and a typical material for the second semiconductor layer is Si.

By the way, the radius of the covalent bond between Si and Ge is:
1.17 and 1.22, respectively.

By stacking a SiGe layer and a Si layer in this order on a Si substrate by a normal epitaxial growth technique, FIG.
As shown in the figure, the lattice of the SiGe layer 4 'is deformed vertically in conformity with the lattice of the underlying Si layer 3, and a tensile strain in the vertical direction is generated in the SiGe layer 4'. The Si layer 5 'formed on the SiGe layer 4' does not receive sufficient tensile strain.

For example, Japanese Patent Application Laid-Open No. H11-121377 discloses that the covalent radius of B (boron) is 0.88, and that the dopant concentration in the SiGe layer is 10 ²⁰ -1.
This is the result of adding B at 0 ²¹ atoms / cm ³ . This technique eliminates the need for CMP after cutting in the hydrogen stripping method when producing an SOI substrate. FIG. 2B schematically shows the lattice matching in this technique, in which B
An additional SiGe layer 4 ″ is laminated, and a Si layer 5 ′ is further laminated. The B-doped SiGe layer 4 ″ is used as an etching stopper and will be removed later. The above-mentioned document states that the Si layer 5 'can be used as a device layer, but this Si layer is
(B) It contains B thermally diffused from the layer 4 ″ and has residual compressive strain. Si layer 5 as this device layer
No distortion is applied to '.

Further, in order to form a strained Si layer as a device layer, as shown in FIGS.
Although it can be achieved by a method of forming a three-layer structure of SiGe / Si, there is a problem that dislocations 33 propagate to the Si layer 5. FIG. 2 shows the semiconductor device and the semiconductor substrate of the present invention.
C, a lattice-relaxed SiGe layer 4 is formed substantially in contact with the silicon oxide film 2 and a Si layer 5 is formed thereon by a bonding method or the like. At this time, a sufficient tensile strain is generated in the Si layer 5 in the lateral direction of the figure by the lattice-relaxed SiGe layer 4. Further, since the SOI layer 3 having the dislocations 33 as shown in FIG. 2A is not provided, the problem of deteriorating the crystallinity of the strained Si layer 5 does not occur.

Further, in the manufacturing method of the present invention, it is not necessary to use a high-temperature annealing step as in the prior art to relax the lattice of the SiGe layer. For this reason, threading dislocations and the like are not introduced into the SOI layer by high-temperature annealing, and do not reach the strained Si device layer forming the channel, thereby deteriorating the blocking characteristics. Therefore, in the present invention, the thickness of the SiGe layer can be made smaller than that of the prior art, and the SiGe layer on the insulating layer can be made thinner.
Layer and the total thickness of the Si layer can be reduced to about 2/3 of the conventional thickness. Therefore, high quality and sufficient strain without defects can be applied to the semiconductor device layer without losing the effect of the SOI structure.

In the present invention, the thickness of the first semiconductor layer is 80 nm or less, and the thickness of the second semiconductor layer is 10 nm or more and 5 nm or less.
It is preferable that the total thickness of the first semiconductor layer and the second semiconductor layer be 0 nm or less and 100 nm or less. Thereby, a good strained semiconductor film without defects can be formed.

In the semiconductor device and the semiconductor substrate of the present invention, the second semiconductor layer has a Si composition, the first semiconductor layer has a Ge composition of less than 100% on the second semiconductor layer side, and has a Ge composition on the side opposite to the second semiconductor layer. A SiGe layer greater than 0% is desirable. More preferably, the second semiconductor layer is Si,
Is preferably a SiGe layer having a Ge composition of at least 30 atm% on the second semiconductor layer side.

In the present invention, the interstitial distance of the first semiconductor layer may be non-uniform in the thickness direction by using the first semiconductor layer as a graded composition. For example, the second of the first semiconductor layer
Of which the Ge composition on the semiconductor layer side is greater than 30 atm%
It is desirable that the Ge composition of the iGe layer, opposite to the second semiconductor layer, is less than 30 atm%.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 3 is a sectional view of a semiconductor substrate for explaining a method of manufacturing a semiconductor substrate according to a first embodiment of the present invention.

First, as shown in FIG. 3A, a Si oxide film 2 is formed on a Si substrate 1 in advance. The Si oxide film 2 is formed by dr
Thermal oxide films such as y-oxide film and wet oxide film, and CVD (Che
medical Vapor Deposition) membrane,
It can be formed by a widely used method such as a wet oxide film by solution processing.

Next, as shown in FIG. 3B, a SiGe layer 4 is formed on another Si substrate 21 in advance. The SiGe layer 4 is basically undoped. In addition, the SiGe layer 4 needs to have at least a Ge composition on the Si substrate 21 side of less than 100% and a Ge composition on the surface side of more than 0%. Further, the SiGe layer 4 has a Ge composition of more than 30 atm% for higher performance, and at least a Ge composition on the Si substrate 21 side of 30 atm%.
% Is desirable. Ge composition of 30 atm
This is because if it is larger than%, the electron mobility in the strained Si layer can be increased. On the other hand, the Ge composition of the SiGe layer 4 is desirably 80 atm% or less.

The SiGe layer 4 is formed by CVD (Chemica).
l Vapor Deposition), MBE (M
Molecular beam epitaxy), a sputtering process, or the like. Si
When the Ge layer 4 is formed by CVD, a Si raw material gas and a Ge raw material gas are heated to, for example, 550 ° C.
It is introduced on the substrate 21 and laminated.

Next, the upper surface 2s of the Si oxide film 2 is
The substrates 1 and 21 are bonded together with the upper surface 4s of the layer 4 aligned. As an example of the bonding method, several hundred degrees (for example, 4
Pre-annealing of about 100 to 700 ° C. and high-temperature annealing (for example,
(100 ° C., 1 hour). In this step, SiGe
Since the layer 4 is not lattice-relaxed, no dislocation occurs.

Next, as shown in FIG. 3C, the Si substrate 21 is peeled off. At this time, the compressive strain received from the Si substrate 21 is released, and the lattice of the SiGe layer 4 is relaxed.

At this time, if the Si layer 5 on the surface of the Si substrate 21 is left very thin, the SiGe layer 4 is lattice-relaxed and, at the same time, tensile strain is introduced into the Si layer 5. By doing so, a good strained Si layer 5 without dislocations, pits or protrusions
Can be formed.

The Si substrate 1, the Si oxide film 2 formed on the Si substrate 1 and the Si oxide film 2
Lattice-relaxed SiGe layer 4 formed by lamination on top
Then, a semiconductor substrate including the strained Si layer 5 formed on the lattice-relaxed SiGe layer 4 is formed.

The Si oxide film 2 and the lattice-relaxed SiGe layer 4 are substantially in direct contact with each other, but may have an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm at the interface. The interface buffer layer is made of, for example, Si.

A polishing or peeling step is performed on the SiGe layer 4 to first relax the lattice of the SiGe layer 4,
It is also possible to form the strained Si layer 5 by regrowing the silicon layer very thinly by E or CVD.

By removing the Si substrate 21 on which the SiGe layer 4 has been formed in advance, the SiGe layer 4 is removed.
To relax the lattice, the thickness of the strained Si layer 5 formed on the SiGe layer 4 is 10 nm to 50 nm, and the total thickness of the SiGe layer 4 and the strained Si layer 5 is 3 nm.
It is desirable that the thickness be 0 to 100 nm. Thereby, a good strained semiconductor film without defects can be formed.

The removal or thinning of the Si substrate 21 can be performed by polishing, for example, chemical polishing or chemical mechanical polishing for reducing the thickness using a chemical solution or an abrasive, or PACE (PACE) for improving the uniformity of the thickness after thinning. plasma assiste
A d chemical dry etching method or the like may be used. In addition, the SiGe layer 4 or Si
A hydrogen stripping method in which hydrogen is injected into the substrate 21 and then stripped from the surface into which hydrogen has been injected, or a thinning method in which the Si substrate 21 is stripped with an HF solution after oxidization may be used.

In the present invention, the SiGe thin film 4 having a sufficiently small thickness of, for example, 50 nm is formed on the Si substrate 21 before the bonding step.
Is formed, the SiGe layer 4 exists as a layer to which a compressive strain is applied. However, this compressed Si
After the lamination, the effect of applying a strain from the Si substrate 21 to the SiGe layer 4 is reduced by thinning or peeling off the Si substrate 21 after the lamination. Thus, the strain of the SiGe layer 4 can be released. As a result, a function as a stressor for applying a strain to the Si device layer, which is an object of the present invention, is exhibited.

The position for removing the Si substrate 21 is
It depends on the specifications of the process such as the thickness of the substrate 21 and the crystallinity. At this time, for example, when a solution etching or a stripping step after hydrogen implantation is used, the surface after stripping may be roughened. In particular, in the PACE method, defects due to the process may be introduced from the surface.

In these cases, for example, hydrogen,
When a step of performing annealing in an atmosphere of argon, nitrogen, oxygen, or the like to recover the crystal surface or the inside of the crystal of the Si substrate 21 is added, a more uniform and high-quality thin film process is realized.

The Si substrate 1 and the Si substrate 21 are made of CZ, F
A Z, MCZ substrate or the like is used. In particular, the Si substrate 21
When the surface is used as it is as a Si device layer after thinning or stripping, it is effective to use an FZ substrate with less oxygen precipitation for improving the crystallinity.

By selecting the density and type of impurities in the Si substrate 21, a desired resistance value can be set to the Si substrate 2.
It is also possible to make them in advance on the surface of one.

The SOI structure having the strained Si device layer 5 having a desired thickness formed as described above has a total thickness on the Si oxide film insulating layer 2 which is 2/3 that of the semiconductor substrate shown in FIG. It can be made as thin as possible. Also,
The dislocation density appearing on the surface of the SiGe layer 4 is reduced by 10% or more, and a higher quality strained Si device layer 5 can be formed.

FIG. 12 is a cross-sectional view of a MISFET (MOSFET) formed on the strained silicon layer 5 described above. This MISFET is formed as follows. First, strain S
The surface of the i-layer 5 is thermally oxidized to form a thin gate oxide film 101 of about 10 nm. Next, for example, an n-type impurity ion for adjusting a threshold voltage is implanted into the channel region via gate oxide film 101 to form an n-type channel region.

Next, the gate electrode 1 is formed on the gate oxide film 101.
After forming a polysilicon film 2 to be 02 by a low pressure CVD method, this polysilicon film is formed by RIE (Reactive).
The gate electrode 102 is formed by patterning using (eIon Etching).

Next, after selectively implanting n-type impurity ions such as phosphorus ions using the gate electrode 102 as a mask, annealing is performed at, for example, about 800 ° C. to thereby form the n-type source region 103 and the n-type drain region. 104 is formed on the gate electrode 102 in a self-aligned manner. An n-channel MISFET is formed in this manner, but the p-channel MISFE is formed by changing impurities to p-type.
T can be formed similarly.

The MISFET formed as described above is
Since it is formed in the strained Si layer, electron scattering in the channel region is suppressed and electron mobility is improved. Also MI
Since the SFET is formed in a thin SOI layer having a thickness of 100 nm or less, the parasitic capacitance is reduced in addition to the improvement of the electron mobility. As a result, a MISFET excellent in driving force can be obtained.

(Second Embodiment) FIG. 4 is a sectional view showing a method for manufacturing a semiconductor substrate according to a second embodiment of the present invention.

In this embodiment, after forming an epitaxial Si layer 6 on a Si substrate 21, a SiGe layer 4 is laminated, and a Si oxide film 9 formed on the SiGe layer 4 is used as one of the bonded substrates. Is done.

First, as shown in FIG. 4A, a Si oxide film 2 is previously formed on a Si substrate 1 in the same manner as in the first embodiment.

Next, as shown in FIG.
An Si layer 6 serving as an element formation layer is formed on an i-substrate 21 by an epitaxial method, and a SiGe layer 4 is formed on the Si layer 6 in the same manner as in the first embodiment. The SiGe layer 4 is basically undoped. The SiGe layer 4 has a Ge composition of at least less than 100% on the Si layer 6 side.
Is required to be greater than 0%. Further, the SiGe layer 4 has a Ge composition of at least 30 at the side of the Si layer 6, more desirably, 30% for higher performance.
It is desirable to make it larger than atm%. Ge composition of 30
This is because if it is larger than atm%, the electron mobility in the strained Si layer can be increased. On the other hand, SiGe
The Ge composition of the layer 4 is desirably 80 atm% or less.

After that, a Si oxide film 9 is formed on the SiGe layer 4.

Next, as shown in FIG. 4C, the Si oxide film 2
The two Si substrates 1 and 21 are bonded together in the same manner as in the first embodiment, together with the upper surface 2s of the silicon oxide film 9 and the upper surface 9s of the Si oxide film 9. As a result, as shown in FIG.
Oxide film 9 is integrated to form Si oxide film 12. After bonding, the Si substrate 12 is peeled off.

When peeling is performed by hydrogen implantation after bonding, the interface between Si layer 6 and Si substrate 21 or S
After injecting hydrogen into the i layer 6, the Si substrate 21 is peeled off.
By doing so, the compressive strain received from the Si substrate 21 is released, and the lattice relaxation of the SiGe layer 4 is performed, and at the same time, the strain is introduced into the Si layer 6 serving as the element forming layer.

Thus, the Si substrate 1 and the Si substrate
An Si oxide film 12 formed on a substrate 1 and a lattice-relaxed SiG film formed on the Si oxide film 12 by lamination.
A semiconductor substrate including the e-layer 4 and the strained Si layer 6 formed on the lattice-relaxed SiGe layer 4 is formed.

The strained Si layer 6 thus formed is
An ideal thin film layer having a desired resistance value with less oxygen precipitation and impurities contained in the CZ substrate is realized.

Although the Si oxide film 2 and the lattice-relaxed SiGe layer 4 are substantially in direct contact with each other, an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm may be provided at the interface. The interface buffer layer is made of, for example, Si.

In the second embodiment, since the Si layer 6 serving as an element formation layer can be formed in advance so as to exhibit desired electric characteristics, a regrowth process is not required. After the SiGe layer 4 is formed, a silicon oxide film 9 is further formed, and the oxide film 2 is formed.
And 9 are bonded together to increase the SiGe
The effect on the layer 4 can be reduced.

In addition to the case where the process proceeds continuously in a clean atmosphere, for example, when the process is performed in the atmosphere, it is assumed that an oxide film is formed on the SiGe layer 4. The silicon oxide film 9 in FIG. 4B may be formed unintentionally.

Thereafter, as in the first embodiment, the MISFET shown in FIG. 12 is formed on the strained Si layer. Also in the second embodiment, a MISFET excellent in driving force can be obtained.

(Third Embodiment) FIG. 5 is a sectional view of a semiconductor substrate showing step by step a method of manufacturing a semiconductor substrate according to a third embodiment of the present invention.

The third embodiment is that the SiGe layer 7 shown in FIG. 5C has a composition distribution in the thickness direction. That is, as shown in FIG. 6, the Ge concentration in the SiGe layer 7 is
The crystal is grown so that the concentration is low on the side and high on the strained Si layer 8 side. This makes the interstitial distance of the SiGe layer 7 non-uniform in the thickness direction.

At this time, it is necessary that the Ge composition on the Si substrate 1 side is higher than 0% and the Ge composition on the Si layer 8 side is less than 100%. Specifically, the Si concentration is set so that the Ge concentration on the Si substrate 1 side is higher than 0 atm% and 30 atm% or lower, and the Ge concentration on the strained Si layer 8 side is higher than 30 atm% and lower than 100 atm%, more preferably 80 atm% or lower.
It is desirable to control the Ge composition in the Ge layer 7.

By controlling the composition of the SiGe layer 7 as described above, the dislocation generated from the interface between the Si oxide film 2 and the SiGe layer 7 proceeds so as to form a loop in the SiGe layer 7 and It does not reach the interface of the strained Si layer 8. Therefore, a better strained Si layer 8 can be provided.

Hereinafter, a method for manufacturing a semiconductor substrate will be described.

First, as shown in FIG. 5A, an Si oxide film 2 is formed on a Si substrate 1 in advance in the same manner as in the first embodiment.

Next, as shown in FIG. 5B and FIG.
The SiGe layer 7 is formed on the substrate 21. Ge at this time
The composition was controlled such that the Ge composition from the Si substrate 21 gradually decreased as described above.

Next, the upper surface 2s of the Si oxide film 2 is
Two Si substrates and 2
1 is bonded in the same manner as in the first embodiment.

Next, as in the first embodiment, the Si substrate 21
Is removed, and the SiGe layer 7 is lattice-relaxed.

At this time, if the Si layer on the surface of the Si substrate 21 is left very thin, the SiGe layer 4 is lattice-relaxed and, at the same time, tensile strain is introduced into the Si layer 8. By doing so, a good strained Si layer 8 without dislocations, pits or protrusions can be formed.

Thus, the Si substrate 1 and the Si substrate
A Si oxide film 2 formed on a substrate 1, a lattice-relaxed SiGe layer 7 formed by laminating on the Si oxide film 2 and having a Ge composition gradually changed;
A semiconductor substrate including the strained Si layer 8 formed on the layer 7 is formed.

Although the Si oxide film 2 and the lattice-relaxed SiGe layer 7 are substantially in direct contact with each other, an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm may be provided at the interface. The interface buffer layer is made of, for example, Si.

A polishing or peeling step is performed to the SiGe layer 7 to first relax the lattice of the SiGe layer 7,
It is also possible to form the strained Si layer 8 by regrowing the silicon layer very thinly by E or CVD.

In this embodiment, the G in the SiGe layer 7 is
Since the e concentration is lower as it is closer to the Si oxide film 2, defects generated at the interface between the Si oxide film 2 and the SiGe layer 7 are confined to the Si oxide film 2 side, and the strained Si layer 8 of the bonded SiGe layer 7 is bonded. At the interface with, a lattice-relaxed SiGe layer is obtained. Thereby, a strained Si layer 8 having a tensile strain is formed on the SiGe layer 7 which has been sufficiently relaxed.

The thickness of each layer, the annealing temperature,
The degree of relaxation varies depending on the annealing time, the thickness of the Si substrate layer 21 that is left after peeling or polishing after bonding, and depending on the process conditions, it is possible to form a Si device layer with or without compression ratio distortion. It is.

Thereafter, similarly to the first embodiment, the MISFET shown in FIG. 12 is formed on the strained Si layer. Also in the third embodiment, a MISFET excellent in driving force can be obtained.

(Fourth Embodiment) FIG. 7 is a sectional view showing a method for manufacturing a semiconductor substrate according to a fourth embodiment of the present invention.

In the fourth embodiment, the Ge concentration in the SiGe layer 7 on the Si substrate 21 shown in FIG. 7B has a concentration gradient in the film thickness direction as shown in FIG. It is located not in the interface but in the SiGe layer 7. afterwards,
A peeling or thinning process is performed so that a portion having a high Ge concentration gradient becomes a surface, and the surface indicated by a dotted line in FIGS. 7B and 8 becomes the upper surface 7s of the thinned SiGe layer 7. The semiconductor substrate shown in FIG. 7C obtained by using the substrate in which the composition of the SiGe layer 7 is controlled is Si
The dislocation generated from the interface between the oxide film 2 and the SiGe layer 7 'is S
Proceeding to form a loop in the iGe layer 7
It does not reach the interface between the e layer 7 'and the strained Si layer 8. Therefore, a better strained Si layer can be provided.

Further, since the crystal growth of the SiGe layer 7 before bonding starts from a low Ge concentration on the Si substrate 21, defects due to mismatch are less likely to be introduced, and a SiGe layer 7 'having good crystallinity is obtained. .

Hereinafter, a method for manufacturing a semiconductor substrate will be described.

First, as shown in FIG. 7A, a Si oxide film 2 is previously formed on a Si substrate 1 in the same manner as in the first embodiment.

Next, as shown in FIG. 7B and FIG.
The SiGe layer 7 is previously formed on the substrate 21 so that the Ge composition ratio becomes 0 atm% → 35 atm% → 0 atm% in the film direction. Subsequently, the film is thinned to the central portion where the Ge composition ratio of SiGe 7 is the highest, thereby forming a SiGe layer 7 ′. As a result, Si
A surface having a Ge composition ratio of 35 atm% is exposed on the upper surface 7s of the Ge layer 7 '.

Next, the upper surface 2s of the Si oxide film 2 is
The two Si substrates 1 and 2 are aligned with the upper surface 7 of 7 ′.
1 is bonded in the same manner as in the first embodiment. Then, the first
The Si substrate 21 is removed in the same manner as in the embodiment of FIG.
'Is lattice relaxed. At this time, S on the surface of the Si substrate 21
If the i-layer is left very thin, the SiGe layer 4 is lattice-relaxed and, at the same time, tensile strain is introduced into the Si layer 8. By doing so, a good strained Si layer 8 without dislocations, pits or protrusions can be formed.

Thus, the Si substrate 1 and the Si substrate
A Si oxide film 2 formed on a substrate 1, a lattice-relaxed SiGe layer 7 formed by laminating on the Si oxide film 2 and having a Ge composition gradually changed;
A semiconductor substrate including the strained Si layer 8 formed on the layer 7 'is formed. Thereby, an effect similar to that of the third embodiment can be obtained.

The Si oxide film 2 and the lattice-relaxed SiGe layer 7 'are substantially in direct contact with each other, but may have an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm at the interface. The interface buffer layer is made of, for example, Si.

A polishing or peeling step is performed to the SiGe layer 7 to first relax the lattice of the SiGe layer 7,
It is also possible to form the strained Si layer 8 by regrowing the silicon layer very thinly by E or CVD.

Thereafter, as in the first embodiment, M shown in FIG.
An ISFET is formed on the strained Si layer 8. Also in the fourth embodiment, a MISFET excellent in driving force can be obtained.

(Fifth Embodiment) FIG. 9 is a sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor substrate according to a fifth embodiment of the present invention.

In the fifth embodiment, a SiGe layer composed of a lattice-relaxed SiGe layer 40 into which dislocations are introduced and a lattice-relaxed SiGe layer 11 is formed on a Si substrate 21. SiG
The e-layer 40 is sufficiently thick and has a Ge concentration that changes with crystal growth, and serves as a so-called buffer layer. For example, in the SiGe buffer layer 40, the Ge concentration on the Si substrate 21 is 0 atm%, the Ge concentration increases with the crystal growth, and the Ge concentration becomes 3 at a thickness of 2 μm.
The structure has a gradient composition of 0 atm%.

Hereinafter, a method for manufacturing a semiconductor substrate will be described.

First, as shown in FIG. 9A, a Si oxide film 2 is formed on a Si substrate 1 in advance in the same manner as in the first embodiment.

Next, as shown in FIG. 9B, a SiGe buffer layer 40 having a Ge composition as described above is formed on another Si substrate 21 to be sufficiently thick to relax the lattice. At this time, Si
Dislocations 33 occur in the Ge buffer layer 4 but are sufficiently thick that they do not affect the semiconductor layer formed thereon. Next, a SiGe layer 11 having a lattice-relaxed good crystal state is formed on the lattice-relaxed SiGe buffer layer 4. The method of growing each layer of SiGe is in accordance with the first embodiment.

Next, the first surface 2s of the Si oxide film 2 and the first surface 11s of the lattice relaxed SiGe layer 11
The two Si substrates 1 and 21 are bonded together in the same manner as in the embodiment.

Next, the Si substrate 21 and the SiGe buffer layer 4 are removed by polishing or hydrogen implantation. Next, the strained Si layer 8 is formed on the lattice-relaxed SiGe layer 11. (FIG. 9C) Thus, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, and the lattice-relaxed SiG formed on the Si oxide film 2 by lamination.
A semiconductor substrate including the e-layer 11 and the strained Si layer 8 formed on the lattice-relaxed SiGe layer 11 is formed.

In the SiGe buffer layer 40, defects such as threading dislocations and misfit dislocations caused by lattice mismatch on the Si substrate 21 side in the SiGe buffer layer 40 are confined. As a result, on the surface side of the SiGe buffer layer 40,
A lattice-relaxed SiGe layer without dislocations is realized.

The surface side Ge of the SiGe buffer layer 40
The concentration is such that a desired strain is applied to the Si device layer, and is typically greater than 30 atm% and 8%.
0 atm% or less, and the Ge concentration distribution in the film thickness direction does not need to be uniform. Subsequent to the formation of the SiGe layer 40, by growing the SiGe layer 11 having the same composition as the surface side composition of the SiGe buffer layer 4, the high-quality relaxed SiGe layer 11 with reduced defect density such as dislocation is formed. You.

The problem here is that the crystal growth of the SiGe layer 40 having a thickness of several μm as a buffer layer requires a raw material and a growth time, and requires a process cost. As described above, a laminated structure of the strain channel layer and the relaxed SiGe layer can be realized by the thinning process after the lamination. However, in order to obtain a SiGe layer of a desired thickness before bonding, for example, a depth cut surface of about 0.3 μm
Hydrogen may be implanted into c (FIG. 9B), and peeling may be performed after bonding. This makes it possible to reuse the lattice-relaxed SiGe buffer layer remaining after peeling, thereby simplifying the process and saving semiconductor resources, and thus reducing the substrate manufacturing cost.

Thereafter, similarly to the first embodiment, M shown in FIG.
An ISFET is formed on the strained Si layer 8. Also in the fifth embodiment, a MISFET excellent in driving force can be obtained.

(Sixth Embodiment) FIG. 10 shows a sixth embodiment of the present invention.
FIG. 5 is a cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a semiconductor substrate according to an example.

In the sixth embodiment, the lattice-relaxed SiGe buffer layer 40 into which dislocations are introduced, the lattice-relaxed SiGe layer 11, the strained Si layer 10, Another lattice relaxed SiGe
After the continuous formation of the layer 13, a laminating process is performed.

First, as shown in FIG.
An Si oxide film 2 is formed on the upper surface in the same manner as in the first embodiment.

Next, as shown in FIG. 10B, a thick SiGe buffer layer 40 is formed on another Si substrate 21 in advance, as in the fifth embodiment, to relax the lattice. On the lattice-relaxed SiGe buffer layer 40, a lattice-relaxed SiGe layer 1
1. A strained Si layer 10 and a lattice-relaxed SiGe layer 13 are successively grown.

Next, as shown in FIG. 6C, the upper surface 2s of the Si oxide film 2 and the upper surface 13s of the lattice-relaxed SiGe film 13
The Si substrates 1 and 21 are bonded in the same manner as in the first embodiment.

Next, the Si substrate 21 and the lattice-relaxed S are formed by polishing or hydrogen implantation so that the strained Si layer 10 is exposed on the surface.
The iGe buffer layer 40 and the lattice-relaxed SiGe layer 11 are removed. (FIG. 10C) Thus, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, and the Si substrate
Lattice-relaxed SiG formed by bonding on oxide film 2
A semiconductor substrate including the e layer 13 and the strained Si layer 10 formed on the lattice-relaxed SiGe layer 13 is formed.

In this embodiment, the Si layer 10 on the lattice-relaxed SiGe layer 11 formed on the Si substrate 21 is naturally subjected to tensile strain, and the SiGe layer 13 thereon is a relaxed layer.

The lattice-relaxed SiGe layer 13 has a gradient in Ge composition as in the third or fourth embodiment in order to reduce defects generated from the interface between the insulating layer 2 and the SiGe layer 13 after bonding. May be attached.

On the lattice-relaxed SiGe layer 13,
As in the second embodiment, the bonding may be performed after the insulating layer 9 is formed in advance.

In the sixth embodiment, SiGe having a high relaxation rate is used.
The strained Si layer 10 can be directly formed on the layer 13 and the Ge concentration in the lattice-relaxed SiGe layer 13 can be arbitrarily selected between 30 atm% and less than 100 atm%. And S on the insulating layer 2
The thickness of each of the iGe layer 13 and the strained Si device layer 10 can be set to 10 nm or less.

As a result, the total thickness on the insulating film 2 is reduced to 40 n
m, the SOI effect can be sufficiently achieved, and sufficient strain can be applied to the Si device layer 10.

Thereafter, similarly to the first embodiment, also in the sixth embodiment, a MISFET excellent in driving force can be obtained.

(Seventh Embodiment) FIG. 11 shows a seventh embodiment of the present invention.
FIG. 5 is a cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a semiconductor substrate according to an example.

In this embodiment, a SiGe substrate 31 is used instead of the Si substrate 21 as one of the bonded substrates.
Lattice-relaxed SiGe layer 11, strained Si layer 10, lattice-relaxed SiGe layer 13, and Si oxide film 9 regrown on Ge substrate 31
The structure will be described.

First, as shown in FIG.
An Si oxide film 2 is formed on the upper surface in the same manner as in the first embodiment.

Next, as shown in FIG. 11B, a SiGe layer 11 is previously formed on the SiGe substrate 31 in the same manner as in the first embodiment, and the Si layer 10 and the SiG layer are formed on the SiGe layer 11.
An e-layer 13 (Ge composition on the Si layer 10 side is larger than 30 atm%) and a Si oxide film 9 are continuously grown.

Next, the Si substrate 1 and the SiGe film are aligned so that the upper surface 2s of the Si oxide film 2 and the upper surface 9s of the Si oxide film 9 are aligned.
The substrate 31 is bonded in the same manner as in the first embodiment. next,
The SiGe substrate 31 and the SiGe layer 11 are removed by polishing or hydrogen implantation so that the Si layer 10 is exposed on the surface.

In this way, as shown in FIG.
i-substrate 1, Si oxide film 12 formed on Si substrate 1, lattice-relaxed SiGe layer 13 formed by bonding on Si oxide film 12, and lattice-relaxed SiGe
A semiconductor substrate composed of the strained Si layer formed on the layer is formed.

In this case, at least one of the Si oxide film 2 and the Si oxide film 9 may be used for bonding. Further, in order to obtain an effect of closing a defect that may occur from a bonding surface between the SiGe layer 13 and the insulating layer 9 during the bonding step, the thinning step, or the peeling step, the Ge concentration in the SiGe layer 13 in contact with the insulating layer must be reduced. It is good to make it uneven.

In this embodiment, the case where the substrate 31 has the same SiGe composition as the layer 11 to be the stressor has been described.
It is also possible to control the composition in a layer formed on the substrate to set a desired concentration.

Thereafter, similarly to the first embodiment, M shown in FIG.
An ISFET is formed in the strained Si layer 10. Also in the sixth embodiment, a MISFET excellent in driving force can be obtained.

Further, in the first to seventh embodiments, the case where the layer (first semiconductor layer) to which strain is applied is a SiGe layer and the device layer (second semiconductor layer) is a Si layer has been described. What is the combination of two layers having different lattice constants such that the second semiconductor layer has a lattice constant smaller than the lattice constant of the first semiconductor layer so that tensile strain is generated in the second semiconductor layer? May be selected. Specifically,
Si, GaAs, SiC, GaN, GaAlAs, In
GaP, InGaPAs, Al ₂ O ₃ , BN, BNC,
C, highly doped Si (impurity B), Si
(Impurity P), Si (impurity As), SiNx, ZnS
The effects of the present invention can be obtained by combining two kinds of substances such as e. However, the concentration of B contained in the first semiconductor layer is desirably less than 1 × 10 ²⁰ atm%.

In the first to seventh embodiments, the substrates 1 and
As the substrates 21 and 31, Si substrates and SiGe substrates were used, but GaAs, ZnSe, SiC, Ge, sapphire,
Any of organic glass, inorganic glass, and plastic may be used.

In the first to seventh embodiments, the insulating film 2,
Although a silicon oxide film was used as 9, a silicon oxynitride film,
Another insulating film such as a silicon nitride film may be used.

[0133]

As described above, according to the present invention, crystallinity degradation of a device layer due to a defect propagated from a strained layer as a stressor, which has been difficult in the past, can be reduced, and the total amount of the insulating layer on the SOI structure can be reduced. It is possible to reduce the thickness. Therefore, deterioration of device characteristics is suppressed, power consumption is reduced,
High integration is possible, and high performance of the semiconductor element can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate for describing a conventional method of manufacturing a semiconductor substrate.

FIG. 2 is a cross-sectional view of a substrate for describing the present invention and a conventional method for manufacturing a semiconductor substrate.

FIG. 3 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor substrate according to the present invention.

FIG. 4 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor substrate according to the present invention.

FIG. 5 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor substrate according to the present invention.

FIG. 6 shows G of the SiGe layer in the semiconductor substrate of the present invention.
The figure which shows e composition.

FIG. 7 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor substrate according to the present invention.

FIG. 8 shows G of the SiGe layer in the semiconductor substrate of the present invention.
The figure which shows e composition.

FIG. 9 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor substrate according to the present invention.

FIG. 10 is a cross-sectional view of a substrate for describing a method of manufacturing a semiconductor substrate according to the present invention.

FIG. 11 is a cross-sectional view of a substrate for describing the method for manufacturing a semiconductor substrate of the present invention.

FIG. 12 is an element cross-sectional view illustrating a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Insulating layer (Si oxide film layer) 3 ... SOI layer 4 ... SiGe layer 5 ... Strained Si layer 6 ... Strained epitaxial Si Layer 7 ... Gradient composition SiGe layer 8 ... Strained Si layer formed by regrowth 9 ... Insulating layer 10 ... Strained Si layer 11 ... SiGe layer 12 ... Insulating layer 13 ... SiGe layer 21 ... Si substrate 31 ... SiGe substrate 33 ... Dislocation

Claims (9)

[Claims] A substrate; an insulating film formed on the substrate; an undoped first semiconductor layer formed substantially in contact with the insulating film and lattice-relaxed; A second semiconductor layer having a lattice constant smaller than that of the first semiconductor layer and having a tensile lattice strain, and a gate insulating film selectively formed on the second semiconductor layer. A gate electrode formed on the gate insulating film, a channel region formed on the surface of the second semiconductor layer immediately below the gate insulating film, and at least the second semiconductor region via the channel region. And a source / drain region provided apart from each other. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer is a SiGe layer having a Ge composition of at least 30 atm% on the side of the second semiconductor layer, and the second semiconductor layer is Si. Semiconductor device. 3. The method according to claim 1, wherein the first semiconductor layer is a SiGe layer,
The Ge composition on the substrate side is 30 atm% or less, the Ge composition on the second semiconductor layer side is larger than 30 atm%, and the second semiconductor layer is Si. Semiconductor device. 4. A step of forming an insulating film on a surface of a substrate;
Forming a laminated substrate having a laminated layer in which the semiconductor layer is formed on a second semiconductor layer, and laminating the substrate and the laminated substrate so that the insulating film and the first semiconductor layer are aligned with each other. Removing the laminated substrate so that at least a part of the first semiconductor layer and the second semiconductor layer remains, and the first semiconductor layer lattice-relaxed;
A method for manufacturing a semiconductor device, comprising: forming a stacked structure with the second semiconductor layer to which a tensile lattice strain has been applied; and forming a transistor in the stacked structure. 5. The step of forming a laminated substrate having a laminated layer in which a first semiconductor layer is formed on a second semiconductor layer,
The method further includes the step of laminating an insulating layer on the first semiconductor layer, and the step of laminating the substrate and the laminated substrate such that the insulating film and the second semiconductor layer are laminated on the substrate, 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of bonding the formed insulating film and the insulating film formed on the first semiconductor layer so as to match each other. 6. A step of forming an insulating film on a surface of a substrate, a step of forming a first semiconductor layer on a surface of a semiconductor substrate, and forming the first semiconductor layer on the surface of the semiconductor substrate so that the insulating film and the first semiconductor layer are aligned. Bonding the semiconductor substrate;
Removing the semiconductor substrate so that at least the semiconductor layer remains, and lattice-relaxing the first semiconductor layer; and laminating a second semiconductor layer on the first semiconductor layer and forming a second semiconductor layer on the second semiconductor layer. A method for manufacturing a semiconductor device, comprising: forming a stacked structure to which a tensile lattice strain is applied; and forming a transistor in the stacked structure. 7. The step of forming a laminated substrate having a laminated layer in which a first semiconductor layer is formed on a second semiconductor layer,
The method further includes the step of laminating an insulating layer on the first semiconductor layer, and the step of laminating the substrate and the laminated substrate such that the insulating film and the first semiconductor layer are laminated on the substrate. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of bonding the formed insulating film and the insulating film formed on the first semiconductor layer so as to match each other. 8. The first semiconductor layer is a SiGe layer,
The second semiconductor layer is a Si layer, and the step of forming the first semiconductor layer includes the step of forming the first semiconductor layer such that the Ge composition of the first semiconductor layer on the side to be combined with the insulating layer is 30% or less, G on the surface side of the first semiconductor layer in contact with the second semiconductor layer
8. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of controlling the composition of the first semiconductor layer so that the e composition has a gradient composition of greater than 30%. 9. A substrate, an insulating film formed on the substrate, an undoped first semiconductor layer with a lattice relaxed formed on the insulating film, and formed on the first semiconductor layer. A second semiconductor layer having tensile lattice strain.