JP2002184962A - Semiconductor substrate, manufacturing method, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate with an SOI structure having a very thin strain relief SiGe layer with a very low transition density and with excellent flatness of its surface even if a strained Si channel structure or a strained SiGe structure is employed. SOLUTION: After an SiGe layer 14 is formed on a silicon layer 13 of a substrate 21, a P++ doped SiGe layer 15 with a thickness about 10 nm-100 nm is formed and then an SiGe layer 16 with a thickness of about 500 nm-1000 nm is formed. With such a constitution, a tensile tension is applied to the silicon layer 13, the strains of the SiGe layers 14, 15, and 16 are relieved, and then the SiGe layers 15 and 16 are removed by etching with the SiGe layer 15 as an etching stopper.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon (Serial)
The present invention relates to a semiconductor substrate having an On Insulator) structure, a semiconductor device using the semiconductor substrate, and a method of manufacturing the same, particularly to a complementary metal oxide semiconductor (CMOS) transistor and a modulation doped field effect transistor (MODF
ET), and semiconductor devices such as heterojunction bipolar transistors (HBTs).

[0002]

2. Description of the Related Art Conventionally, a semiconductor device having a so-called strained Si (silicon) channel or strained SiGe (silicon-germanium) channel structure has been proposed in order to improve the operating characteristics of a transistor. According to this semiconductor device,
The carrier mobility at room temperature is significantly higher than that of a device having a Si channel structure having the same carrier density.
The value of 5 times or more, ie, 00 cm ² / Vs and 1050 cm ² / Vs in the case of a hole, is obtained, which enables further high-speed operation of the transistor.

[0003]

However, the strain Si
The SiGe layer under the channel or strained SiGe channel has a disadvantage that a larger leak current occurs because the band gap is smaller than that of Si. This disadvantage can be solved by forming a strained Si layer or a strained SiGe layer on an insulating substrate. However, even in this case, the distance between the insulating layer and the channel layer is reduced in order to prevent generation of a leak current. It is necessary.

[0004] For this reason, as a conventional manufacturing example, a thick SiG
e Strain relaxation S formed on gradient composition buffer (1 μm) layer
There has been reported a method of obtaining an SiO ₂ layer as an insulating layer by injecting oxygen into an iGe layer and annealing the iGe layer. However, even in this method, the distance from the insulating layer to the channel layer is 300 n.
m or more, and it was difficult to obtain a structure in which the thickness of the SiGe layer was suppressed to 100 nm or less with good controllability.

On the other hand, in order to form these strained layers,
A thick SiGe gradient composition buffer layer (10%
/0.5 to 1 µm), but a very long film thickness was required, so a long time was required for the formation, and the control of the gradient composition was troublesome. In addition, the film quality has a high threading dislocation density (about 10 ⁶ / cm ² ) and a large surface roughness (10
nm), which was not endurable for device applications.

As described above, the strain relaxation S on the conventional insulating substrate
The iGe layer is thick and unsuitable for application to FETs and the like, and has a disadvantage that the film quality of the relaxed SiGe film is low, which is disadvantageous when considering an integrated device such as an LSI.

Accordingly, the present invention has been made in view of the above problems, and employs a strained Si channel or strained SiGe channel structure, but has an extremely thin strain-relaxed SiGe having an extremely low transition density and excellent surface flatness. An object of the present invention is to provide a semiconductor substrate having an SOI structure having a layer and a method for manufacturing the same.

The present invention also relates to a strained Si channel or strained S channel.
Even though the iGe channel structure is adopted, a semiconductor substrate having an SOI structure having an ultra-thin strain-relaxed SiGe layer having an extremely low transition density and excellent surface flatness is used to achieve miniaturization of the element and excellent operating characteristics. It is an object to provide a semiconductor device and a method for manufacturing the same.

[0009]

Means for Solving the Problems As a result of intensive studies, the present inventor has come up with the following aspects of the invention.

The present invention is directed to a semiconductor substrate having a semiconductor substrate provided with a semiconductor film via an insulating film, that is, a semiconductor substrate having an SOI structure. The semiconductor substrate of the present invention is configured such that the semiconductor film has a thickness less than or equal to a critical thickness of strain relaxation for silicon germanium in a bulk state, and a tensile stress is applied to the silicon layer, and the strain is relaxed by itself. It is formed by laminating a silicon-germanium layer.

In this case, it is preferable that the silicon-germanium layer has a strain relaxation rate of 80% or more with respect to silicon-germanium in a bulk state.

Further, the present invention is directed to a semiconductor device using the semiconductor substrate having the above structure. In this case, in addition to the configuration of the semiconductor substrate described above, a tensile stress is applied by the silicon-germanium layer on the silicon-germanium layer, so that a strained semiconductor layer that forms a channel of the semiconductor element is formed. .

Further, the present invention is directed to a method for manufacturing a semiconductor substrate having the above structure. The method of manufacturing a semiconductor substrate according to the present invention includes the steps of: forming the silicon layer so as to have a thickness equal to or less than a critical thickness of strain relaxation for silicon germanium in a bulk state; Gives a tensile stress, and the strain is relaxed.
Forming a second silicon-germanium layer on the first silicon-germanium layer; applying a tensile stress to the silicon thin film; silicon·
Etching the second silicon-germanium layer after the germanium layer has been relaxed.

In this case, the method further comprises a step of forming a third silicon-germanium layer on the second silicon-germanium layer, the third silicon-germanium layer complementing the strain relaxation of the first and second silicon-germanium layers. The second silicon-germanium layer is used as an etching stopper,
Preferably, the third silicon germanium layer is removed by etching.

According to another aspect of the method of manufacturing a semiconductor substrate of the present invention, a step of forming the silicon layer so as to have a thickness equal to or less than a critical thickness for strain relaxation with respect to silicon germanium in a bulk state; Applying a tensile stress to the silicon layer, forming a silicon-germanium layer which itself is strain-relaxed, and heat-treating the silicon-germanium layer, thereby applying a tensile stress to the silicon layer. Causing strain relaxation in the first silicon-germanium layer.

The present invention is also directed to a method for manufacturing a semiconductor device using the semiconductor substrate having the above structure. In this case, a tensile stress is given by the first silicon-germanium layer to the above-described method for manufacturing a semiconductor substrate,
A step of forming a strained semiconductor layer forming a channel of the semiconductor element is added.

In the present invention, the SiGe layer (first SiGe
By stacking the layers on a thin silicon layer (SOI layer), dislocations due to lattice mismatch can be confined at the interface between the SOI layer and the SiO ₂ layer, and a SiGe layer with excellent crystallinity can be obtained. At this time, the thickness of the SOI layer is set to SiGe
By keeping the thickness within the critical thickness for the layer, the generation of dislocations is suppressed in the SOI layer as well as in the SiGe layer.

Further, after the desired SiGe layer thickness is achieved, the SiGe layer (second S
iGe layer), for example, a p ⁺⁺ doped SiGe layer (first
Is formed, followed by undoped SiGe
A layer (third SiGe layer) is formed to relax the SiGe layer and then allow etching to remove the p ⁺⁺ doped SiGe layer. In this case, since selective etching is used, a surface with extremely excellent flatness can be obtained.

Further, as described above, the second and third SiGe
Without forming a layer, a SiGe layer (first SiGe
After forming a layer, this is subjected to a heat treatment at elevated temperature (for example, 800 ° C.).
To 900 ° C.). By this heat treatment, relaxation of the SiGe layer approaches the thermal equilibrium state, and a sufficient tensile stress can be applied to the silicon layer, so that the number of steps can be reduced as a whole.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments to which the present invention is applied will be described below in detail with reference to the drawings.

(First Embodiment) In this embodiment, the distortion S
SOI (Semiconductor On) for realizing a semiconductor device having an iGe (silicon-germanium) channel structure
Insulator) substrate. Here, the structure will be described together with the manufacturing method for convenience.

FIG. 1 is a schematic sectional view showing a method of manufacturing an SOI substrate according to the present embodiment in the order of steps. First, FIG.
As shown in ( ₁ ), a substrate 21 is prepared in which an extremely thin silicon film 13 having a thickness of about 20 nm is formed on a silicon semiconductor substrate 11 via a silicon oxide film (SiO ₂ film) 12. Here, the thickness of the silicon film 13 is S
The critical film thickness for strain relaxation for i _1-x Ge _x (0 <x <1) (10 nm to 20 nm at x = 0.3) or less.

As the substrate 21, the silicon oxide film 1
A silicon oxide film 12 is formed by implanting oxygen ions into a bonded substrate in which a single crystal Si layer is bonded on the substrate 2 or a silicon semiconductor substrate 11, and the silicon film 1 is formed as an upper layer.
3 is used. However, regarding the threading dislocation density, the bonded substrate (10 ² to ³
/ Cm ² ) is smaller than the SIMOX substrate (10 ⁶ / cm ² ), and therefore, the use of the bonded substrate is preferable because the crystallinity of the SiGe layer grown thereon is also excellent. This is also advantageous from the viewpoint of the yield in LSI implementation.

Subsequently, as shown in FIG.
SiGe (Si _1-x
Ge _x : 0 <x <1) The layer 14 is formed by epitaxial growth. Here, since Ge has a lattice constant about 4% larger than that of Si, the SiGe layer 14 is
3 is given a tensile stress. On the other hand, the SiGe film 1
4 increases, and when the accumulated stress exceeds the dislocation generation energy, strain relaxation of the SiGe layer 14 occurs.
Although the thickness of the SiGe layer 14 is about 50 nm to 200 nm, it is preferable that the thickness be about 200 nm or more in consideration of sufficiently relaxing the strain of the SiGe layer 14.

Subsequently, as shown in FIG.
Phosphorus ion (P ⁺⁺ : B, for example) doped with the same Ge composition (x) or a Ge composition that compensates for distortion due to the dopant on the e layer 14 (doping concentration:
(About 1%) of the SiGe layer 15 having a thickness of 10 nm to 100 n.
m. As described later, this SiGe layer 1
5 functions as an etching stopper.

Subsequently, a SiGe layer 16 is formed on the SiGe layer 15 by epitaxial growth. This SiG
The e-layer 16 is intended to apply an additional stress to the silicon layer 13 and is formed to have a thickness in the range of 500 nm to 1000 nm, whereby the strain relaxation for the SiGe layers 14 and 15 is sufficiently complemented. At this time, the silicon layer 1
3, the effect of the silicon layer 13 and SiGe
Since no dislocations occur in layer 14, no dislocations are generated in the SiGe crystal and the surface remains flat as before strain relaxation occurred.

The method of forming such a SiGe layer is described in Yang et al.
According to J. Sci. Technol. B16, 1489 (1998), the SOI layer is thinned to about 20 nm on the SOI substrate, and when a SiGe layer is grown thereon, a threading dislocation caused by strain relaxation causes the SOI layer and the silicon This is a more generalized method based on the report that it can be confined at the oxide film interface.

Thereafter, as shown in FIG.
The SiGe layers 15 and 16 are removed by etching using an OH solution. At this time, the SiGe layer 15 functions as an etching stopper, so that only the SiGe layers 15 and 16 formed for relaxing strain are removed, and the semiconductor substrate 11, the silicon oxide film 12, the silicon layer 13, and the SiGe layer 14 as shown in the figure are removed. The final structure of the SOI substrate made of In the SOI substrate, the silicon layer 13 and S
The iGe layer 14 forms the SOI layer 10.

Here, further, in a hydrogen atmosphere,
It is preferable to perform a hydrogen annealing treatment at a temperature of from 900C to 900C. Thereby, contamination of the impurity (B) due to the P ⁺⁺ -doped SiGe layer 15 can be removed.

[0030] As described above, according to this embodiment, also employing a strained Si channel or strain SiGe channel structure, threading dislocation density is very low (~10 ² ~ ³ / cm
² ) Excellent surface flatness (surface roughness: ~ 0.1n)
m), ultra-thin single-crystal strain-relaxed SiGe suitable for high-speed operation
It is possible to realize a semiconductor substrate having an SOI structure having the layer 14.

(Second Embodiment) Next, a second embodiment will be described. Here, a semiconductor substrate having an SOI structure (and a method of manufacturing the same) is illustrated as in the first embodiment, but differs in that a part of the manufacturing process is different. Note that components and the like common to the SOI substrate of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

FIG. 2 is a schematic sectional view showing a method of manufacturing an SOI substrate according to the present embodiment in the order of steps. First, FIG.
As shown in FIG. 5, the substrate 21 is passed through the first half of the steps, that is, the steps of FIGS. 1A to 1C shown in the first embodiment.
An SiGe layer 14 is formed on the silicon film 13 by epitaxial growth. Here, the thickness of the SiGe layer 14 may be suppressed to about 100 nm.

Subsequently, as shown in FIG.
Elevated temperature treatment for the e-layer 14, here 800 ° C to 900
Annealing is performed at 10 ° C. for about 10 to 30 minutes. As a result, the SiGe layer 14 approaches a thermal equilibrium state, relaxation of strain is promoted, and a final structure of the semiconductor substrate including the semiconductor substrate 11, the silicon oxide film 12, the silicon layer 13, and the SiGe layer 14 as shown is obtained.

[0034] As described above, according to this embodiment, also employing a strained Si channel or strain SiGe channel structure, threading dislocation density is very low (~10 ² ~ ³ / cm
² ) Excellent surface flatness (surface roughness: ~ 0.1n)
m), ultra-thin single-crystal strain-relaxed SiGe suitable for high-speed operation
It is possible to realize a semiconductor substrate having an SOI structure having the layer 14.

Further, as in the first embodiment, SiGe layers 15 and 16 are formed to induce strain relaxation.
It is not necessary to increase the thickness of the entire e-layer, and the heat treatment of the SiGe layer 14 provides the effect of relaxing the strain. Therefore, the number of steps can be reduced as a whole.

(Third Embodiment) In the present embodiment, the first
Alternatively, a semiconductor device formed using a semiconductor substrate having an SOI structure manufactured according to the second embodiment,
A transistor will be exemplified. Here, the structure will be described together with the manufacturing method for convenience.

FIG. 3 is a schematic sectional view showing a method of manufacturing the MOS transistor according to the present embodiment in the order of steps. First, as shown in FIG. 3A, the SOI substrate 1 goes through the steps of the first embodiment (FIG. 1) or the first embodiment (FIG. 2).
Is prepared.

Subsequently, as shown in FIG.
On the SiGe layer 14 of the substrate 1, a strained Si layer (or strained SiGe layer) 2 doped with p-type or n-type impurities is formed. The thickness of the strained Si layer 2 is 50 nm or less for a fully depleted device, and 1 for a partially depleted device.
It is set to about 00 nm to 200 nm. A tensile stress is applied to the strained Si layer 2 by the SiGe layer 14 existing below.

Subsequently, as shown in FIG. 3C, the SOI layer 10 is selectively oxidized by a so-called LOCOS (LOCal Oxidation of Silicon) method to form a field oxide film 3 to define an active region.

Subsequently, a gate insulating film 4 is formed on the strained Si layer 2 and patterned into a desired shape.

Subsequently, as shown in FIG. 3D, p-type or n-type impurities are ion-implanted into the surface layer of the SOI layer 10 on both sides of the gate insulating film 4 using the gate insulating film 4 as a mask. The drain 5 is formed. As a result, a channel 6 is formed in the SOI layer 10 below the gate insulating film 4, and the source / drain 5 functions as a contact electrode to this channel.

Through the above steps, a MOS transistor using a strained Si channel (or a strained SiGe channel) is completed.

When performing element isolation, the above-described LO
A technique other than the COS method may be used. For example, as shown in FIG. 4, the SOI layer 10 is patterned to form an open groove 7 in an element isolation region to define an active region, and furthermore, the open groove 7 is buried with an insulator to form a CMP (Chemical Mechanical).
It is also preferable to flatten the surface by a (Polishing) method.

[0044] As described above, according to this embodiment, also employing a strained Si channel or strain SiGe channel structure, threading dislocation density is very low (~10 ² ~ ³ / cm
² ) Excellent surface flatness (surface roughness: ~ 0.1n)
m), ultra-thin single-crystal strain-relaxed SiGe suitable for high-speed operation
It is possible to realize a semiconductor substrate having an SOI structure having the layer 14.

By using such an SOI substrate 1 to form a MOS transistor, it is possible to miniaturize the device and greatly improve the operation characteristics.

Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Supplementary Note 1) A semiconductor substrate comprising a semiconductor substrate and a semiconductor film provided with an insulating film interposed therebetween, wherein the semiconductor film has a thickness less than or equal to a critical thickness for strain relaxation with respect to silicon germanium in a bulk state. A semiconductor substrate comprising a layer and a silicon-germanium layer that applies a tensile stress to the silicon layer and has its strain relaxed.

(Supplementary Note 2) The semiconductor substrate according to Supplementary Note 1, wherein the silicon-germanium layer has a strain relaxation rate of 80% or more with respect to silicon-germanium in a bulk state.

(Supplementary Note 3) A semiconductor device comprising a semiconductor substrate having a semiconductor film provided on a semiconductor substrate with an insulating film interposed therebetween, and a semiconductor element formed on the semiconductor substrate. A silicon layer having a thickness equal to or less than the critical thickness of strain relaxation for silicon germanium in a bulk state, a tensile stress applied to the silicon layer, and a silicon germanium layer itself strain relaxed, and the silicon germanium layer A semiconductor device characterized by being laminated with a strained semiconductor layer to which a tensile stress is applied and a channel of the semiconductor element is formed.

(Supplementary Note 4) A method of manufacturing a semiconductor substrate having a silicon layer on a semiconductor substrate via an insulating film,
A step of forming the silicon layer so as to have a thickness equal to or less than a critical film thickness for strain relaxation of silicon germanium in a bulk state, and applying a tensile stress to the silicon layer on the silicon layer, whereby the strain is relaxed itself. Forming a first silicon-germanium layer, forming a second silicon-germanium layer on the first silicon-germanium layer, applying a tensile stress to the silicon layer, Etching the second silicon-germanium layer after strain relaxation occurs in the first silicon-germanium layer.

(Supplementary Note 5) A step of forming a third silicon-germanium layer on the second silicon-germanium layer, the third silicon-germanium layer complementing strain relaxation of the first and second silicon-germanium layers, The second silicon
The method of manufacturing a semiconductor substrate according to claim 4, wherein the second and third silicon-germanium layers are removed by etching using the germanium layer as an etching stopper.

(Supplementary Note 6) After the second and third silicon-germanium layers are removed by etching, the first
5. The method of manufacturing a semiconductor substrate according to claim 4, further comprising the step of performing a hydrogen annealing treatment on a surface of the silicon-germanium layer of the above (a) to clean the surface.

(Supplementary Note 7) A method of manufacturing a semiconductor substrate having a silicon layer on a semiconductor substrate via an insulating layer,
A step of forming the silicon layer so as to have a thickness equal to or less than a critical film thickness for strain relaxation of silicon germanium in a bulk state, and applying a tensile stress to the silicon layer on the silicon layer, whereby the strain is relaxed itself. Forming a silicon-germanium layer, and heat-treating the silicon-germanium layer, thereby applying a tensile stress to the silicon layer and causing strain relaxation in the first silicon-germanium layer. A method for manufacturing a semiconductor substrate, comprising:

(Supplementary Note 8) After the second and third silicon-germanium layers are removed by etching, the first
8. The method for manufacturing a semiconductor substrate according to claim 7, further comprising a step of performing a hydrogen annealing treatment on a surface of the silicon-germanium layer to clean the surface.

(Supplementary Note 9) A method of manufacturing a semiconductor device using a semiconductor substrate having a silicon layer on a semiconductor substrate with an insulating layer interposed therebetween, wherein the silicon layer is provided with a criticality of strain relaxation for silicon germanium in a bulk state. Forming a first silicon-germanium layer on the silicon layer, wherein the first silicon-germanium layer is applied with a tensile stress on the silicon layer and the strain of the silicon layer is relaxed; Forming a second silicon-germanium layer on the first silicon-germanium layer; and applying a tensile stress to the silicon layer to cause strain relaxation in the first silicon-germanium layer. Etching the second silicon-germanium layer; and applying a tensile stress by the first silicon-germanium layer, Forming a strained semiconductor layer forming a channel of the conductor element.

(Supplementary Note 10) The method further includes a step of forming a third silicon-germanium layer on the second silicon-germanium layer, which complements strain relaxation of the first and second silicon-germanium layers, 9. The method according to claim 8, wherein the second and third silicon-germanium layers are removed by etching using the second silicon-germanium layer as an etching stopper.

(Supplementary Note 11) A method of manufacturing a semiconductor device using a semiconductor substrate having a silicon layer on a semiconductor substrate with an insulating layer interposed therebetween, wherein the silicon layer is provided with a criticality of strain relaxation to silicon germanium in a bulk state. Forming a silicon germanium layer on the silicon layer to apply a tensile stress to the silicon layer and to reduce the strain on the silicon layer,
Heat-treating the silicon-germanium layer, thereby applying a tensile stress to the silicon layer, and causing strain relaxation in the first silicon-germanium layer; Forming a strained semiconductor layer that forms a channel of a semiconductor element by applying a stress.

[0058]

According to the present invention, a semiconductor substrate having an SOI structure having an ultrathin strain-relaxed SiGe layer having a very low transition density and excellent surface flatness even though a strained Si channel or strained SiGe channel structure is employed. Can be realized.

According to the present invention, a semiconductor substrate having an SOI structure having an extremely thin strain-relaxed SiGe layer having an extremely low transition density and excellent surface flatness, even though a strained Si channel or strained SiGe channel structure is employed. By using the semiconductor device, it is possible to realize a semiconductor device which realizes miniaturization of elements and has excellent operation characteristics.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method for manufacturing an SOI substrate according to a first embodiment in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a method for manufacturing an SOI substrate according to a second embodiment in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a MOS transistor according to a third embodiment in the order of steps.

FIG. 4 is a schematic cross-sectional view showing another method of forming an element isolation in a MOS transistor according to a third embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 SOI substrate 2 strained Si layer (strained SiGe layer) 3 field oxide film 4 gate insulating film 5 source / drain 6 channel 7 open groove 10 SOI layer 11 silicon semiconductor substrate 12 silicon oxide film 13 silicon film 21 substrate

Claims (5)

[Claims] 1. A semiconductor substrate comprising a semiconductor substrate and a semiconductor film provided with an insulating film interposed therebetween, wherein the semiconductor film has a thickness less than a critical thickness for strain relaxation of silicon germanium in a bulk state. A semiconductor substrate, comprising: a silicon germanium layer that applies a tensile stress to the silicon layer and has its strain relaxed. 2. The silicon-germanium layer has a strain relaxation rate of 8 with respect to bulk silicon-germanium.
2. The semiconductor substrate according to claim 1, wherein the content is 0% or more. 3. A semiconductor device comprising: a semiconductor substrate having a semiconductor film provided on a semiconductor substrate via an insulating film; and a semiconductor element formed on the semiconductor substrate, wherein the semiconductor film is in a bulk state. A silicon layer having a thickness equal to or less than the critical thickness for strain relaxation with respect to silicon / germanium, a tensile stress applied to the silicon layer, and a silicon / germanium layer formed by strain relaxation itself; and a tensile stress due to the silicon / germanium layer. And a strained semiconductor layer in which a channel of the semiconductor element is formed is stacked. 4. A method of manufacturing a semiconductor substrate having a silicon layer on a semiconductor substrate via an insulating film, wherein the silicon layer has a thickness less than a critical thickness for strain relaxation of silicon germanium in a bulk state. Forming, on the silicon layer, applying a tensile stress to the silicon layer to form a first silicon germanium layer, which itself is strain-relaxed; and on the first silicon germanium layer, Forming a second silicon-germanium layer on the substrate; and applying a tensile stress to the silicon layer to cause a strain relaxation in the first silicon-germanium layer.
Etching the second silicon-germanium layer. 5. The method according to claim 5, further comprising: forming a third silicon-germanium layer on the second silicon-germanium layer, the third silicon-germanium layer complementing strain relaxation of the first and second silicon-germanium layers. 5. The method according to claim 4, wherein the second and third silicon-germanium layers are etched away using the second silicon-germanium layer as an etching stopper.
3. The method for manufacturing a semiconductor substrate according to item 1.