JP4037803B2 - Method for manufacturing SGOI substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a strained SOI substrate used for manufacturing a strained Si-MOSFET or the like exhibiting a high current driving force.
[0002]
[Prior art]
Conventionally, in order to improve the performance and functionality of CMOS circuit elements, there has been a method of increasing the drive current per unit gate length by shortening the gate length of each transistor and simultaneously reducing the thickness of the gate insulating film. Have been taken. In this way, the size of a transistor for obtaining a necessary drive current can be reduced to enable high integration, and at the same time, the power consumption per unit element can be reduced by lowering the drive voltage. In recent years, however, technical barriers have rapidly increased against shortening the gate length to achieve the required performance improvements.
[0003]
In order to alleviate this situation, it is considered effective to use a channel material with high mobility. A potential candidate for such a high mobility channel material is strained Si. Strained Si has an extensional strain in the in-plane direction of the substrate, and the band structure changes due to the effect of the extensional strain. Therefore, both the mobility of electrons and holes increases compared to unstrained Si. Further, as the strain increases, the electron / hole mobility increases.
[0004]
Usually, strained Si is formed by epitaxial growth on lattice-relaxed SiGe having a larger lattice constant. Moreover, the larger the Ge composition of the underlying SiGe, the greater the strain amount of strained Si, resulting in higher mobility. If a CMOS is formed of MOSFETs having strained Si channels, higher speed operation can be expected than Si-CMOS of the same size.
[0005]
The research group including the present inventors has proposed a MOSFET (strained SOI-MOSFET) in which this strained Si and an SOI (Si-on-insulator) structure are combined, and has further performed an operation verification test (T Mizuno, S. Takagi, N. Sugiyama, J. Koga, T. Tezuka, K. Usuda, T. Hatakeyama, A. Kurobe, and A. Toriumi, IEDM Technical Digests p.934 (1999); T. Tezuka, N. Sugiyama, T. Mizuno and S. Takagi, Symp. On VLSI Technology, p.96 (2002)).
[0006]
The schematic structure of a strained SOI-MOSFET is as follows: a buried oxide film, a lattice relaxed SiGe layer, a strained Si channel, a gate oxide film, and a gate electrode are sequentially stacked on a Si substrate, and source / drain regions are formed on both sides of the strained Si channel. It is formed. In addition to the advantage of the high carrier mobility of the strained Si channel, this structure also has the advantages due to the SOI structure, such as the ability to reduce the junction capacitance and miniaturization while keeping the impurity concentration low. Therefore, if a CMOS logic circuit is configured with this structure, an operation with higher speed and lower power consumption is expected. In particular, the fully-depleted ultra-thin SOI structure is effective for high-end high-speed logic CMOS circuits because the short channel effect can be suppressed without significantly increasing the channel impurity concentration.
[0007]
Conventionally, in order to obtain such an ultra-thin strained SOI structure, a SIMOX method (Separation by implanted oxygen) or a bonding technique has been used for a SiGe film epitaxially grown on a Si substrate (for example, Patent Documents). 1 and 2).
[0008]
However, the former method has a problem in that an SGOI (SiGe-on-insulator) layer having a sufficient Ge composition (about 30%) cannot be formed because the melting point of SiGe decreases due to an increase in Ge composition. .
[0009]
For the latter method, there are a method of forming a strained Si after bonding a lattice-relaxed SiGe layer on the oxide film, and a method of forming a strained Si layer on the lattice-relaxed SiGe in advance and affixing this on the oxide film. Two methods have been reported. However, in any case, the donor substrate to be bonded is an epitaxial wafer having a lattice-relaxed SiGe layer grown thickly (1-3 μm) on the Si substrate or a strained Si layer formed thereon. Problems common to this type of epi-wafer include two points: a large surface roughness, a need for CMP (chemical mechanical polishing) treatment before bonding, and a high threading dislocation density. In particular, the threading dislocation density is 10^Fivecm^-2There is an essential problem that it is the limit to lower it to the level, and that the dislocation density further increases as the Ge composition increases. This is because it is necessary to introduce a large number of lattice defects in order to form lattice-relaxed SiGe on the Si substrate. Therefore, as long as an epitaxial wafer in which lattice-relaxed SiGe is directly formed on a Si substrate is used, it is considered that it is still difficult to reduce threading dislocations.
[0010]
[Patent Document 1]
Japanese Patent No. 2908787
[0011]
[Patent Document 2]
Japanese Patent No. 3037934
[0012]
[Problems to be solved by the invention]
An object of the present invention is to provide a method capable of manufacturing an SGOI substrate and a strained SOI substrate having a SiGe layer having a sufficiently high Ge composition and having a low dislocation density, or a strained SOI substrate having no SiGe layer.
[0013]
[Means for Solving the Problems]
  According to one embodiment of the present invention, a method for manufacturing an SGOI substrate includes heat-treating a stacked structure substrate in which an insulating film, a Si crystal layer, and a strained SiGe crystal layer are stacked over an oxide atmosphere to form an oxide film on the surface. And forming a lattice-relaxed SiGe crystal layer in which the composition of the strained SiGe crystal layer and the Si crystal layer is made uniform to increase the Ge composition over the first SiGe crystal layer; and removing the oxide film formed on the surface Exposing the lattice relaxed SiGe crystal layer;The exposed lattice-relaxed SiGe crystal layer is subjected to hydrogen combustion oxidation to form a SiGe oxide film, and the SiGe oxide film is removed with an ammonium fluoride solution or dilute hydrofluoric acid, or CMP ( chemical mechanical polishing ), CF _Four Thinning the lattice-relaxed SiGe crystal layer by performing reactive ion etching (RIE), chemical dry etching (CDE) using hydrogen containing gas, or wet etching containing hydrogen peroxide;It is characterized by including.
[0014]
  According to another aspect of the inventionSGOI boardIn the manufacturing method, a multilayer structure substrate in which an insulating film, a Si crystal layer, and a strained SiGe crystal layer are stacked on a substrate is heat-treated in an oxidizing atmosphere to form an oxide film on the surface, and the strained SiGe crystal layer and Si Forming a lattice-relaxed SiGe crystal layer having a uniform composition of the crystal layer and increasing the Ge composition over the first SiGe crystal layer; and removing the oxide film formed on the surface to form the lattice-relaxed SiGe crystal layer Exposing, andThe exposed lattice-relaxed SiGe crystal layer is subjected to hydrogen combustion oxidation to form a SiGe oxide film, and the SiGe oxide film is removed with an ammonium fluoride solution or dilute hydrofluoric acid, or CMP ( chemical mechanical polishing ), CF _Four Thinning the lattice-relaxed SiGe crystal layer by performing reactive ion etching (RIE), chemical dry etching (CDE) using hydrogen containing gas, or wet etching containing hydrogen peroxide;It is characterized by including.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In an embodiment of the present invention, a laminated substrate in which an insulating film, a Si crystal layer, and a strained SiGe crystal layer are laminated on a substrate is heat-treated in an oxidizing atmosphere at a temperature of 900 ° C. or more to form an oxide film on the surface. At the same time, a method of forming a lattice-relaxed SiGe crystal layer in which the composition of the strained SiGe crystal layer and the Si crystal layer is made uniform to increase the Ge composition as compared with the first SiGe crystal layer is used. Hereinafter, this method is referred to as an oxidation concentration method. If this method is used, a lattice-relaxed SiGe crystal layer having a sufficiently high Ge composition can be formed. First, for a strained SiGe crystal layer laminated on the substrate via an insulating film and a Si crystal layer, when the Ge composition is x (0 <x <1) and the film thickness is t (nm), The product xt of the composition x and the film thickness t is preferably 10 or more. If these conditions are satisfied, the degree of lattice relaxation (relaxation rate) of the SiGe crystal layer can be sufficiently increased.
[0018]
In the first embodiment of the present invention, an SGOI substrate is manufactured by thinning a lattice-relaxed SiGe crystal layer formed by an oxidation concentration method. The SGOI substrate having the lattice-relaxed SiGe crystal layer thus thinned can be used as a fine fully depleted MOSFET substrate.
[0019]
In the second embodiment of the present invention, a strain relaxed SiGe crystal layer formed by an oxidation concentration method is thinned, and a strained Si crystal layer is epitaxially grown on the thinned lattice relaxed SiGe crystal layer to manufacture a strained SOI substrate. To do. The strained Si crystal layer of the SOI substrate manufactured by such a method has a very low dislocation density.
[0022]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0023]
Example 1
A method for manufacturing a strained SOI substrate in this embodiment will be described with reference to FIGS.
As shown in FIG. 1A, an SOI wafer in which an oxide film 2 having a thickness of 100 nm and an SOI layer 3 having a thickness of 30 nm are sequentially formed on an Si substrate 1 is prepared, and a strained SiGe having a thickness of 150 nm is formed thereon. The layer 4 and the Si cap layer 5 having a thickness of 10 nm are epitaxially grown sequentially.
[0024]
The strained SiGe layer 4 grown in this example has a Ge composition x = 0.15 (Si_0.85Ge_0.15). Epitaxial growth of the strained SiGe layer 4 was performed by UHV-CVD, using disilane and germane as source gases and setting the growth temperature to 550 to 600 ° C.
[0025]
Next, a lattice-relaxed SiGe crystal layer having an increased Ge composition is formed by a technique called the oxidation concentration method described in the previous section (see FIG. 1B). In this embodiment, the wafer of FIG. 1A is thermally oxidized at 1150 ° C. in an oxidizing atmosphere of 50% oxygen / 50% Ar to form an oxide film 6 having a thickness of 280 nm on the surface, and Ge underneath. A first lattice-relaxed SiGe layer 7 having a thickness of 64 nm and having an increased composition is formed.
[0026]
During this oxidation process, Ge atoms are pushed out of the oxide film and enter the SiGe layer. On the other hand, SiO₂Since the diffusion coefficient of Ge in the inside is extremely smaller than that in SiGe, Ge atoms are confined in the SiGe layer. Further, interdiffusion between Ge and Si occurs, the interface between the SOI layer and the SiGe layer that existed before oxidation disappears, and only the SiGe layer 7 having a substantially uniform Ge composition is formed. Since the SiGe layer 7 is formed by such a mechanism, the SiGe film thickness and the Ge composition are in inverse proportion, and the Ge composition increases as the SiGe film thickness decreases. As described above, in order to extrude Ge from the oxide film and sufficiently diffuse the extruded Ge atoms in the SiGe layer, a high temperature of 900 ° C. or higher is required. Since oxidation is performed at such a high temperature, the oxide film exhibits fluidity, and the SiGe layer 7 spreads laterally along with plastic deformation of the oxide film, thereby enabling lattice relaxation.
[0027]
The first lattice relaxed SiGe layer 7 formed after oxidation exhibits a Ge composition x = 0.35 and a relaxation rate R = 0.85. The relaxation rate R is a parameter representing the degree of lattice relaxation, and R = 1−ε / (ε₀x) where ε is the lattice strain parallel to the substrate surface of the target SiGe layer, and ε₀Is the lattice strain parallel to the substrate surface of the Ge crystal thin film grown in lattice matching on the Si substrate). The relaxation rate R is the film thickness t of the strained SiGe layer 4 before oxidation._i(Nm) and Ge composition x_iDepending on, values in the range from 0 to 1 can be taken. R = 1 means a state in which the lattice is completely relaxed. That is, in the state of R = 1, there is no strain in the SiGe lattice. Specifically, x_it_iWhen <10, R is almost 0 and x_it_iAs the value of increases, R also increases and saturates at R = 1. X to obtain a sufficiently large relaxation rate_it_i> 10 and x_it_iIt should be> 12. In this example, x_i= 0.15, for example t_iIf R = 300 nm, R> 0.9 can be achieved. Where t_iIf the thickness is made too thick, there arises a problem that surface roughness and dislocation increase. Therefore, in consideration of the balance between a high relaxation rate and crystallinity and flatness, t_iThe value of is desirably set in the range of 80 nm to 200 nm. This upper limit value depends on the SiGe growth conditions (UHV-CVD, source gas: disilane, germane, growth temperature: 550 to 600 ° C.) used in this example. For example, if a lower growth temperature or a high hydrogen partial pressure is used, t_iIt is also possible to further increase the thickness.
[0028]
Next, the lattice-relaxed SiGe crystal layer is thinned (see FIG. 1C). First, the oxide film 6 formed in FIG. 1B is removed with an ammonium fluoride solution or dilute hydrofluoric acid. The SiGe layer 7 exposed at this stage has a flat surface and does not require CMP, and the threading dislocation density is 1000 cm lower by two orders of magnitude or more than a lattice-relaxed SiGe layer epitaxially grown directly on a conventional Si substrate.^-2It becomes the following values. Therefore, it can be used as an SGOI substrate for a MOSFET as it is at this stage.
[0029]
However, since the SiGe layer 7 is thick, this SGOI substrate is not suitable for use as a fine fully depleted MOSFET substrate. For this reason, in this embodiment, in order to make the SiGe layer thin, hydrogen combustion oxidation (steam oxidation) at 700 ° C. is performed to form the SiGe oxide film 8 on the surface of the SiGe layer 7. When the oxidation treatment is performed at such a low temperature, an oxide film incorporating Ge is generated, so that the SiGe layer 7 is thinned without much change in the Ge composition. In this embodiment, the SiGe layer 7 is thinned to 10 nm. The SGOI substrate having the SiGe layer 7 thus thinned can be used as a fine fully depleted MOSFET substrate.
[0030]
Next, as shown in FIG. 1D, after removing the SiGe oxide film 8 formed in FIG. 1C with an ammonium fluoride solution or dilute hydrofluoric acid, the strained Si layer 9 is formed on the exposed SiGe layer 7. Is grown epitaxially to produce the strained SOI substrate 10.
[0031]
In FIG. 1C, the SiGe layer 7 is thinned by oxidation, but instead of CMP or selective etching (CF_FourThe SiGe layer 7 may be thinned by reactive ion etching (RIE) using a gas containing hydrogen, chemical dry etching (CDE), or wet etching containing hydrogen peroxide).
[0032]
Example 2
A method for manufacturing a strained SOI substrate in this embodiment will be described with reference to FIGS. In this example, a strained Si layer is directly formed on an insulating film on a support substrate by using a bonding method of a donor substrate and a support substrate.
[0033]
A method for manufacturing a donor substrate will be described with reference to FIGS.
In the same manner as in Example 1, an SOI wafer in which an oxide film 2 having a thickness of 100 nm and an SOI layer 3 having a thickness of 30 nm are sequentially formed on an Si substrate 1 is prepared, and a strained SiGe layer 4 having a thickness of 150 nm is formed thereon. The Si cap layer 5 having a Ge composition x = 0.15 and a thickness of 10 nm is sequentially epitaxially grown (see FIG. 2A).
[0034]
Next, according to the same oxidation concentration method as in Example 1, the wafer obtained in FIG. 2 (a) was thermally oxidized at 1150 ° C. in an oxidizing atmosphere of 50% oxygen / 50% Ar, and the surface had a thickness of 280 nm. An oxide film 6 is formed, and a first lattice-relaxed SiGe layer 7 (Ge composition x = 0.35, relaxation rate R = 0.85) having a Ge composition increased and a thickness of 64 nm is formed thereunder (FIG. 5). 2 (b)).
[0035]
Next, as shown in FIG. 2C, the oxide film 6 formed in FIG. 2B is removed with an ammonium fluoride solution or dilute hydrofluoric acid, and then exposed on the exposed first lattice-relaxed SiGe layer 7. Then, a second lattice-relaxed SiGe layer 11 having a thickness of 500 nm and a strained Si layer 12 having a thickness of 20 nm are sequentially epitaxially grown. This strained SOI substrate is used as a donor substrate 15.
[0036]
At this time, the Ge composition of the second lattice relaxation SiGe layer 11 is set to 0.3 which is a value obtained by multiplying the composition x of the first lattice relaxation SiGe layer 7 by the relaxation rate R. Thereby, the lattice strain in the second lattice relaxed SiGe layer 11 becomes completely zero, and the occurrence of surface roughness and dislocation can be suppressed.
[0037]
Referring to FIGS. 3A to 3F, a method for producing an ultra-thin strained SOI substrate in which only a strained Si layer is formed on an oxide film on the surface of a support substrate by bonding a donor substrate and a support substrate together. Will be explained.
[0038]
FIG. 3A shows the donor substrate 15. In this figure, I₁Shows a regrowth interface when the second lattice relaxed SiGe layer 11 is regrown on the first lattice relaxed SiGe layer 7.
[0039]
As shown in FIG. 3B, hydrogen ions are applied to the donor substrate 15 with an acceleration voltage of 50 keV and a dose of 3 × 10.¹⁶cm^-2The damage layer 16 is formed in a region having a thickness of about 70 nm centered at a depth of 300 nm from the surface.
[0040]
The damaged layer 16 is formed by the regrowth interface I between the first lattice relaxed SiGe layer 7 and the second lattice relaxed SiGe layer 8.₁It forms on the surface side rather than. This is because when the damaged layer 16 reaches the first relaxed SiGe layer 7, strain remains in the first relaxed SiGe layer 7, which may induce threading dislocations. However, when the first relaxed SiGe layer 7 is completely lattice relaxed, the formation position of the damage layer 16 is not limited.
[0041]
As shown in FIG. 3C, a substrate having an oxide film 22 having a thickness of 100 nm is prepared on the surface of the support substrate 21, and the strain on the surface of the donor substrate 15 on which the damage layer 16 is formed in FIG. The Si layer 12 is brought into contact and bonded at room temperature.
[0042]
As shown in FIG. 3D, when the bonded substrate is annealed at 550 ° C. in a nitrogen atmosphere, hydrogen gas bubbles and microcracks are generated in the damaged layer 16. The donor substrate 15 can be peeled off.
[0043]
A substrate in which the strained Si layer 12 and the second lattice relaxation SiGe layer 11 are attached to the surface of the support substrate 21 via the oxide film 22 is referred to as a receptor substrate 23. By annealing the receptor substrate 23 at 850 ° C. in a nitrogen atmosphere, the bond between the strained Si layer 12 and the oxide film 22 is enhanced.
[0044]
Next, the remaining damage layer 16 on the receptor substrate 23 and a part of the second lattice relaxation SiGe layer 11 are removed by CMP and planarized. Thereafter, hydrogen combustion oxidation (steam oxidation) is performed at 700 ° C., and the remaining portion of the second lattice relaxation SiGe layer 11 and a part of the strained Si layer 12 are oxidized and removed, and only the strained Si layer 12 having a thickness of 15 nm is removed. Leave (see FIG. 3 (e)). In addition, instead of hydrogen combustion oxidation, CMP or selective etching (CF_FourReactive ion etching (RIE), chemical dry etching (CDE), or wet etching containing hydrogen peroxide) using a gas containing hydrogen, and the rest of the second lattice relaxation SiGe layer 11 and a part of the strained Si layer 12 are removed. It may be removed.
[0045]
Finally, the oxide film 22 around the support substrate 21 is removed to manufacture the strained SOI substrate 30 (see FIG. 3F). Note that the final oxide film peeling step may be omitted depending on the subsequent transistor manufacturing process.
[0046]
On the other hand, a method for reusing a donor substrate will be described with reference to FIGS. FIG. 4A shows the donor substrate 15 peeled from the receptor substrate 23 in the step of FIG. On the surface of the donor substrate 15, the first lattice relaxed SiGe layer 7, a part of the second lattice relaxed SiGe layer 11, and a part of the damaged layer 16 remain. As shown in FIG. 4B, the surface of the donor substrate 15 is planarized by removing the damaged layer 16 by CMP. In addition, instead of CMP, hydrogen combustion oxidation or selective etching (CF_FourThe surface of the donor substrate 15 may be planarized by reactive ion etching (RIE), chemical dry etching (CDE), or wet etching containing hydrogen peroxide) using a gas containing hydrogen. The donor substrate 15 can be reused as the donor substrate 15 shown in FIG. 3A by epitaxially growing the second relaxed SiGe layer 11 and the strained Si layer 12 on the exposed SiGe layer again. In this way, since the donor substrate 15 can be reused many times, the cost increase due to using an expensive SOI substrate in the first cycle is negligible.
[0047]
At this time, the decrease in film thickness due to planarization is minimized, and the second and subsequent regrowth interface I₂Is the first regrowth interface I₁It should be located on the front side. This is because the first regrowth interface I is caused by excessive thinning.₁This is because if the first lattice-relaxed SiGe layer 7 in which the strain remains beyond this is exposed, it will not be able to follow the rapid fluctuation of the strain and surface roughness will occur. However, this is not the case when the first lattice-relaxed SiGe layer 7 is completely lattice-relaxed.
[0048]
In this embodiment, the separation technique by hydrogen ion implantation is used in the step of FIG. 3B, but the ion species is not limited to hydrogen, and for example, He ions may be used. It is naturally possible to use other existing peeling methods. For example, hydrogen ions may be implanted after a high Ge concentration (30% or more) SiGe layer having a thickness of about 20 nm is inserted into the peeling position in the second lattice relaxed SiGe layer 11. When such a method is used, the flatness of the peeling interface can be improved. Alternatively, a method may be used in which a porous Si layer or a porous SiGe layer is inserted at the peeling position and peeled off by a jet water flow.
[0049]
Example 3
With reference to FIGS. 5A to 5F, a method for manufacturing a strained SOI substrate in this embodiment will be described. In this embodiment, a relaxed SiGe layer and a strained Si layer are formed on an insulating film on a support substrate by using a bonding method of a donor substrate and a support substrate.
[0050]
In this embodiment, as shown in FIG. 5A, a donor substrate 15 ′ in which an oxide film 2, a first lattice relaxed SiGe layer 7 and a second lattice relaxed SiGe layer 11 are stacked on an Si substrate 1 is used. . The donor substrate 15 ′ is manufactured by a method similar to that shown in FIG. 2, but no strained Si layer is formed on the surface of the second lattice relaxed SiGe layer 11.
[0051]
As shown in FIG. 5B, hydrogen ions are applied to the donor substrate 15 ′ with an acceleration voltage of 50 keV and a dose of 3 × 10.¹⁶cm^-2The damage layer 16 is formed in a region having a thickness of about 70 nm centered at a depth of 300 nm from the surface. The reason for adopting such conditions is the same as in the case of the second embodiment.
[0052]
As shown in FIG. 5C, a support substrate 21 having an oxide film 22 having a thickness of 100 nm is prepared, and the surface of the donor substrate 15 ′ on which the damage layer 16 is formed in FIG. The second lattice-relaxed SiGe layer 11 is brought into contact and bonded at room temperature.
[0053]
As shown in FIG. 5D, when the bonded substrate is annealed at 550 ° C. in a nitrogen atmosphere, hydrogen gas bubbles and microcracks are generated in the damaged layer 16, so that the damaged layer 16 serves as a boundary from the support substrate 21. The donor substrate 15 ′ can be peeled off. By annealing the strained Si layer 12 and the second lattice relaxed SiGe layer 11 on the surface of the support substrate 21 via the oxide film 22 at 850 ° C. in a nitrogen atmosphere, the strained Si layer 12 and The bond with the oxide film 22 is enhanced.
[0054]
Next, the rest of the damaged layer 16 on the receptor substrate 23 ′ and a part of the second lattice relaxed SiGe layer 11 are removed by CMP and planarized. Thereafter, hydrogen combustion oxidation (steam oxidation) is performed at 700 ° C. to oxidize the remainder of the second lattice relaxation SiGe layer 11 and a part of the strained Si layer 12 to 10 nm on the oxide film 22 of the receptor substrate 23 ′. After the thinned second lattice relaxed SiGe layer 11 ′ is formed, the oxide film is removed. Note that the second lattice relaxation SiGe layer may be thinned only by CMP, omitting the above-described thinning step by oxidation. Also, instead of CMP, CF_FourAlternatively, reactive ion etching (RIE) using a gas containing hydrogen, chemical dry etching (CDE), or wet etching using an acid solution containing hydrogen peroxide may be used. Next, the strained Si layer 24 is epitaxially grown on the second lattice relaxed SiGe layer 11 '(see FIG. 5E).
[0055]
Finally, the oxide film 22 around the support substrate 21 is removed to manufacture the strained SOI substrate 40 (see FIG. 5F). Note that the final oxide film peeling step may be omitted depending on the subsequent transistor manufacturing process.
[0056]
Also in this embodiment, the second relaxed SiGe layer 11 can be epitaxially grown again after the surface of the donor substrate 15 peeled from the receptor substrate 23 in the step of FIG. It is the same. Also in this embodiment, the peeling technique described in Embodiment 2 can be employed.
[0057]
Example 4
With reference to FIGS. 6A to 6F, a method for manufacturing a strained SOI substrate in this embodiment will be described. In this embodiment, the method of Embodiment 2 is modified to form a relaxed SiGe layer and a strained Si layer on the insulating film on the support substrate.
[0058]
In this example, a donor substrate is prepared in the same manner as in Example 2, and after the donor substrate and the support substrate are bonded together, the donor substrate 15 is peeled off from the support substrate 21. Furthermore, the receptor substrate 23 having the strained Si layer 12 and the second lattice relaxed SiGe layer 11 attached to the surface of the support substrate 21 via the oxide film 22 is annealed at 850 ° C. in a nitrogen atmosphere, whereby the strained Si layer 12 And the bond between the oxide film 22 and the oxide film 22 are enhanced. (See FIG. 6 (a)).
[0059]
Next, the remaining damage layer 16 on the receptor substrate 23 and a part of the second lattice relaxation SiGe layer 11 are removed by CMP and planarized. Also, instead of CMP, CF_FourAlternatively, reactive ion etching (RIE) using a gas containing hydrogen, chemical dry etching (CDE), or wet etching using an acid solution containing hydrogen peroxide may be used. Thereafter, thermal oxidation is performed at 1050 ° C. in an oxygen atmosphere (oxidation concentration method) to form an oxide film 25 on the surface, and to form a lattice-relaxed SiGe layer 26 having a Ge composition increased by reducing the thickness to 10 nm below the oxide film 25. (See FIG. 6 (b)). That is, interdiffusion between Ge and Si occurs during this oxidation treatment, and the interface between the strained Si layer 12 and the second lattice relaxed SiGe layer 11 that existed before the oxidation disappears, and a substantially uniform Ge composition. Only the lattice relaxed SiGe layer 26 having Further, the thermal oxidation at 1050 ° C. further enhances the bond between the lattice-relaxed SiGe layer 26 and the oxide film 22 and reduces the interface state density.
[0060]
Next, the oxide film 25 is removed from the surface (see FIG. 6C). Next, a strained Si layer 27 is epitaxially grown on the lattice-relaxed SiGe layer 26, the oxide film 22 around the support substrate 21 is removed, and a strained SOI substrate 50 is manufactured (see FIG. 6C). Note that the final oxide film peeling step may be omitted depending on the subsequent transistor manufacturing process.
[0061]
Also in this embodiment, after planarizing the surface of the donor substrate 15 peeled from the receptor substrate 23 in the step of FIG. 6A, the second relaxed SiGe layer 11 and the strained Si layer 12 are epitaxially grown again and reused. What can be done is the same as in the second embodiment. Also in this embodiment, the peeling technique described in Embodiment 2 can be employed.
[0062]
【The invention's effect】
As described above in detail, according to the present invention, an SGOI substrate and a strained SOI substrate having a sufficiently low Ge composition and a low dislocation density, or a strained SOI substrate having no SiGe layer can be manufactured. .
[Brief description of the drawings]
1 is a cross-sectional view showing a method for manufacturing a strained SOI substrate in Example 1. FIG.
2 is a cross-sectional view showing a method for manufacturing a donor substrate used in manufacturing a strained SOI substrate in Example 2. FIG.
3 is a cross-sectional view showing a method for producing a strained SOI substrate in Example 2. FIG.
4 is a cross-sectional view showing a method for regenerating a donor substrate used for manufacturing a strained SOI substrate in Example 2. FIG.
5 is a cross-sectional view showing a method for producing a strained SOI substrate in Example 3. FIG.
6 is a cross-sectional view showing a method for producing a strained SOI substrate in Example 4. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Si substrate, 2 ... Oxide film, 3 ... SOI layer, 4 ... Strained SiGe layer, 5 ... Si cap layer, 6 ... Oxide film, 7 ... First lattice relaxation SiGe layer, 8 ... SiGe oxide film, 9 ... Strained Si layer, 10 ... strained SOI substrate 10, 11 ... second lattice relaxed SiGe layer, 12 ... strained Si layer, 15 ... donor substrate, 16 ... damaged layer, 21 ... support substrate, 22 ... oxide film, 23 ... receptor Substrate, 24 ... strained Si layer, 25 ... oxide film, 26 ... lattice relaxed SiGe layer, 27 ... strained Si layer 27, 30, 40, 50 ... strained SOI substrate.

Claims (3)

A laminated structure substrate in which an insulating film, a Si crystal layer, and a strained SiGe crystal layer are laminated on a substrate is heat-treated in an oxidizing atmosphere to form an oxide film on the surface, and the composition of the strained SiGe crystal layer and the Si crystal layer is changed. Forming a lattice-relaxed SiGe crystal layer that is homogenized and has a higher Ge composition than the first SiGe crystal layer;
Removing the oxide film formed on the surface to expose the lattice relaxed SiGe crystal layer;
The exposed lattice-relaxed SiGe crystal layer is subjected to hydrogen combustion oxidation to form a SiGe oxide film, and the SiGe oxide film is removed with an ammonium fluoride solution or dilute hydrofluoric acid, or CMP ( chemical mechanical polishing ), CF ₄ is removed. A step of thinning the lattice-relaxed SiGe crystal layer by performing reactive ion etching (RIE), gas dry etching (CDE), or wet etching containing hydrogen peroxide using a gas containing A method for manufacturing an SGOI substrate, comprising: A laminated structure substrate in which an insulating film, a Si crystal layer, and a strained SiGe crystal layer are laminated on a substrate is heat-treated in an oxidizing atmosphere to form an oxide film on the surface, and the composition of the strained SiGe crystal layer and the Si crystal layer is changed. Forming a lattice-relaxed SiGe crystal layer that is homogenized and has a higher Ge composition than the first SiGe crystal layer;
Removing the oxide film formed on the surface to expose the lattice relaxed SiGe crystal layer;
The exposed lattice-relaxed SiGe crystal layer is subjected to hydrogen combustion oxidation to form a SiGe oxide film, and the SiGe oxide film is removed with an ammonium fluoride solution or dilute hydrofluoric acid, or CMP ( chemical mechanical polishing ), CF ₄ is removed. A step of thinning the lattice-relaxed SiGe crystal layer by performing reactive ion etching (RIE) using a gas containing, chemical dry etching (CDE), or wet etching containing hydrogen peroxide;
And a step of epitaxially growing a strained Si crystal layer on the thinned lattice-relaxed SiGe crystal layer. The method for producing an SGOI substrate according to claim 1 or 2 , wherein the hydrogen combustion oxidation is performed at 700 ° C.

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