JP3712599B2 - Semiconductor device and semiconductor substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a high-speed, low-power-consumption field effect transistor, in particular, a semiconductor device including a field effect transistor having strained Ge or strained SiGe as a channel layer, and a semiconductor substrate used for obtaining the semiconductor device.
[0002]
[Prior art]
Ge hole and electron mobility subjected to compressive strain in a plane parallel to the substrate may exceed Si hole and electron mobility in both p and n channels by selecting an appropriate plane orientation. Are known.
[0003]
  FIG. 13 shows one of conventional transistor structures using this strained Ge as a channel (first conventional example). This structure is disclosed in Japanese Patent Laid-Open No. 2-196436. This structure isp-Si on the n-type Si substrate 61 _0.5 Ge _0.5 Buffer layer 62, i-Si _0.5 Ge _0.5 Ge spacer layer 63, i-Ge channel layer 64, i-Si _0.5 Ge _0.5 Ge spacer layer 65, p-Si _0.5 Ge _0.5 Layer 66, i-Si _1-x Ge _x Layer (x = 0.5 → 0) (SiGe cap layer) 67,A Ti Schottky gate electrode 68 is stacked. Further, source / drain regions 69 are formed at both ends immediately below the gate electrode 68.
[0004]
This structure is a so-called modulation-doped FET (MODFET), which is a p-Si that is a doping layer separated from the i-Ge channel layer 64._0.5Ge_0.5Buffer layer 62, i-Si_0.5Ge_0.5Since carriers are supplied from the Ge spacer layer 65 to the channel layer 64, the hole mobility does not decrease due to scattering by the doped impurities. Therefore, it is said that high speed operation utilizing the high mobility of positive holes of strained Ge is possible.
[0005]
A structure similar to this structure is described in E.I. Murakami et al. , IEEE Transactions on Electron Devices, Vol. 41, p. 857 (1994), and Y.M. H. Xie et al. , Applied Physics Letters Vol. 63, p. 2263 (1994).
[0006]
As another conventional technique, a transistor using strained Si subjected to in-plane tensile strain as a channel is also known. The carrier mobility of strained Si is also known to exceed that of Si in both p and n channels, as in the case of strained Ge. Therefore, these transistors are larger at the same gate size than Si channel transistors. Driving force can be obtained. Among them, a transistor structure considered to have the highest practicality is shown in FIG. 14 (second conventional example).
[0007]
This structure has been proposed and demonstrated by a research group including the present inventors (T. Mizuno, S. Takagi, N. Sugiyama, J. Koga, T. Tetsuka, K. Usuda, T. Hatakeyama, A. Kurube, and A. Toriumi, IEDM Technical Digests p.934 (1999)).
[0008]
In this structure, a buried oxide film 72, a SiGe buffer layer 73, a strained Si channel layer 74, a gate oxide film 75, and a gate electrode 76 are sequentially stacked on the Si or SiGe layer 71 to form the SiGe buffer layer 73 and the strained Si channel layer 74. Source / drain regions 77 are formed.
[0009]
In this structure, in addition to the high carrier mobility due to the strained Si channel 74, the existence of the buried oxide film 72 reduces the parasitic capacitance, and the miniaturization can be performed while keeping the impurity concentration low, so that the driving force can be increased. It has both advantages. Therefore, if a CMOS logic circuit is configured with this structure, it is possible to operate at higher speed and with lower power consumption.
[0011]
[Problems to be solved by the invention]
First, the problem that arises when the first conventional example is put to practical use is that the source / drain junction leakage is large. In the structure of the first conventional example, the thickness of the SiGe buffer layer 62 is a considerably large value of 500 nm, but in other similar conventional examples, the thickness is several hundred nm to about 1 μm or more. . This is a thickness necessary for sufficiently reducing the dislocation density of the SiGe buffer layer 62 and thus reducing the dislocation density reaching the channel layer 64. At this time, at the interface between the lower portion of the source / drain diffusion region 69 and the SiGe buffer layer 62, p⁺-N interface (for p-channel) or n⁺A -p junction surface (in the case of n channel) is formed.
[0012]
  Here, since the Ge composition of the SiGe buffer layer 62 is as high as about 50 atm% or more, the band gap value is about 75-60% of the Si band gap value. The reverse bias saturation current of the pn junction is expressed as the sum of the diffusion current and the recombination current. Each component is proportional to the square of the intrinsic carrier density. The intrinsic carrier density increases as the band gap energy decreases. For example, the intrinsic carrier density of Ge is a value that is 1000 times or more that of Si. Therefore, there arises a problem that the junction leakage or off-current between the source / drain region 69 and the SiGe buffer layer 62 in the first conventional example is 2 to 4 digits larger than Si. Considering the leakage current through dislocations in the SiGe buffer layer 62, the off current is further increased. This causes a problem of a significant increase in power consumption when a large-scale circuit is formed. If the SiGe buffer layer 62 having a low Ge composition is used to reduce this leakage, the lattice constant difference from the Ge channel layer 64 will increase, causing dislocations in the channel or releasing strain. As a result, the surface becomes uneven. Therefore, in the first conventional example, a thick SiGe buffer layer 62 having a Ge composition of 50 atm% or more must be used. Therefore, leakage between the source and drain or between the drain and substrate is smaller than that of a Si-based transistor. It is unavoidable that it becomes several orders of magnitude larger.
[0013]
Next, problems of the second conventional example will be described. FIG. 3B shows a band structure in the vicinity of the channel of the second conventional example. As can be seen from FIG. 3B, since the energy of the valence band of the strained Si channel layer 74 is lower than the energy of the valence band edge of the SiGe buffer layer 73, a negative voltage is applied to the gate to form a hole channel. When a bias is applied, a buried channel is formed at the interface between the strained Si channel layer 74 and the SiGe buffer layer 73 before the surface channel is formed.
[0014]
15 shows a current (log (Id) -voltage (Vg) curve of the transistor and the Si-MOSFET of the second conventional example. Due to the presence of the above-described buried channel, characteristics near the threshold voltage are obtained as shown in FIG. (The S factor increases.) The effect of the buried channel becomes more significant as the thickness of the strained Si channel layer 74 becomes thinner, that is, the effect becomes larger as the size is reduced. In this case, it is difficult to set the threshold voltage low.
[0015]
  FIG. 16 shows (Vg (gate voltage) -Vth (threshold voltage))-current characteristics of the transistor of the second conventional example and the Si-MOSFET. The mobility of the buried channel is low due to the influence of alloy scattering in the SiGe buffer layer. Therefore, as shown in FIG. 16, in the second conventional example, the driving power is low at a low gate voltage as compared with the driving power of a normal surface channel Si-MOSFET. For the above reasons, it is difficult to reduce power consumption in the second conventional example.
[0016]
An object of the present invention is to provide a field effect transistor which has a small leakage current between a source and a drain or between a drain and a substrate and can reduce power consumption.
[0017]
Another object of the present invention is to provide a semiconductor substrate from which the field effect transistor can be easily obtained.
[0018]
As for the method of manufacturing the SiGe layer on the oxide film, first, the method (1) requires a base SOI, so that the thickness of the semiconductor layer on the oxide film increases accordingly, and an FET is manufactured. This hinders the shortening of the channel. Further, when SiGe is epitaxially grown on the SOI and annealed for relaxation, dislocation occurs in the SOI layer.
[0019]
In the method (2), a SiGe buffer layer having a thickness of several μm is grown on a Si substrate, and a SiGe thin film having a desired composition is formed thereon. In this case, undulation of the surface having a period of about 1 μm, which is inevitably called a cross hatch, occurs. Furthermore, it is difficult to completely remove dislocations remaining in the buffer layer, and 10⁶cm^-2There is a problem that dislocations occur at a certain density. As the Ge composition increases, the dislocation density tends to increase.
[0020]
In (3), when the Ge composition is increased, Ge is combined with oxygen during evaporation to evaporate, and a continuous buried oxide film is not formed or the surface becomes rough.
[0021]
  Semiconductor substrate capable of suppressing an increase in the thickness of the laminated structure on the oxide film, generation of dislocations, or surface roughness even when the Ge composition is high (30 atm% or more) in manufacturing the SiGe layer on the oxide film There is a need for a production method.
[0022]
  The present invention includes a support base, an insulating film formed on the support base, a semiconductor layer formed on the insulating film and having a source region and a drain region, and formed on the semiconductor layer. In a semiconductor device including a field effect transistor including a gate insulating film and a gate electrode formed on the gate insulating film, the semiconductor layer has a Ge composition of 30 atm% or more provided on the side in contact with the insulating film And a SiGe or Ge channel region having a Ge composition higher than that of the SiGe region provided on the surface opposite to the insulating film.And a Si layer having a thickness of 2 nm or less existing between the SiGe or Ge channel region and the gate insulating film.This is a semiconductor device.
[0023]
  In addition, the present invention includes an insulating film, a first semiconductor layer including a SiGe layer having a Ge composition of 30 atm% or more, and a SiGe layer or a Ge layer having a Ge composition higher than that of the first semiconductor layer on a support substrate. A gate insulating film and a gate electrode are sequentially stacked on a substrate on which a second semiconductor layer is sequentially stacked, and a source region and a drain region are formed in the first and second semiconductor layers,In addition, a Si layer having a thickness of 2 nm or less is provided between the second semiconductor layer and the gate insulating film.A semiconductor device comprising a field effect transistor.
[0024]
  The present invention also provides an insulating film, a first semiconductor layer that is a SiGe layer having a Ge composition of 30 atm% or more, a SiGe layer or a Ge layer that has a Ge composition higher than that of the first semiconductor layer. Two semiconductor layers,Si layer having a thickness of 2 nm or less present on the second semiconductor layerIs a semiconductor substrate characterized by being sequentially laminated.
[0025]
  Note that, as a first manufacturing method of a semiconductor substrate, a step of forming a stacked structure in which an insulating film and a semiconductor layer containing Si and Ge are sequentially stacked on a supporting base, and an oxidation treatment on the semiconductor layer are performed. A method of manufacturing a semiconductor substrate, comprising performing a Si oxide film and a step of forming a SiGe layer having a Ge composition higher than that of the semiconductor layer by performing the process.
[0026]
  Further, as a second method for manufacturing a semiconductor substrate, a step of forming a semiconductor layer containing Si and Ge on a Si layer or SiGe layer formed on a support base via an insulating film, and an oxidation treatment on the semiconductor layer A method for manufacturing a semiconductor substrate, comprising performing a step of forming a Si oxide film and a SiGe layer having a Ge composition higher than that of the semiconductor layer by performing the above.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
A field effect transistor according to the present invention includes a support base, an insulating film formed on the support base, a semiconductor layer formed on the insulating film and having a source region and a drain region, and the semiconductor layer A field effect transistor comprising a gate insulating film formed thereon and a gate electrode formed on the gate insulating film, wherein the semiconductor layer has a Ge composition provided on a side in contact with the insulating film A SiGe region of 30 atm% or more and a SiGe or Ge channel region containing Ge more than the SiGe region provided on the surface opposite to the insulating film are provided.
[0028]
SiGe with a Ge composition of 30 atm% or more is Si_1-xGe_xIt is a compound represented by (1> x ≧ 0.3).
[0029]
  A schematic diagram illustrating one embodiment of a field effect transistor is shown in FIG. An insulating film 2 is formed on the support base 1, and a semiconductor layer is formed on the insulating film 2. The insulating film 2 electrically insulates the support base 1 and the semiconductor layer, and examples thereof include a Si oxide film. The semiconductor layer includes a SiGe buffer layer 3 (first semiconductor layer) having a high Ge composition with a Ge composition of 30 atm% or more, and a channel layer 4 (SiGe layer or Ge layer having a Ge composition higher than that of the first semiconductor layer). A layer formed by laminating a second semiconductor layer) can be given. The substrate 5 is formed by laminating the support base 1, the insulating film 2, the first semiconductor layer, and the second semiconductor layer. Source / drain regions 6 are formed on the substrate 5 and connected to a source electrode (not shown) and a drain electrode (not shown), respectively. Further, the gate insulating film 7 and the gate electrode 8 are laminated to constitute a field effect transistor.
[0030]
  In the field effect transistor according to this embodiment, a SiGe buffer layer 3 having a high Ge composition and a channel layer 4 made of a Ge layer or a SiGe layer are stacked on an insulating film 2. As a result, the leakage current between the source and drain, which has been a problem in the past, can be suppressed to a practical level. Further, an integrated circuit capable of low power consumption and high speed operation utilizing the high mobility of the Ge or SiGe channel can be obtained.
[0031]
This will be described in more detail below.
[0032]
  In the channel layer 4 formed on the SiGe buffer layer 3, strain is introduced into the crystal structure due to the difference in lattice constant between the SiGe buffer layer 3 and the channel layer 4. Thereby, the hole and electron mobility in the channel layer 4 greatly exceeds the hole and electron mobility of Si, and the device speed can be increased. In the channel layer 4, no strain may be introduced, and even in that case, the mobility of electrons and holes is sufficiently higher than that of Si. However, the mobility of electrons and holes is higher when strain is introduced.
[0033]
  FIG. 2 shows an enlarged view of the pn junction portion of the source region or the drain region in the field effect transistor according to the first prior art and this embodiment. FIG. 2A is an enlarged view of the pn junction portion of the source region or drain region of the field effect transistor according to the first conventional example shown in FIG. FIG. 2B is an enlarged view of the pn junction portion of the source region or drain region in the substrate of the field effect transistor according to the present embodiment shown in FIG. In the field effect transistor of this embodiment shown in FIG. 2B, source / drain regions 6 are formed in the SiGe buffer layer 3 and the channel layer 4 formed on the insulating film 2. Due to the presence of the insulating film 2, the leakage current to the support substrate is completely suppressed. In addition, since the channel layer 4 and the SiGe buffer layer 3 are both depleted by applying a gate voltage, the leakage current between the source and the drain is first reduced. Compared to the conventional example, it is significantly reduced.
[0034]
  In contrast, in the first conventional field effect transistor substrate shown in FIG. 2A, an i-Ge channel layer 64 and a SiGe cap layer 67 are stacked on a thick (> 500 nm) buffer layer 62. Yes. A source or drain region 69 is also formed. In FIG. 2A, since the insulating film 2 as shown in FIG. 2B does not exist, leakage to the support base occurs. Further, since the area of the pn junction is large and the transition remaining in the buffer layer 62, the leakage current between the source and the drain is remarkably larger than that in the present embodiment.
[0035]
  FIG. 3A shows a band structure in the vicinity of the channel layer of the field effect transistor according to the present embodiment. As can be seen from FIG. 3A, the energy of the valence band of the channel layer (Ge) 4 is equal to that of the SiGe buffer layer.(Si _0.3 Ge _0.7 )Therefore, when a negative bias is applied to the gate electrode to form a hole channel, only the surface channel is formed. Therefore, the absence of a buried channel as in the second conventional example makes it possible to set the threshold voltage low without deteriorating the characteristics near the threshold voltage. Further, the driving force at a low gate voltage can be increased. For the above reasons, low power consumption can be realized.
[0036]
  In the conventional Si-MOSFET, an SOI substrate having a similar structure is used, but this is mainly aimed at speeding up by reducing the parasitic capacitance between the substrate and the wiring and the junction capacitance of the region. . The role of the insulating film 2 in the present embodiment is to suppress off-current for the SiGe or Ge channel layer, which is practically essential, whereas for the conventional Si-MOSFET, there is an additional role. It only gives function.
[0037]
  In the field effect transistor of this embodiment, the dislocation density of the SiGe buffer layer 3 (first semiconductor layer) is10 ⁶ cm ^{− 2}The following is desirable. Thereby, the yield of the element or LSI can be brought to a practical level. More preferably, the dislocation density is10 ⁴ cm ^-2 It is as follows.
[0038]
  In addition, if the Ge composition depth direction distribution of the SiGe buffer layer 3 (first semiconductor layer) is substantially uniform, no distortion is accumulated in the SiGe buffer layer 3, and therefore, a transition is unlikely to occur. Therefore, in order to reduce the dislocation density, it is desirable that the Ge composition depth direction distribution of the SiGe buffer layer 3 (first semiconductor layer) is substantially uniform.
[0039]
  In the field effect transistor of this embodiment, it is desirable that a Si cap layer is provided between the channel layer 4 (first semiconductor layer) and the gate insulating film 7. This prevents oxidation of the SiGe or Ge surface in the field effect transistor manufacturing process. Furthermore, it is possible to prevent the interface with the gate insulating film 7 from being formed in SiGe or Ge, thereby preventing an increase in interface state. Further, dislocation does not occur when the thickness of the Si cap layer is not more than the critical thickness with respect to the SiGe buffer layer 3 (the minimum thickness at which dislocation occurs due to mismatch of lattice constants). Due to these effects, the carrier mobility can be kept high.
[0040]
  The semiconductor substrate of the present invention is a semiconductor substrate that is used for manufacturing the field effect transistor according to the present invention, and has, for example, two layers having a high Ge composition corresponding to the SiGe buffer layer 3 and the channel layer 4. When a field effect transistor is manufactured using the semiconductor substrate of the present invention, a field effect transistor having a small leakage current between a source and a drain or between a drain and a substrate, high speed operation, and low power consumption is provided. be able to.
[0041]
  In the semiconductor substrate of the present embodiment, the dislocation density of the SiGe buffer layer 3 (first semiconductor layer) is10 ⁶ cm ^-2 The following is desirable. Thereby, the yield of the semiconductor device or LSI can be brought to a practical level. More preferably, the dislocation density is10 ⁴ cm ^-2 It is as follows.
[0042]
  In the semiconductor substrate of the present embodiment, it is preferable that the Ge composition depth direction distribution of the SiGe buffer layer 3 (first semiconductor layer) is substantially uniform.
[0043]
  For example, for the field effect transistor according to the present invention, a semiconductor substrate on which a SiGe layer having a high Ge composition (30 atm% or more) is formed as a SiGe buffer layer is required. In the first and second semiconductor substrate manufacturing methods used for manufacturing the semiconductor substrate having the SiGe layer having the high Ge composition, the insulating film formed on the support base is directly formed on the insulating film or on the insulating film. A semiconductor layer including a Si and Ge layer having a low Ge composition is formed on the Si layer or SiGe layer formed above, and is oxidized, specifically, heat-treated in an oxidizing atmosphere to simultaneously produce the Si oxide film. A high Ge composition SiGe layer enriched with Ge is generated.
[0044]
  That is, by subjecting a semiconductor layer including Si and Ge layers having a low Ge composition to oxidation, Si atoms are selectively oxidized from the surface of the semiconductor layer including Si and Ge layers having a low Ge composition to form a Si oxide film. Further, Ge atoms are discharged from the formed Si oxide film and accumulated in the semiconductor layer containing Si and Ge inside the semiconductor layer. this is,SiO ₂ The bond between Si and OGeO ₂ Alternatively, the oxygen atom is preferentially bonded to the Si atom because it is chemically more stable than the Ge—O bond of GeO. Therefore, Ge is concentrated to produce a SiGe layer and a Si oxide film having a high Ge composition.
[0045]
  What is necessary is just to remove the Si oxide film produced | generated at this time as needed. Further, a step of forming a channel layer or the like is performed as necessary.
[0046]
  According to the first and second manufacturing methods, the semiconductor layer containing Si and Ge is oxidized, specifically, heat treatment is performed in an oxidizing atmosphere so that Ge atoms are sufficiently contained in the semiconductor layer containing Si and Ge. The Ge concentration in the generated SiGe layer becomes uniform. If this layer is used as, for example, a SiGe buffer layer in a field effect transistor according to the present invention, distortion in the SiGe buffer layer due to nonuniform Ge composition does not occur. As a result, after sufficient lattice relaxation, the dislocation density10 ⁶ cm ^-2 The following can be suppressed.
[0047]
  This will be described with reference to FIGS. FIG. 4 is a diagram for explaining a Ge composition distribution during oxidation of the semiconductor layer containing Si and Ge in the method for manufacturing a semiconductor substrate. Semiconductor layer in which Ge atoms contain Si and Ge(Si _1-x Ge _x )In general, whether Ge atoms accumulate or diffuse at the interface depends roughly on the relationship between the diffusion length of Ge per unit time and the thickness (consumption rate) at which SiGe is consumed by oxidation. It's okay. If the diffusion length is larger than the consumption rate, Ge diffuses into the SiGe layer and the Ge composition becomes uniform in the depth direction, and if it is reversed, it accumulates at the interface (FIG. 4).
[0048]
FIG. 5 is a diagram showing the relationship between the diffusion length of Ge atoms in Si and the thickness at which SiGe is consumed per unit time due to oxidation. As shown in FIG. 5A, the atmospheric gas is 100% O.₂If it is 950 ° C. or higher, the diffusion length always exceeds the consumption rate.
[0049]
However, looking at the consumption rate immediately after oxidation, the diffusion length is similar to that at 950 ° C. or higher, and Ge accumulates to some extent at the interface immediately after oxidation. There is no problem if the film thickness of the accumulation region is sufficiently thinner than the critical film thickness, but dislocation occurs when the film thickness is about the same or thicker. In order to reduce the risk of the occurrence of dislocation immediately after such oxidation, the consumption rate may be reduced without changing the temperature (that is, without changing the diffusion length). Therefore, it is desirable to use oxygen gas diluted with an inert gas as the atmospheric gas. Since the consumption rate is almost proportional to the partial pressure of oxygen, when oxygen gas diluted to 50% is used, the consumption rate is almost halved, and a sufficiently large margin is obtained for the diffusion length (FIG. 5B). Therefore, it is desirable to use oxygen gas diluted to 50% or less.
[0050]
  Further, according to the first and second manufacturing methods, the Si oxide film becomes viscous fluid, the interface between the SiGe layer and the Si oxide film becomes slippery, and the lattice constant associated with the increase in the Ge composition of the SiGe layer is increased. Increase is not hindered. With these effects, Ge concentration, thinning, and lattice relaxation can be achieved simultaneously without generating dislocations. Further, the surface roughness is reduced.
[0051]
As a result, when a channel layer is further formed on the obtained SiGe layer, a channel layer having a lower dislocation density compared to the conventional method can be obtained, so that carrier mobility can be kept high, and A field effect transistor capable of suppressing leakage current can be provided.
[0052]
【Example】
Example 1
FIG. 6 shows a schematic diagram of the field effect transistor of the first embodiment. In this embodiment, a (001) Si substrate is used as the support base 11, and a buried oxide film as an insulating film 12, a SiGe buffer layer 13 as a first semiconductor layer, and a strain as a second semiconductor layer are formed on the support base. A gate insulating film 17 and a gate electrode 18 are sequentially stacked on a semiconductor substrate 16 in which a channel layer 14 made of Ge and a Si cap layer 15 are stacked. At both ends of the gate region in the SiGe buffer layer 13 and the channel layer 14, a source region and a drain region 19 for obtaining ohmic contact with the source and drain electrodes and a reaction layer 20 with metal are formed.
[0053]
  As the plane orientation of the Si substrate 11 used as the support base 11, not only (001) but also other plane orientations such as (111) substrate and (110) substrate may be used.
[0054]
  The thickness of the channel layer 14 is desirably 3 nm or more. The reason why a thickness of 3 nm or more is necessary is to confine most of the carriers in the channel layer 14. That is, the width in the depth direction of the inversion layer channel formed immediately below the gate insulating film 17 is about 5 nm, and even if the thickness of the Si cap layer 15 is taken into consideration, the thickness of the channel layer 14 needs to be at least 3 nm. Become.
[0055]
In addition, the channel layer 14 has an upper limit depending on the critical film thickness according to the Ge composition of the SiGe buffer layer 13. For example, when the Ge composition is 70 atm%, the upper limit of the channel layer 14 thickness is 5 nm.
[0056]
  The thickness of the SiGe buffer layer 13 can be arbitrarily set in principle. However, when a field effect transistor having a gate length of 100 nm or less is manufactured, the total thickness of the channel layer 14 and the SiGe buffer layer 13 is preferably 35 nm or less in the channel region in order to suppress the short channel effect.
[0057]
  The Ge composition of the SiGe buffer layer 13 is 30 atm% or more. This is because if the Ge composition contained in the SiGe buffer layer 13 is less than 30 atm%, the strain of the channel layer 14 increases and a flat film cannot be obtained with a thickness of 3 nm or more.
[0058]
More desirably, 60 atm% or more is desirable. This is because, when the Ge composition of the SiGe buffer layer 13 is less than 60 atm%, dislocation may occur in the channel layer 4 when the channel layer 14 is stacked by 3 nm or more. This is because the Ge thermodynamic critical film thickness with respect to the Ge composition of the SiGe buffer layer 13 is 3 nm.
[0059]
  A more desirable Ge composition range is 60 atm% or more and 80 atm% or less. This upper limit value of 80 atm% is a set value for enjoying the effect of increasing hole mobility due to strain. That is, when the Ge composition is 80 atm% or less, the phonon scattering mobility of holes in the channel layer 14 becomes more than twice the mobility for unstrained Ge due to the influence of strain applied to the channel layer 14.
[0060]
  The channel layer 14 is a Ge layer, but may be a SiGe layer having a higher Ge composition than the SiGe buffer layer 13. The higher the Ge composition of the channel layer 14, the higher the carrier mobility. Therefore, a channel layer made of a Ge layer is most desirable.
[0061]
  In order to protect the surface of the channel layer 14, an ultrathin Si cap layer 15 is preferably laminated between the channel layer 14 and the gate insulating film 17. The Si cap layer 15 on the channel layer 14 prevents oxidation of the Ge surface in the transistor manufacturing process. Further, the interface with the gate insulating film 17 is prevented from being formed in the channel layer 14, thereby preventing the interface state from increasing. The film thickness of the Si cap layer 15 is preferably 2 nm or less in order not to cause dislocation. This is because when the Ge composition of the SiGe buffer layer 13 is 80 atm%, the thermodynamic critical film thickness of the Si cap layer is 2 nm.
[0062]
Further, the thickness of the Si cap layer 15 is preferably as small as possible, but it is desirable that the thickness of the Si cap layer 15 be 0.5 nm or more in consideration of fluctuations in the film thickness.
[0064]
  As the gate insulating film 17, Zr silicate /ZrO ₂ The laminated film can be used. In FIG. 7, on the Zr silicate layer 21ZrO ₂ Layer 22 is laminated. Here is silicateSiO ₂ It is a substance in which a metal such as Zr, Hf, or La is dissolved.
[0065]
The material of the gate insulating film 17 is a Si oxide film (SiO₂) Si nitride film (Si₃N₄), Si oxynitride film (SiO_xN_y), Al₂O₃, Ta₂O₅TiO₂, Ya₂O₃A high dielectric gate insulating film such as the above can also be used.
[0066]
The film thickness of the source region and drain region 19 must be suppressed to 35 nm or less when the gate length is 100 nm or less. At this time, the parasitic resistance due to the thin source / drain region increases. In order to suppress this, the resistance of the source / drain regions can be kept low by using the compound 20 (silicide, germanide) of Si, Ge and metal (Co, Ti, Ni) to the vicinity of the lower portion of the gate sidewall.
[0067]
As the gate electrode 18, p-type or n-type doped poly-Si or poly-SiGe can be used. It is also possible to use a metal such as W.
[0068]
Next, a method for manufacturing the field effect transistor of this example will be described with reference to FIG.
[0069]
  First, a UHV-CVD method, an MBE method, or an LP-CVD method is performed on an SOI substrate 34 (the thickness of the SOI film 33 is 20 nm) in which a buried oxide film 32 and an SOI film 33 are formed on a Si layer 31 that is a support base. AtSi _0.9 Ge _0.1 Membrane 35The Si layer 36 is epitaxially grown by 5 nm. At this time, dislocation does not occur by making each film thickness less than the critical film thickness at the growth temperature [FIG. 8 (1)]. At this time, instead of the SOI substrate 34, a substrate in which an oxide film is formed on a Si substrate, and a substrate in which an oxide film and a SiGe layer are sequentially formed on the Si substrate may be used.
[0070]
Next, this wafer is put into an oxidation furnace and heated to carry out an oxidation treatment. Si_0.9Ge_0.1SiGe layer containing more Ge than film 35 (Si_0.3Ge_0.7Layer) 37 and Si oxide film 38 are formed. Heating is performed using oxygen gas diluted to 50% with nitrogen at 1000 ° C. for 16 hours until the generated SiGe layer 37 becomes 8 nm. Alternatively, after oxidation at 1000 ° C. and 50% oxygen for 3 hours, switch to 100% oxygen and oxidize for another 8 hours and 20 minutes. Alternatively, after oxidation at 1050 ° C. and 50% oxygen for 1 hour and 23 minutes, the temperature is lowered to 1000 ° C. and oxidation is performed at 100% oxygen for 8 hours and 20 minutes. As a result of the oxidation, the Ge composition of the SiGe layer 37 is concentrated to 70 atm% [FIG. 8 (2)].
[0071]
  Here, care must be taken that the oxidation temperature does not exceed the melting point of the SiGe layer 37. As in this example, in order to obtain the SiGe layer 37 containing Ge with a Ge composition of 70 atm%, the final oxidation temperature must be 1025 ° C. or lower. In order to shorten the oxidation time, it is effective to set a high temperature at first and then gradually or gradually decrease the temperature within a range not exceeding the melting point corresponding to the Ge composition in the SiGe layer 37. is there.
[0072]
Next, after removing the Si oxide film 38 and cleaning the surface, the Si film having a thickness of 5 nm is again formed by the UHV-CVD method, the MBE method, or the LP-CVD method._0.3Ge_0.7A SiGe buffer layer 37 ′ having the composition and a Ge channel layer 39 made of Ge with a thickness of 5 nm are sequentially formed.
[0073]
Subsequently, an amorphous Si layer 40 is deposited as a Si cap layer on the Ge channel layer 39 by 2 nm. In order to deposit amorphous Si, the Si material (Si atom, silane gas, or disilane gas) may be supplied after lowering the substrate temperature to 300 ° C. or lower [FIG. 8 (3)]. By depositing the Si layer 40 in an amorphous state on the Ge channel layer 39, it is possible to prevent the formation of surface irregularities and islands due to lattice mismatch and to obtain a flat surface. The amorphous Si layer is crystallized in a later step. At that time, the surface of the Si layer is covered with an oxide film, so that the flatness of the surface is maintained even when Si is crystallized. Therefore, when a field effect transistor is formed, carrier mobility can be kept high.
[0074]
On the other hand, direct epitaxial growth of Si on the Ge channel layer 39 is not desirable because surface irregularities and islands due to lattice mismatching are formed.
[0075]
Next, a Si oxide film (not shown) of about 0.5 nm is formed on the surface of the amorphous Si layer 40 with a hydrochloric acid / hydrogen peroxide mixture, and then ZrO is used as a gate insulating film.₂A film 41 is deposited by laser ablation or sputtering, and subsequently a poly-SiGe gate electrode 42 is deposited [FIG. 8 (4)]. At this time, since the substrate temperature is 500 ° C. or higher, the amorphous Si layer 40 is crystallized by solid phase growth.
[0076]
Source / drain regions 43 and the like are formed on the wafer thus obtained and processed into transistors in the same manner as in a normal MOSFET process [FIG. 8 (5)].
[0077]
Here, another method for obtaining a structure having the SiGe layer 37 having a high Ge composition shown in FIG. First, a gradient composition Si having a thickness of 1 μm on a Si substrate._1-xGe_xLayer (x = 0 → 0.1), 1.5 μm thick Si_0.9Ge_0.1A Si layer having a thickness of 20 nm is stacked by UHV-CVD, MBE, or LP-CVD.
[0078]
Next, oxygen ions are accelerated by an acceleration voltage of 160 keV and a dose of 4 × 10.¹⁷atoms / cm²The thermal oxide film is formed on the surface at 900 ° C. to a thickness of 10 nm or more. The reason why the Ge composition of the SiGe layer into which oxygen ions are implanted is as low as 10 atm% is to obtain a continuous and uniform buried oxide film. If the Ge composition is 30 atm% or more, a continuous buried oxide film cannot be obtained by this method [Y. Ishikawa et al. , Appl. Phys. Lett. , 75, 983 (1999)].
[0079]
Next, when annealing is performed at 1300 ° C. for 4 hours in an argon gas atmosphere containing a small amount of oxygen (0.5%), a buried oxide film is formed on the 300 nm substrate side from the oxide film-SiGe interface. Ge is excluded from this buried oxide film, and almost pure SiO 2 is removed.₂It becomes. Next, the wafer is etched with a mixed solution of hydrofluoric acid and nitric acid until the SiGe layer reaches 56 nm.
[0080]
Next, when the SiGe layer is oxidized to 8 nm in an oxygen atmosphere, the Ge composition increases to 70 atm%, and the structure of FIG.
(Example 2)
FIG. 9 shows a schematic diagram of the field effect transistor of the second embodiment. In the present embodiment, in order to suppress an increase in parasitic resistance due to the thin film thickness of the source / drain region, the surface of the source / drain region 19 in the transistor shown in FIG. It is covered with a thin film 50 of Al or W.
(Example 3)
FIG. 10 shows a schematic diagram of the field effect transistor of the third embodiment. In this embodiment, in order to suppress the parasitic resistance, Si in the transistor shown in FIG._0.3Ge_0.7A layer 51 is deposited to increase the source / drain region thickness to 100 nm. In order to produce this structure, once the entire surface is SiO.₂After depositing the mask, only the upper surface of the source / drain region may be exposed, and the SiGe layer may be deposited by selective CVD.
Example 4
FIG. 11 shows a schematic diagram of the field effect transistor of the fourth embodiment. In this embodiment, the SiGe buffer layer 13 has a two-layer structure in the transistor shown in FIG. A second buffer layer 53 having a Ge composition of 75 atm% and a thickness of 10 nm is stacked on the first buffer layer 52 having a Ge composition of 55 atm% and a thickness of 5 nm formed by oxidation. According to the present embodiment, the strain applied to the Ge channel is increased by the presence of the second buffer layer as compared with the case of only the first buffer layer. Therefore, compared with the first embodiment, the Ge composition of the first buffer layer can be kept low, so that the margin for film thickness control during oxidation is increased and the yield is improved.
[0081]
As a modification of this embodiment, a structure in which the Ge composition of the second buffer layer increases continuously or stepwise as it approaches the surface is also possible.
(Example 5)
FIG. 12 shows an example in which the field effect transistor shown in the first embodiment shown in FIG. 6 is applied to a CMOS inverter. The p-channel and n-channel MOSFETs are insulated by a trench that reaches the buried oxide film. The substrate 11 is biased to function as a back gate for adjusting the threshold value.
[0082]
【The invention's effect】
As described above, according to the semiconductor device and the semiconductor substrate of the present invention, it is possible to obtain a MISFET capable of operating at high speed with lower power consumption than Si-MOSFET. Also, using these MISFETs, an integrated circuit capable of high-speed operation with lower power consumption than before can be obtained.
[Brief description of the drawings]
FIG. 1 is a schematic view showing an embodiment of a field effect transistor according to the present invention.
FIG. 2 is an enlarged view of a pn junction portion of a source region or a drain region portion in the field effect transistor according to the first conventional technique and this embodiment.
FIG. 3 is a diagram showing a band structure in the vicinity of a channel layer of a field effect transistor according to the present embodiment and the second conventional technique.
FIG. 4 is a view for explaining a Ge composition distribution during oxidation of a semiconductor layer containing Si and Ge in a method for manufacturing a semiconductor substrate.
FIG. 5 is a diagram showing the relationship between the diffusion length of Ge atoms in Si and the thickness at which SiGe is consumed per unit time due to oxidation.
FIG. 6 is a schematic view of a field effect transistor according to the first embodiment.
FIG. 7 is a schematic diagram illustrating an example of a gate insulating film.
FIG. 8 is a process diagram showing a method of manufacturing the field effect transistor according to the first embodiment.
FIG. 9 is a schematic view of a field effect transistor according to a second embodiment.
FIG. 10 is a schematic view of a field effect transistor according to a third embodiment.
FIG. 11 is a schematic view of a field effect transistor according to a fourth embodiment.
FIG. 12 is a schematic view showing an example in which the field effect transistor shown in the first embodiment is applied to a CMOS inverter.
FIG. 13 is a schematic view showing a field effect transistor structure of a first conventional example.
FIG. 14 is a schematic view showing a field effect transistor structure of a second conventional example.
FIG. 15 is a characteristic diagram showing a relationship between current (log (Id) −voltage (Vg)) of a transistor of the second conventional example and a Si-MOSFET.
FIG. 16 is a characteristic diagram showing a relationship of (Vg (gate voltage) −Vth (threshold voltage)) − current between the transistor of the second conventional example and the Si-MOSFET.
[Explanation of symbols]
1 ... Support base
2 ... Insulating film
3 ... SiGe buffer layer (first semiconductor layer)
4 ... Channel layer (second semiconductor layer)
5 ... Board
6 ... Source region, drain region
7 ... Gate insulation film
8 ... Gate electrode
11 ... Support base
12 ... Insulating film
13: First semiconductor layer (SiGe buffer layer)
14 ... Second semiconductor layer (channel layer made of strained Ge)
15 ... Si cap layer
16 ... Semiconductor substrate
17 ... Gate insulating film
18 ... Gate electrode
19 ... Source region and drain region
20 ... Reaction layer with metal
31 ... Si layer
32 ... buried oxide film
33 ... SOI film
34 ... SOI substrate
35 ...Si _0.9 Ge _0.1 film
36 ... Si layer
37 ... SiGe layer with high Ge composition(Si _0.3 Ge _0.7 layer)
37 '... SiGe buffer layer
38 ... Si oxide film
39... Ge channel layer
40: Amorphous Si layer
41 ... Gate insulating film
42 ... Gate electrode

Claims (10)

A support substrate;
An insulating film formed on the support substrate;
A semiconductor layer formed on the insulating film and having a source region and a drain region formed thereon;
A gate insulating film formed on the semiconductor layer;
In a semiconductor device comprising a field effect transistor comprising a gate electrode formed on the gate insulating film,
The semiconductor layer includes a SiGe region having a Ge composition of 30 atm% or more provided on a side in contact with the insulating film and a SiGe or Ge having a Ge composition higher than that of the SiGe region provided on a surface opposite to the insulating film. And a Si layer having a thickness of 2 nm or less existing between the SiGe or Ge channel region and the gate insulating film . 2. The semiconductor device according to claim 1, wherein the dislocation density of the SiGe region having the Ge composition of 30 atm% or more is 10 ^{< 6} > cm ^<-2 > or less.   2. The semiconductor device according to claim 1, wherein the Ge composition in the depth direction distribution of the SiGe region having a Ge composition of 30 atm% or more is substantially uniform. An insulating film, a first semiconductor layer including a SiGe layer having a Ge composition of 30 atm% or more, and a second semiconductor layer including a SiGe layer or a Ge layer having a higher Ge composition than the first semiconductor layer are provided on a supporting substrate. sequentially laminated by comprising substrate, a gate insulating film are sequentially laminated gate electrode, and the result is formed a source region and a drain region in the first and second semiconductor layer, and said second semiconductor layer the semiconductor device according to claim and between the gate insulating film, further comprising a field-effect transistor you includes a Si layer below 2nm thick. 5. The semiconductor device according to claim 4, wherein the dislocation density of the first semiconductor layer is 10 ⁶ cm ⁻² or less. The semiconductor device according to claim 4 , wherein a depth direction distribution of a Ge composition of the first semiconductor layer is substantially uniform. On a supporting substrate, an insulating film, a first semiconductor layer Ge composition is 30 atm% or more of the SiGe layer, the first second semiconductor layer is higher SiGe layer or Ge layer of Ge composition than the semiconductor layer, wherein A semiconductor substrate, wherein a Si layer having a thickness of 2 nm or less existing on the second semiconductor layer is sequentially laminated. The semiconductor substrate according to claim 7, wherein the dislocation density of the first semiconductor layer is 10 ⁶ cm ⁻² or less. The semiconductor device according to claim 7 , wherein a Ge direction depth distribution of the first semiconductor layer is substantially uniform. 8. The semiconductor substrate according to claim 7 , wherein a gate insulating film and a gate electrode are further sequentially stacked on the Si layer.

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