JP4282579B2 - Semiconductor substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device necessary for obtaining a semiconductor device including a field effect transistor having a high-speed and low power consumption, in particular, a field effect transistor having strained Ge or strained SiGe as a channel layer. About.

Ge hole and electron mobility subjected to compressive strain in a plane parallel to the substrate may exceed Si hole and electron mobility in both p and n channels by selecting an appropriate plane orientation. Are known.

FIG. 13 shows one of conventional transistor structures using this strained Ge as a channel (first conventional example) (see Patent Document 1) . In this structure, p-Si is formed on an n-type Si substrate 61.
_0.5 Ge _0.5 buffer layer 62, i-Si _0.5 Ge _0.5 Ge spacer layer 63, i-
Ge channel layer 64, i-Si _0.5 Ge _0.5 Ge spacer layer 65, p-Si _0.5 G
e _0.5 layer 66, i-Si _1-x Ge _x layer (x = 0.5 → 0) (SiGe cap layer) 6
7. A Ti Schottky gate electrode 68 is stacked. The source / drain region 6
9 is formed at both ends immediately below the gate electrode 68.

This structure is a so-called modulation doped FET (MODFET), i-Ge channel layer 6
P-Si _0.5 Ge _0.5 buffer layer 62, i-Si ₀ , which is a doping layer away from 4
_{. Since} carriers are supplied from the ₅ Ge _0.5 Ge spacer layer 65 to the channel layer 64 , the hole mobility does not decrease due to scattering by the doped impurities. Therefore, it is said that high speed operation utilizing the high mobility of positive holes of strained Ge is possible. Non-patent document 1 discloses a structure similar to this structure.

As another conventional technique, a transistor using strained Si subjected to in-plane tensile strain as a channel is also known. The carrier mobility of strained Si is also known to exceed that of Si in both p and n channels, as in the case of strained Ge. Therefore, these transistors are larger at the same gate size than Si channel transistors. Driving force can be obtained. Among them, a transistor structure considered to be most practical is shown in FIG. 14 (second conventional example). This structure is a structure proposed and verified by a research group including the present inventors (see Non-Patent Document 2).

In this structure, the buried oxide film 72 and the SiGe buffer layer 7 are formed on the Si or SiGe layer 71.
3, a strained Si channel layer 74, a gate oxide film 75, and a gate electrode 76 are sequentially stacked to form S
Source / drain regions 77 are formed in the iGe buffer layer 73 and the strained Si channel layer 74.

In this structure, in addition to the high carrier mobility due to the strained Si channel 74, the existence of the buried oxide film 72 reduces the parasitic capacitance, and the miniaturization can be performed while keeping the impurity concentration low, so that the driving force can be increased. It has both advantages. Therefore, if a CMOS logic circuit is configured with this structure, it is possible to operate at higher speed and with lower power consumption.

Further, as a method of manufacturing a semiconductor substrate having a SiGe layer having a high Ge composition on an oxide film like the SiGe buffer layer 73 on the oxide film as shown in FIG. 14, (1) a thin film SOI (Silicon
on Insulator) (see Non-Patent Document 3),
2) A method in which an oxide film formed on a Si substrate and a laminated structure of SiGe epitaxially grown on the Si substrate face each other and a part of the SiGe laminated structure is removed later (Patent Document 2)
3), and (3) a method of manufacturing a SiGe crystal on an oxide film by oxygen ion implantation and annealing (SIMOX method) used in the process of creating the second conventional example has been proposed.
Japanese Patent Laid-Open No. 2-196436 E. Murakami et al., IEEE Transaction on Electron Devices, Vol. 41, p.857 (1994), and YH Xie et al., Applied Physics Letters Vol. 63, p. 2263 (1994) T. Mizuno, S. Takagi, N. Sugiyama, J. Koga, T. Tezuka, K. Usuda, T. Hatakeyama, A. Kurobe, and A. Toriumi, IEDM Technical Digests p.934 (1999) AR Powell et al., Appl. Phys. Lett. 64, 1856 (1994) Japanese Patent No. 3037934 Japanese Patent No. 2908787

First, the problem that arises when the first conventional example is put to practical use is that the source / drain junction leakage is large. In the structure of the first conventional example, the thickness of the SiGe buffer layer 62 is a considerably large value of 500 nm, but in other similar conventional examples, the thickness is several hundred nm to about 1 μm or more. . This is the SiGe buffer layer 6
2 is a thickness necessary for sufficiently reducing the dislocation density of 2 and thus reducing the dislocation density reaching the channel layer 64. At this time, the lower portion of the source / drain diffusion region 69 and the SiGe buffer layer 6
2 is connected to the p ⁺ -n junction surface (in the case of p channel) or the n ⁺ -p junction surface (n channel).
In the case of a le) .

Here, since the Ge composition of the SiGe buffer layer 62 is as high as about 50 atm% or more, the band gap value is about 75-60% of the Si band gap value. The reverse bias saturation current of the pn junction is expressed as the sum of the diffusion current and the recombination current. Each component is proportional to the square of the intrinsic carrier density. The intrinsic carrier density increases as the band gap energy decreases. For example, the intrinsic carrier density of Ge is a value that is 1000 times or more that of Si. Therefore, there arises a problem that the junction leakage or off-current between the source / drain region 69 and the SiGe buffer layer 62 in the first conventional example is 2 to 4 digits larger than Si. Considering the leakage current through dislocations in the SiGe buffer layer 62, the off current is further increased. This causes a problem of a significant increase in power consumption when a large-scale circuit is formed. In order to reduce this leakage, SiGe with a low Ge composition
When the buffer layer 62 is used, the lattice constant difference from the Ge channel layer 64 is increased.
Dislocation occurs in the channel, or the surface becomes uneven to release the strain. Therefore, in the first conventional example, a thick SiGe buffer layer 62 having a Ge composition of 50 atm% or more must be used. Therefore, leakage between the source and drain or between the drain and substrate is smaller than that of a Si-based transistor. It is unavoidable that it becomes several orders of magnitude larger.

Next, problems of the second conventional example will be described. FIG. 3B shows a band structure in the vicinity of the channel of the second conventional example. As can be seen from FIG. 3B, the strained Si channel layer 7
Since the energy of the valence band of 4 is lower than the energy of the valence band edge of the SiGe buffer layer 73, if a negative bias is applied to the gate to form the hole channel, the strain is strained before the surface channel is formed. A buried channel is formed at the interface between the Si channel layer 74 and the SiGe buffer layer 73.

FIG. 15 shows the current (log (Id) − of the second conventional transistor and the Si-MOSFET.
A voltage (Vg) curve is shown. Due to the presence of the aforementioned buried channel, as shown in FIG.
The characteristic near the threshold voltage is deteriorated (S factor is increased). The influence of the buried channel becomes more prominent as the strained Si channel layer 74 becomes thinner. In other words, the effect increases as the size is reduced. Therefore, it is difficult to set the threshold voltage low when a fine MOSFET is manufactured.

FIG. 16 shows (Vg (gate voltage) -Vth (threshold voltage))-current characteristics of the transistor of the second conventional example and the Si-MOSFET. The mobility of this buried channel is SiG
The mobility is low due to the influence of alloy scattering in the e-buffer layer. Therefore, as shown in FIG. 16, in the second conventional example, the driving power is low at a low gate voltage as compared with the driving power of a normal surface channel Si-MOSFET. For the above reasons, it is difficult to reduce power consumption in the second conventional example.

An object of the present invention is to provide a field effect transistor which has a small leakage current between a source and a drain or between a drain and a substrate and can reduce power consumption.

Another object of the present invention is to provide a semiconductor substrate from which the field effect transistor can be easily obtained.

As for the method of manufacturing the SiGe layer on the oxide film, first, the method (1) requires a base SOI, so that the thickness of the semiconductor layer on the oxide film increases accordingly, and an FET is manufactured. This hinders the shortening of the channel. Further, when SiGe is epitaxially grown on the SOI and annealed for relaxation, dislocation occurs in the SOI layer.

In the method (2), a SiGe buffer layer having a thickness of several μm is grown on a Si substrate, and a SiGe thin film having a desired composition is formed thereon. In this case, undulation of the surface having a period of about 1 μm, which is inevitably called a cross hatch, occurs. Furthermore, it is difficult to completely remove the dislocations remaining in the buffer layer, and there is a problem that dislocations occur at a density of about 10 ⁶ cm ⁻² near the surface. As the Ge composition increases, the dislocation density tends to increase.

In (3), when the Ge composition is increased, Ge is combined with oxygen during evaporation to evaporate, and a continuous buried oxide film is not formed or the surface becomes rough.

The present invention suppresses the increase in the thickness of the laminated structure on the oxide film, the occurrence of dislocations, or the surface roughness even when the Ge composition is increased (30 atm% or more) in manufacturing the SiGe layer on the oxide film. It is an object of the present invention to provide a method of manufacturing a semiconductor substrate that can be manufactured.

The first method of a semiconductor substrate of manufacture of the present invention, on the SOI substrate, and epitaxially growing a first 1SiGe layer, by performing an oxidation treatment, so as to generate an Si oxide film on the surface of the 1SiGe layer, Si oxide A step of diffusing Ge from the film to the first SiGe layer to form a second SiGe layer having a higher Ge composition, a step of peeling the Si oxide film, and a CVD method or an MBE method on the second SiGe layer, and performing the step of laminating the first 3 SiGe layer higher Ge composition than the first 2SiGe layer.

The second method for manufacturing a semiconductor substrate according to the present invention includes a step of epitaxially growing a first SiGe layer on an SOI substrate, a step of epitaxially growing a Si layer on the first SiGe layer, and an oxidation treatment to thereby form an Si layer. And forming a Si oxide film on the surface of the first SiGe layer stack, diffusing Ge from the Si oxide film to the first SiGe layer to form a second SiGe layer having a higher Ge composition, and peeling the Si oxide film using the method, a CVD method or a MBE method, on the 2SiGe layer, and performing the step of laminating the the higher Ge composition than the 2SiGe layer first 3SiGe layer and the Ge layer sequentially.

The present invention also includes a step of sequentially stacking a gate insulating film and a gate electrode film on a semiconductor substrate obtained by the first method for manufacturing a semiconductor substrate, and a gate insulating film and a gate electrode film on the gate insulating film and the gate electrode film. A step of performing gate electrode processing and forming source / drain regions is performed to form a field effect transistor in which a channel is formed in a third SiGe layer of a semiconductor substrate .

The present invention also includes a step of sequentially laminating a gate insulating film and a gate electrode film on a semiconductor substrate obtained by the semiconductor substrate manufacturing method obtained by the second semiconductor substrate manufacturing method, And a step of forming a gate insulating film and a gate electrode and forming a source / drain region on the gate electrode film to form a field effect transistor having a channel formed in a Ge layer of a semiconductor substrate .

According to the semiconductor device and the semiconductor substrate obtained by the present invention, it is possible to obtain a MISFET capable of operating at high speed with lower power consumption than Si-MOSFET. Also, these MISFE
Using T, an integrated circuit capable of high-speed operation with lower power consumption than in the past can be obtained.

According to the semiconductor substrate manufacturing method of the present invention, a SiGe layer having a low dislocation density and a lattice relaxation is formed.

An embodiment of a field effect transistor obtained by applying the method for manufacturing a semiconductor device of the present invention includes a supporting base, an insulating film formed on the supporting base, a source region formed on the insulating film, and A field effect transistor comprising a semiconductor layer in which a drain region is formed, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film, wherein the semiconductor layer includes: The Ge composition provided on the side in contact with the insulating film is 30 atm%
The SiGe region described above and a SiGe or Ge channel region having a higher Ge composition than the SiGe region provided on the surface opposite to the insulating film are provided.

SiGe having a Ge composition of 30 atm% or more is a compound represented by Si _1-x Ge _x (1> x ≧ 0.3) .

A schematic diagram showing an example of a field effect transistor is shown in FIG. An insulating film 2 is formed on the support base 1, and a semiconductor layer is formed on the insulating film 2. The insulating film 2 electrically insulates the support base 1 and the semiconductor layer, and examples thereof include a Si oxide film. The semiconductor layer includes a SiGe buffer layer 3 (first semiconductor layer) having a high Ge composition with a Ge composition of 30 atm% or more, and a channel layer 4 (SiGe layer or Ge layer having a Ge composition higher than that of the first semiconductor layer). A layer formed by laminating a second semiconductor layer) can be given. The substrate 5 is the support base 1
The insulating film 2, the first semiconductor layer, and the second semiconductor layer are stacked. Source / drain regions 6 are formed on the substrate 5 and connected to a source electrode (not shown) and a drain electrode (not shown), respectively. Further, the gate insulating film 7 and the gate electrode 8 are laminated to constitute a field effect transistor.

That is, in the field effect transistor, a SiGe buffer layer 3 having a high Ge composition and a channel layer 4 made of a Ge layer or a SiGe layer are stacked on an insulating film 2. As a result, the leakage current between the source and drain, which has been a problem in the past, can be suppressed to a practical level. Further, an integrated circuit capable of low power consumption and high speed operation utilizing the high mobility of the Ge or SiGe channel can be obtained.

  This will be described in more detail below.

In the channel layer 4 formed on the SiGe buffer layer 3, strain is introduced into the crystal structure due to the difference in lattice constant between the SiGe buffer layer 3 and the channel layer 4. Thereby, the hole and electron mobility in the channel layer 4 greatly exceeds the hole and electron mobility of Si, and the device speed can be increased. In the channel layer 4, no strain may be introduced, and even in that case, the mobility of electrons and holes is sufficiently higher than that of Si. However, the mobility of electrons and holes is higher when strain is introduced.

FIG. 2 shows an enlarged view of the pn junction portion of the source region or the drain region in the field effect transistor according to the first prior art and this embodiment. FIG. 2A is an enlarged view of the pn junction portion of the source region or drain region of the field effect transistor according to the first conventional example shown in FIG. FIG. 2B is an enlarged view of the pn junction portion of the source region or drain region in the substrate of the field effect transistor according to the present embodiment shown in FIG. In the field effect transistor of the present invention shown in FIG. 2B, source / drain regions 6 are formed in the SiGe buffer layer 3 and the channel layer 4 formed on the insulating film 2. Due to the presence of the insulating film 2, the leakage current to the support substrate is completely suppressed. Further, the area of the pn junction surface is greatly reduced, and a gate voltage is applied, whereby the channel layer 4 and the SiGe buffer layer 3
Since both are depleted, the leakage current between the source and the drain is significantly reduced as compared with the first conventional example.

In contrast, in the first conventional field effect transistor substrate shown in FIG. 2A, an i-Ge channel layer 64 and a SiGe cap layer 67 are stacked on a thick (> 500 nm) buffer layer 62. Yes. A source or drain region 69 is also formed. In FIG. 2A, since the insulating film 2 as shown in FIG. 2B does not exist, leakage to the support base occurs. Further, since the area of the pn junction is large and the transition remaining in the buffer layer 62, the leakage current between the source and the drain is remarkably larger than that in the present embodiment.

FIG. 3A shows a band structure in the vicinity of the channel layer of the field effect transistor according to the present embodiment. 3A, the energy of the valence band of the channel layer 4 is higher than the energy of the valence band edge of the SiGe buffer layer (Si _0.3 Ge _0.7 ) 3. Therefore, when a negative bias is applied to the gate electrode to form a hole channel, only the surface channel is formed. Accordingly, since there is no buried channel as in the second conventional example, the characteristics near the threshold voltage are not deteriorated, and the threshold voltage can be set low. Further, the driving force at a low gate voltage can be increased. For the above reasons, low power consumption can be realized in the present invention.

In the conventional Si-MOSFET, an SOI substrate having a similar structure is used, but this is mainly aimed at speeding up by reducing the parasitic capacitance between the substrate and the wiring and the junction capacitance of the region. . The role of the insulating film 2 in this embodiment is to suppress the off-current for the SiGe or Ge channel layer, which is practically essential, whereas the conventional Si-MO
For the SFET only an additional function is provided.

In the field effect transistor of the present embodiment, it is desirable that the dislocation density of the SiGe buffer layer 3 (first semiconductor layer) is 10 ⁶ cm ⁻² or less. Element or L
The yield of SI can be made a practical level. The dislocation density is more preferably 10 ^4.
cm ⁻² or less.

In addition, if the Ge composition depth direction distribution of the SiGe buffer layer 3 (first semiconductor layer) is substantially uniform, no distortion is accumulated in the SiGe buffer layer 3, and therefore, a transition is unlikely to occur. Therefore, in order to reduce the dislocation density, it is desirable that the Ge composition depth direction distribution of the SiGe buffer layer 3 (first semiconductor layer) is substantially uniform.

In the field effect transistor of this embodiment, it is desirable that a Si cap layer is provided between the channel layer 4 (second semiconductor layer) and the gate insulating film 7. This prevents oxidation of the SiGe or Ge surface in the field effect transistor manufacturing process. Furthermore, it is possible to prevent the interface with the gate insulating film 7 from being formed in SiGe or Ge, thereby preventing an increase in interface state. Furthermore, when the film thickness of the Si cap layer is not more than the critical film thickness with respect to the SiGe buffer layer 3 (the minimum thickness at which dislocation occurs due to mismatch of lattice constant), dislocation does not occur. Due to these effects, the carrier mobility can be kept high.

The semiconductor substrate of the present embodiment is a semiconductor substrate that is used for manufacturing the field effect transistor according to the present embodiment and has two layers having a high Ge composition corresponding to the SiGe buffer layer 3 and the channel layer 4. Yes, if a field effect transistor is manufactured using the semiconductor substrate of this embodiment, the leakage current between the source and drain or between the drain and substrate is small.
In addition, a field effect transistor capable of high-speed operation and low power consumption can be provided.

In the semiconductor substrate of this embodiment, the dislocation density of the SiGe buffer layer 3 (first semiconductor layer) is desirably 10 ⁶ cm ⁻² or less. Semiconductor device or LSI
Yield can be brought to a practical level. The dislocation density is more preferably 10 ⁴ cm.
^-2 or less.

In the semiconductor substrate of the present embodiment, the Ge of the SiGe buffer layer 3 (first semiconductor layer).
It is desirable that the depth distribution of the composition is substantially uniform.

For example, for the field effect transistor according to the present embodiment, a semiconductor substrate on which a SiGe layer having a high Ge composition (30 atm% or more) is formed as a SiGe buffer layer is required. First and second used for manufacturing a semiconductor substrate having the SiGe layer of the high Ge composition
In this semiconductor substrate manufacturing method, a semiconductor including a Si and Ge layer having a low Ge composition directly on an insulating film formed on a support base or on a Si layer or SiGe layer formed on the insulating film. A layer is formed and subjected to an oxidation treatment, specifically, a heat treatment in an oxidizing atmosphere to produce a SiGe layer having a high Ge composition in which Ge is concentrated simultaneously with the formation of a Si oxide film.

That is, by applying an oxidation treatment to a semiconductor layer including a Si and Ge layer having a low Ge composition, a low G
Si atoms are selectively oxidized from the surface of the semiconductor layer including the Si and Ge layers of e composition to form a Si oxide film, and Ge atoms are discharged from the formed Si oxide film. Accumulated in a semiconductor layer containing Si and Ge. This is because the bond between the SiO ₂ SiO
This is because oxygen atoms are preferentially bonded to Si atoms because they are chemically stable as compared with Ge—O bonds of GeO ₂ or GeO. Therefore, Ge is concentrated to have a high Ge composition SiGe
A layer and a Si oxide film are formed.

What is necessary is just to remove the Si oxide film produced | generated at this time as needed. Further, a step of forming a channel layer or the like is performed as necessary.

According to the first and second manufacturing methods of the present invention, a semiconductor layer containing Si and Ge is obtained by subjecting a semiconductor layer containing Si and Ge to an oxidation treatment, specifically, a heat treatment in an oxidizing atmosphere. The Ge concentration in the generated SiGe layer becomes uniform due to sufficient diffusion. If this layer is used as a SiGe buffer layer in the field effect transistor according to the present embodiment, for example, Ge
No distortion occurs in the SiGe buffer layer due to non-uniform composition. As a result, the dislocation density can be suppressed to 10 ⁶ cm ⁻² or less after sufficient lattice relaxation.

This will be described with reference to FIGS. FIG. 4 is a view for explaining the Ge composition distribution during oxidation of the semiconductor layer containing Si and Ge in the method of manufacturing a semiconductor substrate according to the present invention. In general, whether a Ge atom accumulates or diffuses at an interface in a semiconductor layer ( Si _1-x Ge _x ) containing Si and Ge depends on the diffusion length of Ge per unit time and oxidation. SiGe
It can be considered that it depends on the size of consumption (consumption rate). If the diffusion length is larger than the consumption rate, Ge diffuses into the SiGe layer and the Ge composition becomes uniform in the depth direction, and if it is reversed, it accumulates at the interface (FIG. 4).

FIG. 5 is a diagram showing the relationship between the diffusion length of Ge atoms in Si and the thickness at which SiGe is consumed per unit time due to oxidation. As can be seen from FIG. 5A, when the atmospheric gas is 100% O ₂ , the diffusion length always exceeds the consumption rate at 950 ° C. or higher.

However, looking at the consumption rate immediately after oxidation, the diffusion length is similar to that at 950 ° C. or higher, and Ge accumulates to some extent at the interface immediately after oxidation. There is no problem if the film thickness of the accumulation region is sufficiently smaller than the critical film thickness, but dislocation occurs when the film thickness is about the same or thicker. In order to reduce the risk of occurrence of dislocation immediately after such oxidation, the consumption rate may be reduced without changing the temperature (that is, without changing the diffusion length). Therefore, it is desirable to use oxygen gas diluted with an inert gas as the atmospheric gas. Since the consumption rate is almost proportional to the oxygen partial pressure, when oxygen gas diluted to 50% is used, the consumption rate is almost halved, and a sufficiently large margin is obtained for the diffusion length (FIG. 5B). Therefore, it is desirable to use oxygen gas diluted to 50% or less.

Further, according to the first and second manufacturing methods of the present invention, the Si oxide film becomes viscous fluid, and S
The interface between the iGe layer and the Si oxide film becomes slippery, and the increase in the lattice constant accompanying the increase in the Ge composition of the SiGe layer is not hindered. With these effects, Ge concentration, thinning, and lattice relaxation can be achieved simultaneously without generating dislocations. Further, the surface roughness is reduced.

As a result, when a channel layer is further formed on the obtained SiGe layer, a channel layer having a lower dislocation density compared to the conventional method can be obtained, so that carrier mobility can be kept high, and A field effect transistor capable of suppressing leakage current can be provided.

Example 1
FIG. 6 shows a schematic diagram of the field effect transistor of the first embodiment. In this embodiment, a (001) Si substrate is used as the support base 11, and a buried oxide film as an insulating film 12, a SiGe buffer layer 13 as a first semiconductor layer, and a strain as a second semiconductor layer are formed on the support base. A gate insulating film 17 and a gate electrode 18 are sequentially stacked on a semiconductor substrate 16 in which a channel layer 14 made of Ge and a Si cap layer 15 are stacked. SiGe buffer layer 13 and channel layer 1
4, a source region and a drain region 19 for obtaining an ohmic contact with the source and drain electrodes and a metal reaction layer 20 are formed at both ends of the gate region.

In the field effect transistor according to this example, the plane orientation of the Si substrate 11 used as the support base 11 is not limited to (001), but other plane orientations, for example, a (111) substrate,
(110) A substrate may be used.

In the field effect transistor according to this embodiment, it is desirable that the channel layer 14 has a thickness of 3 nm or more. The reason why a thickness of 3 nm or more is necessary is to confine most of the carriers in the channel layer 14. That is, the width in the depth direction of the inversion layer channel formed immediately below the gate insulating film 17 is about 5 nm, and even if the thickness of the Si cap layer 15 is taken into consideration, the thickness of the channel layer 14 needs to be at least 3 nm. Become.

In addition, the channel layer 14 has an upper limit depending on the critical film thickness according to the Ge composition of the SiGe buffer layer 13. For example, when the Ge composition is 70 atm%, the upper limit of the channel layer 14 thickness is 5 nm.

In the field effect transistor according to the present invention, the thickness of the SiGe buffer layer 13 can be arbitrarily set in principle. However, when a field effect transistor having a gate length of 100 nm or less is manufactured, the channel layer 14 and the SiGe buffer layer 13 are used to suppress the short channel effect.
The total film thickness is preferably 35 nm or less in the channel region.

In the field effect transistor of this example, the Ge composition of the SiGe buffer layer 13 is 30 atm.
% Or more. This is because if the Ge composition contained in the SiGe buffer layer 13 is less than 30 atm%, the strain of the channel layer 14 increases and a flat film cannot be obtained with a thickness of 3 nm or more.

More desirably, 60 atm% or more is desirable. This is because, when the Ge composition of the SiGe buffer layer 13 is less than 60 atm%, dislocation may occur in the channel layer 4 when the channel layer 14 is stacked by 3 nm or more. This is because the Ge composition of the SiGe buffer layer 13 is 60 at.
This is because the thermodynamic critical film thickness of Ge with respect to m% is 3 nm.

A more desirable Ge composition range is 60 atm% or more and 80 atm% or less. This upper limit value of 80 atm% is a set value for enjoying the effect of increasing hole mobility due to strain. That is, when the Ge composition is 80 atm% or less, the phonon scattering mobility of holes becomes more than twice that of unstrained Ge due to the strain applied to the channel layer 14.

In the field effect transistor of this embodiment, the channel layer 14 is a Ge layer, but may be a SiGe layer having a higher Ge composition than the SiGe buffer layer 13 instead of Ge. The higher the Ge composition of the channel layer 14, the higher the carrier mobility. Therefore, a channel layer made of a Ge layer is most desirable.

In the field effect transistor according to this example, it is desirable that an extremely thin Si cap layer 15 is laminated between the channel layer 14 and the gate insulating film 17 in order to protect the surface of the channel layer 14. The Si cap layer 15 on the channel layer 14 prevents oxidation of the Ge surface in the transistor manufacturing process. Further, the interface with the gate insulating film 17 is the channel layer 14.
It is prevented from being formed inside, thereby preventing an increase in interface state. The film thickness of the Si cap layer 15 is preferably 2 nm or less in order not to cause dislocation. This is because when the Ge composition of the SiGe buffer layer 13 is 80 atm%, the thermodynamic critical film thickness of the Si cap layer is 2 nm.
Because.

Further, the thickness of the Si cap layer 15 is preferably as small as possible, but it is desirable that the thickness of the Si cap layer 15 be 0.5 nm or more in consideration of fluctuations in the film thickness.

A structure without the Si cap layer 15 is also possible. In this case, a Ge nitride film can be used as the gate insulating film 17 in addition to the material described later. This Ge nitride film can be obtained by nitriding the Ge surface directly using ammonia gas or nitrogen gas, in addition to deposition by CVD.

In the field effect transistor according to this embodiment, as the gate insulating film 17, a Zr silicate / ZrO ₂ laminated film as shown in FIG. 7 can be used. In FIG. 7, a ZrO ₂ layer 22 is laminated on the Zr silicate layer 21. Here, silicate means Zr in SiO _2.
, Hf, La and other metals in solid solution.

The material of the gate insulating film 17 is not only the Si oxide film (SiO ₂ ) but also the Si nitride film (Si ₃ N ₄ ) , Si oxynitride film (SiO _x N _y ) , Al ₂ O ₃ , Ta ₂ O _5. TiO ₂
A high dielectric gate insulating film such as Ya ₂ O ₃ can also be used.

The film thickness of the source region and drain region 19 must be suppressed to 35 nm or less when the gate length is 100 nm or less. At this time, the parasitic resistance due to the thin source / drain region increases. In order to suppress this, the resistance of the source / drain regions can be kept low by using the compound 20 (silicide, germanide) of Si, Ge and metal (Co, Ti, Ni) to the vicinity of the lower portion of the gate sidewall.

As the gate electrode 18, p-type or n-type doped poly-Si or poly-Si
Ge can be used. It is also possible to use a metal such as W.

  Next, a method for manufacturing the field effect transistor of this example will be described with reference to FIG.

First, a UHV-CVD method or MB is performed on an SOI substrate 34 (the thickness of the SOI film 33 is 20 nm) in which the buried oxide film 32 and the SOI film 33 are formed on the Si layer 31 which is a support base.
The Si _0.9 Ge _0.1 film 35 is 56 nm and the Si layer 36 is 5 by the E method or the LP-CVD method.
nm epitaxial growth. At this time, dislocation does not occur by making each film thickness less than the critical film thickness at the growth temperature [FIG. 8 (1)]. At this time, instead of the SOI substrate 34, a substrate in which an oxide film is formed on a Si substrate, and a substrate in which an oxide film and a SiGe layer are sequentially formed on the Si substrate may be used.

Next, this wafer is put into an oxidation furnace and heated to carry out an oxidation treatment. Thereby, Si _0
. SiGe layer containing more Ge than the ₉ Ge _0.1 film 35 ( Si _0.3 Ge _0.7 layer )
37 and a Si oxide film 38 are formed. Heating is performed using oxygen gas diluted to 50% with nitrogen.
Oxidation is performed at 000 ° C. for 16 hours until the generated SiGe layer 37 reaches 8 nm. Alternatively, after oxidation at 1000 ° C. and 50% oxygen for 3 hours, switch to 100% oxygen for another 8 hours and 20 hours.
Oxidize. Alternatively, after oxidation for 1 hour and 23 minutes at 1050 ° C. and 50% oxygen, the temperature is 1000
Reduce to 0 ° C. and oxidize with 100% oxygen for 8 hours and 20 minutes. As a result of the oxidation, the Ge composition of the SiGe layer 37 is concentrated to 70 atm% [FIG. 8 (2)].

Here, care must be taken that the oxidation temperature does not exceed the melting point of the SiGe layer 37.
As in this example, in order to obtain the SiGe layer 37 containing Ge with a Ge composition of 70 atm%, the final oxidation temperature must be 1025 ° C. or lower. In order to shorten the oxidation time, it is effective to set a high temperature at first and then gradually or gradually decrease the temperature within a range not exceeding the melting point corresponding to the Ge composition in the SiGe layer 37. is there.

Next, after removing the Si oxide film 38 and cleaning the surface, the SiGe buffer layer 37 having a composition of Si _0.3 Ge _0.7 having a thickness of 5 nm is again formed by the UHV-CVD method, the MBE method, or the LP-CVD method. The Ge channel layer 39 made of Ge with a thickness of 5 nm is sequentially formed.

Subsequently, an amorphous Si layer 40 is formed as a Si cap layer on the Ge channel layer 39 by 2
nm deposition. In order to deposit amorphous Si, the substrate temperature is lowered to 300 ° C. or lower, and then Si raw material (Si atoms, silane gas, or disilane gas) is supplied [FIG.
(3)]. By depositing the Si layer 40 in an amorphous state on the Ge channel layer 39, it is possible to prevent the formation of surface irregularities and islands due to lattice mismatch and to obtain a flat surface. The amorphous Si layer is crystallized in a later step. At that time, the surface of the Si layer is covered with an oxide film, so that the flatness of the surface is maintained even when Si is crystallized. Therefore, when a field effect transistor is formed, carrier mobility can be kept high.

On the other hand, direct epitaxial growth of Si on the Ge channel layer 39 is not desirable because surface irregularities and islands due to lattice mismatching are formed.

Next, about 0.5 nm of Si is formed on the surface of the amorphous Si layer 40 with a hydrochloric acid / hydrogen peroxide mixture.
After forming an oxide film (not shown), a ZrO ₂ film 41 is deposited as a gate insulating film by laser ablation or sputtering, and subsequently a poly SiGe gate electrode 42 is deposited [
FIG. 8 (4)]. At this time, since the substrate temperature is 500 ° C. or higher, the amorphous Si layer 40 is crystallized by solid phase growth.

Source / drain regions 43 and the like are formed on the wafer thus obtained, and the normal M
The transistor is processed in the same manner as the OSFET process [FIG. 8 (5)].

Here, another method for obtaining a structure having the SiGe layer 37 having a high Ge composition shown in FIG. First, a gradient composition Si _1-x Ge _x layer (x = 0 → 0) having a thickness of 1 μm on a Si substrate.
. 1) A Si _0.9 Ge _0.1 layer having a thickness of 1.5 μm and a Si layer having a thickness of 20 nm are formed by UHV-C
Lamination is performed by the VD method, the MBE method, or the LP-CVD method.

Next, oxygen ions are accelerated by an acceleration voltage of 160 keV and a dose of 4 × 10 ¹⁷ atoms / cm.
^{2 is} implanted, and a thermal oxide film is formed on the surface at 900 ° C. to a thickness of 10 nm or more. S implanting oxygen ions
The reason why the Ge composition of the iGe layer is as low as 10 atm% is to obtain a continuous and uniform buried oxide film. If the Ge composition is 30 atm% or more, a continuous buried oxide film cannot be obtained by this method [Y. Ishikawa et al., Appl. Phys. Lett., 75, 983 (1999)].

Next, when annealing is performed at 1300 ° C. for 4 hours in an argon gas atmosphere containing a small amount of oxygen (0.5%), a buried oxide film is formed on the 300 nm substrate side from the oxide film-SiGe interface. Ge is excluded from the buried oxide film, so that it becomes almost pure SiO ₂ . Next, the wafer is etched with a mixed solution of hydrofluoric acid and nitric acid until the SiGe layer reaches 56 nm.

Next, when the SiGe layer is oxidized in an oxygen atmosphere until the SiGe layer reaches 8 nm, the Ge composition becomes 70 atm.
% And the structure shown in FIG.

(Example 2)
FIG. 9 shows a schematic diagram of the field effect transistor of the second embodiment. In this example,
In order to suppress an increase in parasitic resistance due to the thin film thickness of the source / drain region, in the transistor shown in FIG. 6 of the first embodiment, the surface of the source / drain region 19 is made of Al or W thin film 50 by selective CVD. Covered with.

(Example 3)
FIG. 10 shows a schematic diagram of the field effect transistor of the third embodiment. In the present embodiment, in order to suppress parasitic resistance, in the transistor shown in FIG. 6 of the first embodiment, a Si _0.3 Ge _0.7 layer 51 is selectively deposited on the source / drain region 19, The drain region thickness is increased to 100 nm. In order to fabricate this structure, a SiO ₂ mask is once deposited on the entire surface, then only the upper surfaces of the source / drain regions are exposed, and a SiGe layer is deposited by selective CVD.

(Example 4)
FIG. 11 shows a schematic diagram of the field effect transistor of the fourth embodiment. In this embodiment, the SiGe buffer layer 13 has a two-layer structure in the transistor shown in FIG. A second buffer layer 53 having a Ge composition of 75 atm% and a thickness of 10 nm is stacked on the first buffer layer 52 having a Ge composition of 55 atm% and a thickness of 5 nm formed by oxidation. According to this embodiment, the strain applied to the Ge channel is reduced by the presence of the second buffer layer.
It increases compared to the case of only the buffer layer. Therefore, compared to the first embodiment, the Ge composition of the first buffer layer can be kept low, so that the margin for film thickness control during oxidation increases.
Yield is improved.

As a modification of this embodiment, a structure in which the Ge composition of the second buffer layer increases continuously or stepwise as it approaches the surface is also possible.

(Example 5)
FIG. 12 shows an example in which the field effect transistor shown in the first embodiment shown in FIG. 6 is applied to a CMOS inverter. The p-channel and n-channel MOSFETs are insulated by a trench that reaches the buried oxide film. The substrate 11 is biased to function as a back gate for adjusting the threshold value.

1 is a schematic diagram illustrating one embodiment of a field effect transistor. FIG. The enlarged view of the pn junction part of the source region or drain region part in the field effect transistor which concerns on 1st prior art and embodiment of this invention. The figure which shows the band structure in the channel layer vicinity of the field effect transistor which concerns on embodiment of this invention, and 2nd prior art. The figure explaining Ge composition distribution during oxidation of the semiconductor layer containing Si and Ge in the manufacturing method of the semiconductor substrate concerning the present invention. The figure which shows the relationship between the diffusion length of Ge atom in Si, and the thickness by which SiGe is consumed per unit time by oxidation. 1 is a schematic diagram of a field effect transistor according to a first embodiment. FIG. Schematic which shows an example of a gate insulating film. Process drawing which shows the manufacturing method of the field effect transistor of a present Example. The schematic of the field effect transistor of a 2nd Example. The schematic of the field effect transistor of a 3rd Example. The schematic of the field effect transistor of a 4th Example. Schematic which shows the example which applied the field effect transistor shown to 1st Example to the CMOS inverter. Schematic which shows the field effect transistor structure of a 1st prior art example. Schematic which shows the field effect transistor structure of the 2nd prior art example. The characteristic view which shows the relationship of the electric current (log (Id) -voltage (Vg)) of the transistor of a 2nd prior art example, and Si-MOSFET. The characteristic view which shows the relationship of (Vg (gate voltage) -Vth (threshold voltage))-current of the transistor of a 2nd prior art example, and Si-MOSFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support base body 2 ... Insulating film 3 ... SiGe buffer layer (1st semiconductor layer)
4 ... Channel layer (second semiconductor layer)
5 ... Substrate 6 ... Source region, drain region 7 ... Gate insulating film 8 ... Gate electrode 11 ... Support base 12 ... Insulating film 13 ... First semiconductor layer (SiGe) Buffer layer)
14 ... Second semiconductor layer (channel layer made of strained Ge)
DESCRIPTION OF SYMBOLS 15 ... Si cap layer 16 ... Semiconductor substrate 17 ... Gate insulating film 18 ... Gate electrode 19 ... Source region and drain region 20 ... Reaction layer 31 with metal 31 ... Si layer 32 ... buried oxide film 33 ... SOI film 34 ... SOI substrate 35 ... Si _0.9 Ge _0.1 film 36 ... Si layer 37 ... SiGe layer with high Ge composition ( Si _0.3 Ge _0.7 layer )
37 '... SiGe buffer layer 38 ... Si oxide film 39 ... Ge channel layer 40 ... Amorphous Si layer 41 ... Gate insulating film 42 ... Gate electrode

Claims (12)

Epitaxially growing a first SiGe layer on an SOI substrate;
Performing an oxidation treatment to generate a Si oxide film on the surface of the first SiGe layer and to diffuse Ge from the Si oxide film to the first SiGe layer to generate a second SiGe layer having a higher Ge composition; When,
Peeling the Si oxide film;
Using a CVD method or a MBE method, the first 2SiGe on the layer, a method of manufacturing a semiconductor substrate, characterized in that a step of laminating the first 3 SiGe layer higher Ge composition than the first 2SiGe layer.   2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the oxidation treatment is performed by thermal oxidation using oxygen gas diluted to a concentration of 50% or less with an inert gas. 2. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a step of forming a Si layer having a thickness of 2 nm or less on the third SiGe layer .   4. The method of manufacturing a semiconductor substrate according to claim 3, further comprising the step of sequentially stacking a gate insulating film layer and a gate electrode layer on the Si layer. 2. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a step of sequentially stacking a gate insulating film layer and a gate electrode layer on the third SiGe layer . Epitaxially growing a first SiGe layer on an SOI substrate;
Epitaxially growing a Si layer on the first SiGe layer;
By performing the oxidation treatment, a Si oxide film is generated on the surface of the stacked layer of the Si layer and the first SiGe layer, and Ge is diffused from the Si oxide film to the first SiGe layer, so that the second having a higher Ge composition . Producing a SiGe layer; and
Peeling the Si oxide film;
Using a CVD method or a MBE method, the first 2SiGe on the layer, a method of manufacturing a semiconductor substrate, characterized in that a step of laminating the the first 2SiGe second 3SiGe layer higher Ge composition than layer and the Ge layer sequentially.   7. The method of manufacturing a semiconductor substrate according to claim 6, wherein the oxidation treatment is performed by thermal oxidation using an oxygen gas diluted to a concentration of 50% or less with an inert gas. 7. The method of manufacturing a semiconductor substrate according to claim 6, further comprising a step of forming a Si layer having a thickness of 2 nm or less on the Ge layer . 9. The method of manufacturing a semiconductor substrate according to claim 8, further comprising a step of sequentially stacking a gate insulating film layer and a gate electrode layer on the Si layer. 7. The method of manufacturing a semiconductor substrate according to claim 6, further comprising a step of sequentially stacking a gate insulating film layer and a gate electrode layer on the Ge layer .
A step of sequentially stacking a gate insulating film and a gate electrode film on a semiconductor substrate obtained by the method for manufacturing a semiconductor substrate according to claim 1, and forming the gate insulating film and the gate electrode film on the gate insulating film And a step of forming a gate insulating film and a gate electrode and forming a source / drain region to form a field effect transistor in which a channel is formed in the third SiGe layer of the semiconductor substrate. Production method. A step of sequentially stacking a gate insulating film and a gate electrode film on a semiconductor substrate obtained by the method for manufacturing a semiconductor substrate according to claim 6, and forming the gate insulating film and the gate electrode film on the gate insulating film And a step of forming a gate insulating film and a gate electrode and forming source / drain regions to form a field effect transistor in which a channel is formed in the Ge layer of the semiconductor substrate. Method.

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