JP3598271B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a high-speed, low-power-consumption transistor, particularly to a vertical field-effect transistor having strained SiGe (silicon germanium) or strained Ge (germanium) as a channel.
[0002]
[Prior art]
When stress strain is applied to the Si or SiGe crystal, the band structure is modulated and the mobility of electrons and holes is improved. In the strained Si layer formed on the lattice-relaxed SiGe crystal with little stress applied, the electron mobility and the hole mobility are expected to be improved by more than twice.
[0003]
On the other hand, up to now, high speed and high performance of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) have been realized by reducing the element size. However, in this case, since the gate processing accuracy by lithography is the key to success, the lower limit of the dimension is limited by the lithography technology.
[0004]
On the other hand, there is a measure to adopt a vertical structure in order to realize an element having a size of 50 nm or less. By introducing strain into this vertical element, the effect of improving carrier mobility can be taken.
[0005]
For example, K. C. Liu et al. (Tech. Dig. IEDM (1999) p. 63) report that a SiGe layer grown on a Si substrate as a thin film and not lattice-relaxed (having a crystal lattice extending in the vertical direction, that is, the layer thickness direction) has a columnar shape. A MOSFET structure is proposed in which a Si crystal is grown on the side wall of the column, the surface of the Si crystal is oxidized to form a gate electrode, and a source and a drain are formed at the top and bottom of the column. In this structure, the thickness of the SiGe layer can be used as the gate length, and an ultrafine element having a gate length of 50 nm or less can be realized. Further, since the strained Si crystal layer is formed in contact with the SiGe crystal whose lattice extends in the vertical direction, it is not necessary to prepare a SiGe crystal whose lattice has been relaxed unlike the conventional structure formed in a plane.
[0006]
On the other hand, there has been proposed a vertical MOSFET in which a lattice-relaxed SiGe layer is formed on a Si substrate to serve as a source, and a strained Si layer serving as a channel portion and a SiGe layer serving as a drain portion are sequentially stacked on the SiGe layer. 10-22501). In this structure, when the band structure of the source / channel portion is viewed, the energy of the conduction band increases on the source side, so that high-energy (accelerated) electrons can be introduced into the channel. As a result, particularly in the case of a FET having a short channel length, the speed of the accelerated electrons can reach the source before the speed of the electrons is reduced. Switching elements can be expected.
[0007]
On the other hand, as an element material technique for realizing the above-described element structure, a technique of directly forming a lattice-relaxed SiGe layer on an insulating film has been proposed. As a method of manufacturing a relaxed SiGe buffer layer on an oxide film, (1) a method of epitaxially growing SiGe on a thin film SOI (Silicon on Insulator) (AR Powell et al., Appl. Phys. Lett. 64, 1856) 1994)), (2) A method in which an oxide film formed on a Si substrate and a laminated structure of SiGe epitaxially grown on the Si substrate are bonded to each other, and a part of the SiGe laminated structure is removed later (Japanese Patent No. 3037934). And Japanese Patent No. 2908787), and (3) a method in which oxygen ions are implanted into a SiGe layer and a buried oxide film is formed in the SiGe layer through high-temperature annealing.
[0008]
[Problems to be solved by the invention]
The method of forming a strained Si layer on the side surface of a strained SiGe layer having a lattice extending in the vertical direction to form a channel is characterized in that the structure is made vertical as compared with a conventional lateral FET. On the other hand, in a vertical MOSFET using a strained Si layer above a relaxed SiGe layer as a channel, electrons with high energy can be injected, so that a device with higher performance can be expected.
[0009]
However, high-energy carriers can be injected from relaxed SiGe (source) into strained Si (channel) only for electrons whose conduction band positions on the source side are high, and the band structure of a valence material is reversed. , High energy holes cannot be injected into the channel. Therefore, this structure has a problem that it is not easy to manufacture a complementary MOSFET (CMOSFET).
[0010]
The present invention has been made based on the recognition of such problems, and an object of the present invention is to provide a vertical hetero MOSFET having a hetero structure capable of injecting high-energy carriers, which has a higher performance and can easily realize a CMOSFET. A semiconductor having a realizable structure is to provide a device.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention employs a structure in which a high Ge concentration SiGe buffer layer and a strained Ge channel are stacked on an insulating film.
[0012]
That is, the semiconductor device according to the present invention includes a first semiconductor crystal made of a group IV semiconductor, a second semiconductor crystal made of a group IV semiconductor stacked on the first semiconductor crystal, A third semiconductor crystal made of a group IV semiconductor stacked on the crystal, a gate insulating film covering a side wall of the second semiconductor crystal, and a side wall of the second semiconductor crystal via the gate insulating film A gate electrode provided above,
At least one of the first and third semiconductor crystals has a conduction band potential for electrons higher than the conduction band potential for electrons of the second semiconductor crystal, and a valence band potential for holes of the second semiconductor crystal. 2 is higher than the potential of the valence band for holes in the semiconductor crystal,
An inversion layer is induced on a side portion of the second semiconductor crystal by an electric field effect according to a voltage applied to the gate electrode, so that electrons or holes between the first semiconductor crystal and the third semiconductor crystal are generated. The flow is controlled.
[0013]
Here, the second semiconductor crystal is made of a semiconductor having a larger lattice constant than the first semiconductor crystal, and the second semiconductor crystal is parallel to a lamination plane with the first semiconductor crystal. It can have a compressive strain due to a compressive stress generated in various directions.
[0014]
In one of the first and third semiconductor crystals, the conduction band potential for electrons is higher than the conduction band potential for electrons of the second semiconductor crystal, and the valence band potential for holes is higher. Higher than the potential of the valence band for holes of the second semiconductor crystal,
The other one of the first and third semiconductor crystals may have a conduction band potential and a valence band potential substantially the same as those of the second semiconductor crystal.
[0015]
Further, the second semiconductor crystal may have a channel region of a first conductivity type and a drain region of a second conductivity type.
[0016]
Further, the first semiconductor crystal is made of silicon germanium (SiGe) containing 70 atomic% or more of germanium (Ge), and the second semiconductor crystal is more than germanium or the first semiconductor crystal. It may consist of silicon germanium containing a high concentration of germanium.
[0017]
Further, the first semiconductor crystal may contain carbon (C).
[0018]
According to the present invention, a strained Ge layer serving as a channel layer is stacked on a lattice-relaxed SiGe layer having a high Ge concentration and formed on an insulating film according to the present invention. The crystal layer in which the lattice is extended in the direction of travel can be used for the channel, and higher mobility can be expected.
[0019]
Further, according to the present invention, since the source portion of the conductor and the valence band have higher energy than the channel portion, a structure capable of injecting the accelerated charges of both electrons and holes into the channel can be realized. Thus, an ultra-high-speed CMOSFET can be easily manufactured.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021]
FIG. 1 is a conceptual diagram illustrating a cross-sectional configuration of a main part of a semiconductor device of the present invention. That is, in the semiconductor device of the present invention, a buried oxide film 2, a SiGe buffer layer (first source / drain portion) 3, a strained Ge channel layer 4, and a SiGe cap layer (second 5) are stacked, and a gate insulating film 6 and a gate electrode 7 are formed around the side wall of the strained Ge channel layer 4.
[0022]
Here, the lattice constant of the SiGe buffer layer 3 in the relaxed state is smaller than that of the Ge channel layer 4. A thin channel layer 4 is epitaxially stacked on the thick buffer layer 3. As a result, the lattice of the buffer layer 3 is relaxed, that is, has little distortion, and the channel layer 4 has distortion according to the difference in lattice constant.
[0023]
Specifically, a compressive stress is applied to the channel layer 4 in a direction parallel to the lamination surface. As a result, the crystal lattice of the channel layer 4 is compressed in a direction parallel to the stacking plane and stretched in a direction perpendicular to the stacking plane. Here, in Ge or SiGe, when the crystal lattice is stretched due to strain, there is an effect that the mobility of carriers increases in the stretching direction. That is, in the present invention, in the vertical FET, the mobility of carriers can be increased by generating a stretching strain along the channel direction, and a higher-speed operation can be realized.
[0024]
Here, the Ge composition of the SiGe buffer layer 3 is desirably 70 atomic% or more. This is because, when the Ge composition of the buffer layer 3 is 70 atomic% or less, when the strained Ge channel layer 4 is laminated to 50 nm or more, crystal defects such as dislocations may be generated in the channel layer 4. This is because the critical thermodynamic film thickness of Ge with respect to the Ge composition of 70 atomic% of the buffer layer 3 is 50 nm. A more desirable range of the Ge composition is 70 atomic% or more and 80 atomic% or less. The upper limit of 80 atomic% is a set value for enjoying the effect of increasing the hole mobility due to strain. That is, if the Ge composition is 80 atomic% or less, the phonon scattering mobility of holes becomes twice or more the mobility of unstrained Ge due to the influence of the strain applied to the Ge channel layer 4.
[0025]
Here, a similar effect can be obtained by using a strained Si _1-x Ge _x (0.8 <x <1) channel layer containing Si instead of the strained Ge channel layer 4.
[0026]
As the gate insulating film 6, for example, a Zr (zirconium) silicate / ZrO ₂ film can be used. This is a substance in which a metal such as Zr, Hf (hafnium), or La (lanthanum) is dissolved in silicate: SiO ₂ .
[0027]
Further, as the gate electrode 7, polycrystalline Si (polySi) or polycrystalline SiGe (polySiGe) doped with p-type or n-type can be used.
[0028]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
[0029]
2 and 3 are process cross-sectional views illustrating a main part manufacturing process of the semiconductor device of the present invention.
[0030]
First, as shown in FIG. 2A, a laminated structure including the Si substrate 1, the buried oxide film 2, the SOI film 11, the SiGe layer 12, and the Si cap layer 13 is formed. Specifically, for example, a UHV-CVD (ultra-high vacuum chemical vapor deposition) is formed on a silicon-on-insulator (SOI) substrate 10 including a Si substrate 1, a buried oxide film 2, and an SOI film 3 (about 20 nm in thickness). ) Method, MBE method or LP-CVD method, etc., to grow the Si _0.9 Ge _0.1 film 12 to about 150 nm and the Si cap layer 13 to about 5 nm. Since the thickness of each layer formed at this time is lower than the critical thickness at the growth temperature, misfit dislocation does not occur.
[0031]
Next, as shown in FIG. 2B, a thermal oxide film 14 is formed. Specifically, this wafer is put into an oxidation furnace, and oxidation is progressed at, for example, about 1000 ° C. using an oxygen gas diluted to 50% with nitrogen until the thickness of the SiGe layer 3 becomes 25 nm. In this oxidation process, Ge atoms can sufficiently diffuse inside the SiGe layer 3 sandwiched between the buried oxide film 2 (lower layer) and the thermal oxide film 14 (upper layer), but the upper and lower oxide films are Atoms cannot penetrate. For this reason, as the thermal oxidation progresses, the thickness of the SiGe layer 3 is reduced, and the Ge concentration is increased to about 70 atomic%.
[0032]
Here, care must be taken that the processing temperature does not exceed the melting point of the SiGe layer 12. In the case of this specific example, the final oxidation temperature must be 1025 ° C. or lower in order to obtain a SiGe layer 3 having a Ge concentration of 70 atomic%. In order to shorten the oxidation time without melting the SiGe layer, the temperature is initially set to a high value within a range not exceeding the melting point corresponding to the Ge concentration in the SiGe layer, and the temperature is gradually or gradually reduced. It is effective to go.
[0033]
Next, as shown in FIG. 2C, the thermal oxide film 14 is peeled off, and arsenic (As) is ion-implanted into the entire surface of the wafer at a dose of about 5 × 10 ¹⁵ cm ⁻² . Thereafter, annealing is performed to lower the resistance of the injection layer.
[0034]
Next, as shown in FIG. 2D, a crystal layer is stacked. Specifically, after the surface cleaning, a Ge channel layer 4 having a thickness of 30 nm and a Si _0.3 Ge _0.7 layer 5 having a thickness of 100 nm are again formed by a method such as UHV-CVD, MBE or LP-CVD. (Upper source / drain). At this time, it is desirable that the Si _0.3 Ge _0.7 layer 5 (upper source / drain portion) is subjected to high-concentration n-type doping, but ion implantation may be performed again after the epitaxial growth.
[0035]
Subsequently, patterning is performed as shown in FIG. Specifically, a photoresist pattern (not shown) is formed on the wafer surface, and the n-type Si _0.3 Ge _0.7 layer 5 and the Ge channel layer 4 are formed by using the resist pattern as a mask by RIE (reactive ion etching). To form an island. The resist pattern is peeled off after the completion of the etching.
[0036]
Next, as shown in FIG. 3B, a thin insulating film 16 having a thickness of about 3 nm is formed on the wafer surface by a CVD method or the like. Part of the insulating film 16 becomes the gate insulating film 6.
[0037]
Thereafter, as shown in FIG. 3C, a polycrystalline Si layer 17 having a thickness of about 20 nm is deposited on the entire surface of the wafer for a gate electrode, and phosphorus (P) is doped at a dose of about 5 × 10 ¹⁵ cm ^−2. The polycrystalline Si layer 17 is made to have a high concentration of n-type by ion implantation in an amount and further annealing.
[0038]
Next, as shown in FIG. 3D, a gate electrode is formed. Specifically, the polycrystalline Si layer 17 is etched back from above by anisotropic etching. Thus, the gate electrode 7 is formed with the n-type polycrystalline Si layer left on the side surface of the island-shaped projection P. Here, before etching back by anisotropic etching, the surface of the wafer is polished by CMP (chemical mechanical polishing) to remove the polycrystalline Si layer 17 on the upper surface of the island-shaped projections P. It may be.
[0039]
Thereafter, by opening a part of the insulating film 16, upper and lower source / drain electrodes are formed, and the main part of the transistor of the present invention is completed.
[0040]
Next, another method for obtaining the laminated structure shown in FIG. 2C will be described.
[0041]
FIG. 4 is a schematic process sectional view showing this method.
[0042]
First, the laminated structure shown in FIG. 4A is formed. Specifically, a thickness of about 1μm on a graded composition _{Si 1-x} Ge _x layer 21 Si substrate 1 (where the composition x increases from 0 to about 0.1 with increasing distance from the substrate 1), A Si _0.9 Ge _0.1 layer 22 having a thickness of about 1.5 μm and a Si cap layer 23 having a thickness of about 20 nm are stacked. As the lamination method, the above-described UHV-CVD, MBE method, LP-CVD method, or the like can be used.
[0043]
Next, as shown in FIG. 4B, a buried oxide film is formed. Specifically, oxygen ions are implanted under the conditions of an acceleration voltage of 160 keV and a dose of about 4 × 10 ¹⁷ ions / cm ² , and oxidized at 900 ° C. to form a thermal oxide film 24 on the wafer surface to a thickness of 10 nm or more. Form. The reason why the Ge composition of the SiGe layer 22 into which oxygen ions are implanted is as low as 10 atomic% is to obtain a continuous and uniform buried oxide film. When the Ge composition is 30 atomic% or more, it is difficult to obtain a continuous buried oxide film by this method (Y. Ishikawa et al., Appl. Phys. Lett., 75, 983 (1999)).
[0044]
Next, when annealing is performed at 1300 ° C. for about 4 hours in an argon gas atmosphere containing a small amount of oxygen (0.5%), the buried oxide film 2 is formed on the substrate side about 300 nm from the upper surface of the SiGe layer 22. Ge is removed from the buried oxide film ₂ and becomes almost pure SiO ₂ .
[0045]
Next, as shown in FIG. 4C, when this wafer is etched with a mixed solution of hydrofluoric acid and nitric acid until the thickness of the SiGe layer 2 becomes about 23 nm, a structure similar to that of FIG. can get.
[0046]
In the present invention, a metal such as W (tungsten) can be used as the material of the gate electrode 7. Further, as the gate insulating film 6, not only a Si oxide film (SiO _x ), but also a Si nitride film (Si ₃ N ₄ ), a Si oxynitride film (SiO _x N _y ), Al ₂ O ₃ , Ta ₂ O ₅ , High dielectric insulating films such as TiO ₂ and Ya ₂ O ₃ can also be used.
[0047]
Further, as the gate insulating film 6, a Ge nitride film can be used in addition to the above-described materials. This Ge nitride film can be obtained not only by deposition by CVD, but also by nitriding the Ge surface directly with ammonia gas or nitrogen gas.
[0048]
Further, the plane orientation of the substrate 1 is not limited to (001), but may be another plane orientation, for example, a (111) substrate or a (110) substrate.
[0049]
Next, a modification of the semiconductor device of the present invention will be described.
[0050]
In the semiconductor device illustrated in FIG. 1, the channel portion is formed as a strained Ge (germanium) layer 4 and the upper and lower source / drain portions are formed of the SiGe layers 3 and 5, but the drain portion may be formed of Ge. Good. This makes it possible to further enhance the effect of the ballistic injection of the carrier.
[0051]
FIG. 5A is a conceptual diagram showing a band diagram when the channel portion C is formed by strain Ge and the source portion S and the drain portion D are both formed by SiGe as illustrated in FIG. That is, the potential of both the electron and the hole is higher on both sides of the source section S and the drain section D than on the Ge channel layer (channel section) C. In this case, both the conduction band and the valence band have higher energy in the source than in the channel, so that accelerated charges can be injected into the channel for both electrons and holes, and the same material system can be used easily. An ultra-high-speed CMOSFET can be manufactured.
[0052]
Further, when the source portion S is formed by SiGe and the drain portion D is formed by the same strain Ge as the channel portion C, as shown in FIG. However, the potential barrier disappears.
[0053]
In order to inject ballistic carriers, which is one of the features of the semiconductor device of the present invention, it is required that the potential of the source part is higher than that of the channel part, but any potential on the drain side is acceptable. Therefore, the following points should be considered in designing the potential on the drain side, that is, in selecting a material.
[0054]
First, when the drain side is formed of Ge, the boundary between the channel and the drain does not become a heterojunction, so that the doping profile can be easily designed.
[0055]
However, since a Ge layer having a different lattice constant is grown on the source portion made of SiGe, the thickness of the stack needs to be equal to or less than the so-called critical thickness. Further, in the case of forming a CMOS by combining a plurality of FETs, in a vertical structure such as the present invention, it is convenient if the lower side can be freely selected as a source or a drain. That is, a symmetrical structure in which the source and the drain are made of the same material has a higher degree of freedom when designing a circuit such as an inverter.
[0056]
On the other hand, when the drain portion is formed of SiGe, the boundary between the channel and the drain becomes a heterojunction. In this case, it is desirable that the profile of impurity implantation into the hetero interface and the drain coincide with each other. On the other hand, a structure in which the junction between the channel and the drain is provided to be shifted may be considered.
[0057]
FIG. 6A is a conceptual cross-sectional view illustrating a structure in which a junction between a channel and a drain is provided inside a strained Ge layer, and FIG. 6B is a conceptual diagram illustrating a band diagram of this structure. . In the configuration shown in FIG. 2, the SiGe layer 51, the strained Ge layer 52, and the SiGe layer 53 are sequentially stacked. By adjusting the doping profile in the strained Ge layer 52, the junction between the channel portion C and the drain portion D is adjusted. J is formed inside the strained Ge layer 52. This eliminates the potential barrier between the channel and the drain, and provides a vertical FET which is nearly vertically symmetric.
[0058]
In the specific examples described above, the combination of the SiGe layer and the strained Ge layer, or the combination of the SiGe layer and the strained SiGe layer has been described. However, the present invention is not limited to these, and it is also possible to use a SiGeC crystal in which C (carbon) is added at a concentration of about 5% or less in the SiGe crystal. The addition of C makes it possible to increase the difference in lattice constant between the strained Ge layer and the strained SiGe layer while maintaining the band gap of SiGe.
[0059]
In addition, when SiGeC is used for the source / drain portions, an effect that diffusion of impurities can be suppressed is also obtained.
[0060]
Next, a CMOS inverter according to the present invention will be described.
[0061]
FIG. 7 is a conceptual diagram illustrating an example of the CMOS inverter according to the present invention. That is, the inverter shown in the figure has an n-channel transistor 60A and a p-channel transistor 60B formed on a common Si substrate 1 and a buried oxide film 2. These transistors have, for example, the configuration of the present invention as described above with reference to FIGS. More specifically, for example, the SiGe buffer layers 3A and 3B, the strained Ge channel layers 4A and 4B, and the SiGe cap layers 5A and 5B. In these layers, the conductivity type and the carrier concentration are adjusted according to either the n-channel or the p-channel.
[0062]
The gate electrodes 7A and 7B are connected by a common input wiring W1. Further, one of the source and the drain of the n-channel transistor 60A and the other of the source and the drain of the p-channel transistor 60B are connected by a common output wiring W2. Further, the zero volt input wiring W3 and the plus one volt input wiring W4 are respectively connected to either the source or the drain, and the transistors 60A and 60B perform complementary operation.
[0063]
Here, when forming the p-channel transistor 60B, for example, boron (B) may be ion-implanted as an additional impurity instead of arsenic (As). That is, if the ion implantation is performed twice in accordance with the ion implantation region, the n-channel transistor and the p-channel transistor can be formed over the same substrate.
[0064]
Note that, also in the CMOS inverter of this specific example, a vertical FET combining a SiGe layer and a strained SiGe channel layer can be used. Alternatively, a SiGeC layer to which carbon is added and a strained Ge channel layer (or a strained SiGe channel layer) may be combined.
[0065]
【The invention's effect】
As described in detail above, according to the present invention, a strained Ge layer or a strained SiGe layer serving as a channel layer is laminated on a lattice-relaxed SiGe layer formed on an insulating film, and further a SiGe layer is further formed thereon. By forming this, the strained Ge layer can be used as a channel, and a vertical MOSFET with higher mobility can be realized.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram illustrating a cross-sectional configuration of a main part of a semiconductor device of the present invention.
FIG. 2 is a process cross-sectional view illustrating a main part manufacturing process of the semiconductor device of the present invention.
FIG. 3 is a process cross-sectional view illustrating a main part manufacturing process of the semiconductor device of the present invention.
FIG. 4 is a schematic process sectional view showing another method for obtaining the laminated structure shown in FIG. 2 (c).
FIG. 5A is a conceptual diagram showing a band diagram when a channel portion C is formed by strain Ge and a source portion S and a drain portion D are both formed by SiGe as illustrated in FIG. 1; (B) is a conceptual diagram showing a band diagram in a case where the source portion S is formed of SiGe and the drain portion D is formed of the same strain Ge as the channel portion C.
6A is a conceptual cross-sectional view illustrating a structure in which a junction between a channel and a drain is provided inside a strained Ge layer, and FIG. 6B is a conceptual diagram illustrating a band diagram of this structure. .
FIG. 7 is a conceptual diagram illustrating an example of a CMOS inverter according to the present invention.
[Explanation of symbols]
Reference Signs List 1 substrate 2 buried oxide film 3, 3A, 3B SiGe buffer layer 4, 4A, 4B strained Ge channel layer 5, 5A, 5B SiGe cap layer 6 gate insulating film 7 gate electrode W1, W2, W3, W4 Wiring

Claims (4)

An insulating film formed on the semiconductor layer;
A first semiconductor crystal made of silicon-germanium (SiGe) formed on the insulating film and containing 70 atomic% or more of germanium (Ge) ;
A second semiconductor crystal made of silicon germanium stacked on the first semiconductor crystal and containing germanium or germanium at a higher concentration than the first semiconductor crystal;
A third semiconductor crystal stacked on the second semiconductor crystal and made of germanium, or silicon-germanium containing germanium at the same or lower concentration than the second semiconductor crystal;
A gate insulating film covering a side wall of the second semiconductor crystal;
A gate electrode provided on a side wall of the second semiconductor crystal via the gate insulating film;
With
In the first semiconductor crystal , the conduction band potential for electrons is higher than the conduction band potential for electrons of the second semiconductor crystal, and the valence band potential for holes is positive for the second semiconductor crystal. Higher than the potential of the valence band for the hole,
The third semiconductor crystal has a conduction band potential for electrons equal to or higher than a conduction band potential for electrons of the second semiconductor crystal, and a valence band potential for holes of the second semiconductor crystal. The same as or higher than the potential of the valence band for holes of
An inversion layer is induced near the side wall of the second semiconductor crystal by an electric field effect according to a voltage applied to the gate electrode, so that electrons or positive electrons between the first semiconductor crystal and the third semiconductor crystal are generated. A semiconductor device that controls the flow of holes. The second semiconductor crystal is made of a semiconductor having a larger lattice constant than the first semiconductor crystal,
2. The semiconductor device according to claim 1, wherein the second semiconductor crystal has a compressive strain caused by a compressive stress generated in a direction parallel to a plane of stacking with the first semiconductor crystal. 3. 3. The semiconductor device according to claim 1, wherein the second semiconductor crystal has a channel region of a first conductivity type and a drain region of a second conductivity type. 4. The semiconductor device according to claim 1, wherein the first semiconductor crystal contains carbon (C). 5.

Images