JP2004214457A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device composed of complementary field effect transistors each improved in mobilities of both carriers of a positive hole and an electron by a simplified process. <P>SOLUTION: There are manufactured a PMOSFET 10a that forms a p-channel in which positive holes move in the direction of the compression stress of an SiGe layer 2 formed on an Si substrate 1 and comprising (Ge) having a lattice constant different from that of the case of Si, and an NMOSFET 10b that forms an n-channel in which electrons move in the direction of the tensile stress of the SiGe layer 2. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including complementary field-effect transistors.
[0002]
[Prior art]
With the advancement of advanced information, high-speed MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are required in order to enable large-capacity and high-speed data communication.
[0003]
In a MOSFET, the mobility of holes or electrons is improved by applying compression or tensile strain to a semiconductor layer serving as a channel. Until now, by stacking a silicon germanium (hereinafter, referred to as SiGe) layer on a silicon (hereinafter, referred to as Si) substrate having a (001) plane as a main surface, a SiGe layer subjected to in-plane compressive strain due to a difference in lattice constant. Among them, it has been reported that the effective mass of holes is reduced and the hole mobility is improved. On the other hand, the electrons of the SiGe layer subjected to the in-plane compressive strain have electron mobility lower than the value in Si in the horizontal direction to the film surface. Therefore, it has been difficult to improve both the mobility of holes and electrons in strained SiGe formed on a Si (001) substrate.
[0004]
In order to solve this problem, a p-channel MOSFET (hereinafter referred to as a PMOSFET) is a strained SiGe channel which is effective in improving the mobility of holes, and an n-channel MOSFET (hereinafter referred to as an NMOSFET) is a device which improves the mobility of electrons. There has been proposed a complementary field effect transistor using a transistor to which a strained Si channel is applied, which is effective for the above.
[0005]
On the other hand, a complementary field-effect transistor using a vertical MOSFET that moves carriers in a direction perpendicular to the stacked surface of strained SiGe or strained Ge (direction of tensile strain) has been proposed (for example, Patent Document 1). .
[0006]
[Patent Document 1]
JP-A-2002-203971 (FIG. 7)
[0007]
[Problems to be solved by the invention]
However, in order to form the strained Si on the Si substrate, a lattice-relaxed SiGe layer having a thickness of about several μm must be formed, and the strained SiGe layer has a lattice relaxation of about several tens nm. Therefore, there is a problem that it is difficult to coexist both of them in terms of process.
[0008]
Also, as described above, in the case of a vertical MOSFET in which carriers move in a direction perpendicular to the stacked surface of strained SiGe or strained Ge, the mobility of electrons is improved by moving electrons in the direction of tensile strain. Is possible. However, as described above, the hole does not consider that the mobility is improved in the direction of the in-plane compressive strain.
[0009]
The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device including complementary field-effect transistors in which the mobility of both holes and electrons is improved.
[0010]
Another object of the present invention is to provide a semiconductor device manufacturing method for manufacturing a semiconductor device including complementary field-effect transistors in which the mobility of both holes and electrons is improved by a simple process. is there.
[0011]
[Means for Solving the Problems]
According to the present invention, in order to solve the above problems, in a semiconductor device including complementary field-effect transistors, as shown in FIG. 1, a SiGe layer containing germanium (Ge) having a different lattice constant from Si formed on a Si substrate 1. 2. A semiconductor device 10 comprising: a PMOSFET 10a forming a p-channel in which holes move in the direction of compressive stress 2; and an NMOSFET 10b forming an n-channel in which electrons move in the direction of tensile stress of the SiGe layer 2. Is provided.
[0012]
According to the above configuration, since the p-channel is formed in the direction of the compressive stress and the n-channel is formed in the direction of the tensile stress, both the mobilities of holes and electrons are improved.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention.
[0014]
The semiconductor device 10 according to the first embodiment of the present invention is formed on a p-type Si substrate 1 having a (001) plane as a main surface, using SiGe containing Ge having a lattice constant different from that of Si. It comprises a horizontal PMOSFET 10a and a vertical NMOSFET 10b.
[0015]
The PMOSFET 10a has an n-type SiGe layer 2 formed on a Si substrate 1 and having a (001) plane as a main surface, p-type drain or source regions 5a and 5b having a high impurity concentration, and a gate oxide film 3a. And a gate electrode 4a to be formed.
[0016]
On the other hand, the NMOSFET 10b includes an n-type drain or source region 2a, 2b and a p-type channel region 2c formed by performing ion implantation on the SiGe layer 2 by a method described later, and a gate formed on the sidewall SW. It is composed of a gate electrode 4b arranged via an oxide film 3b.
[0017]
Note that the side wall portion SW has a (100) plane or a (110) plane perpendicular to the substrate plane (001), or a (-100) plane, a (010) plane, a (0-10) plane, or an equivalent plane. (-110) plane, (1-10) plane, and (-1-10) plane.
[0018]
Further, trenches tr1 and tr2 are formed in the semiconductor device 10, and the oxide film 3 is buried in the semiconductor device 10, thereby performing isolation between elements. In the PMOSFET 10a, the wirings 7a and 7c are connected to the drain or source regions 5a and 5b, and the wiring 7b is connected to the gate electrode 4a. On the other hand, in the NMOSFET 10b, the wirings 7d and 7f are connected to the drain or source regions 2b and 2a, and the wiring 7e is connected to the gate electrode 4b. An insulating film 6 for preventing a short circuit is formed between the wirings.
[0019]
Here, the PMOSFET 10a and the gate electrodes 4a and 4b of the NMOSFET 10b are connected by wirings 7b and 7e, and one of the drain or source regions 5a and 5b of the PMOSFET 10a and one of the drain or source regions 2a and 2b of the NMOSFET 10b are connected by wiring. A CMOS (Complementary MOS) is configured by connecting the devices with 7a, 7c, 7d, and 7f.
[0020]
It is necessary that the thickness of the SiGe layer 2 be equal to or less than a critical thickness at which lattice relaxation does not occur. For example, it is desirable to set the Ge ratio to 0.2 to about 20 nm or less. The oxide film 3, the gate oxide films 3a and 3b, and the insulating film 6 are made of, for example, silicon oxide (SiO 2). ₂ ). In the gate oxide films 3a and 3b, aluminum oxide (Al ₂ O ₃ ), Hafnium oxide (HfO ₂ ), Zircon (ZrO) ₂ ) May be used. Further, the insulating film 6 may use a low dielectric constant material. For the gate electrodes 4a and 4b, a metal such as SiGe, SiGeC (C is carbon), and aluminum (Al) may be used in addition to poly-Si. The wirings 7a, 7b, 7c, 7d, 7e, 7f are, for example, aluminum (Al) or copper (Cu).
[0021]
In the PMOSFET 10a, when a gate voltage is applied to the gate electrode 4a by the wiring 7b, the surface of the n-type SiGe layer 2 under the gate electrode 4a is inverted to p-type, and the in-plane <100> direction or <110> direction. A p-channel is formed in the direction. At this time, by applying a voltage to the drain or source regions 5a, 5b by the wirings 7a, 7c, a hole current flows through the p-channel.
[0022]
On the other hand, in the NMOSFET 10b, when a gate voltage is applied to the gate electrode 4b through the wiring 7e, the surface of the channel region 2c of the side wall SW on the gate electrode 4b side is inverted to the n-type. At this time, by applying a voltage to the drain or source region 2a, 2c by the wirings 7d, 7f, an electron current flows through the n-channel in the <001> direction.
[0023]
The SiGe layer 2 formed on the Si substrate 1 having the (001) plane as the main surface has the (001) plane as the main surface, is distorted due to the difference in lattice constant between Si and Ge, and is <100 in the in-plane direction. >, <110> directions generate a compressive stress, and a <001> direction, which is the film thickness direction, generates a tensile stress. In the semiconductor device 10 according to the first embodiment of the present invention, the PMOSFET 10a has a p-channel in the in-plane direction, and the NMOSFET 10b has an n-channel in the film thickness direction. That is, in the semiconductor device 10, a p-channel is formed in the direction of the compressive stress and an n-channel is formed in the direction of the tensile stress. Thereby, the mobilities of holes and electrons are increased, and the current driving capability can be improved. The reason will be described in detail below.
[0024]
FIGS. 2A and 2B are diagrams showing an equal energy surface of a conduction band lower end (valley) in a wavenumber space (K space) of a MOSFET, wherein FIG. 2A is a three-dimensional diagram, FIG. C) is a projection view in the <100> direction.
[0025]
FIGS. 3A and 3B are diagrams showing a valley level difference between Si and strained SiGe caused by two-dimensional quantization of channel electrons. FIG. 3A shows a case where two-dimensional quantization is performed in the <001> direction, and FIG. FIG. 4 is a diagram illustrating a valley level difference when two-dimensional quantization is performed in the <100> direction.
[0026]
As shown in FIG. _x Direction, k _y Direction and k _z In each of the two directions, normal Si valleys 100a, 101a, and 102a indicated by solid lines and strained SiGe valleys 100b, 101b, and 102b indicated by dotted lines are arranged on the K space in the shape of a spheroid.
[0027]
It is reported that the level difference due to the distortion is about 0.12 eV higher in the valley 100b than in the valleys 101b and 102b at a Ge ratio of 0.2.
When the electrons in the channel inversion layer of the NMOS are considered as a two-dimensional state, in the planar MOSFET, the valley is represented by a projection in the <001> direction as shown in FIG. At this time, the degeneration into the valleys 100a, 101a, and 102a can be resolved by the quantization in the <001> direction. When the electric field intensity immediately below the gate is 1 MV / cm, the difference is about 0.12 eV higher in the valleys 101a and 102a than in the valley 100a (FIG. 3A). The quantum level difference of the channel electrons is represented by the sum of the level difference caused by the distortion and the level difference caused by the two-dimensional quantization (J. Welser et al, IEDM94 p.373-p.376). In the case of the type-strained SiGe channel, the quantum level difference of the channel electrons in the channel inversion layer is almost equal to 0 (FIG. 3A). Since electrons occupy a low energy level preferentially, in the case of a strained SiGe MOSFET, the probability of the existence of electrons in the valleys 101b and 102b increases compared to the valleys 101a and 102a of the SiMOSFET. The effective mass of the conduction electrons is proportional to the square root of the component overlapping the current direction with the radius from the center of the valley, and the electrons in the valleys 101b and 102b are larger than the electrons in the valley 100b. Effective mass increases. This makes it difficult to improve the mobility.
[0028]
On the other hand, in the case of a vertical MOSFET, when the channel is formed on the (100) plane, the valley is represented by a projection in the <100> direction as shown in FIG. 2C. The channel electrons are degenerated into valleys 100a, 101a, and 102b by two-dimensional quantization as shown in the SiMOSFET of FIG. 3B, and the level difference becomes 0.12 eV. On the other hand, in the case of strained SiGe channel electrons, degeneracy is resolved into three valleys 100b, 101b, and 102b as shown in FIG. 3B by considering the level difference due to the strain and two-dimensional quantization. The valley 102b is located at a level higher by 0.12 eV than the low valley 101b, and the valley 100b is located at a level higher by 0.12 eV. When the channel is taken in the <001> direction, the effective mass of the conduction electrons is smaller in the valleys 101b and 102b than the electrons in the valley 100b. It becomes lighter and electron mobility improves.
[0029]
From these facts, as in the semiconductor device 10 according to the first embodiment of the present invention, the vertical NMOSFET 10b is formed on the Si substrate 1 having the (001) plane as the main surface, and the strained SiGe channel region 3b is formed. When a channel for moving electrons is formed in the vertical pulling direction, the mobility of electrons can be increased. In addition, the mobility of holes can be increased by forming the lateral PMOSFET 10a on the Si substrate 1 and forming a channel for moving holes in the compression direction of the n-type strained SiGe layer 2. . As a result, it is possible to form a CMOS in which the current drive capability of both the PMOSFET 10a and the NMOSFET 10b is improved.
[0030]
Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described.
4 to 12 are cross-sectional views of the semiconductor device in respective steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
[0031]
First, as shown in FIG. 4, an n-type SiGe layer 2 is grown by epitaxial growth on a p-type Si substrate 1 having a (001) plane as a main surface. At this time, it is necessary that the thickness of the SiGe layer 2 be equal to or less than the critical thickness at which lattice relaxation does not occur. For example, it is about 20 nm or less at a Ge ratio of 0.2. After that, trenches tr1 and tr2 are formed as shown in FIG. Here, the oxide film 3 is, for example, SiO 2 ₂ It is.
[0032]
Next, in order to form a vertical NMOSFET 10b as shown in FIG. 6, an impurity is introduced into the SiGe layer 2 by ion implantation so as to be n-type, p-type, and n-type. Thus, n-type drain or source regions 2a and 2b and a channel region 2c are formed. At this time, the distribution width of the source / gate / drain is controlled by the energy of the implanted ions. For example, the region width of the p-type portion of the channel region 2c is set to about 10 nm.
[0033]
The impurity may be mixed at the same time as the formation of the SiGe layer 2. At this time, SiOGe is prevented from growing in the region where the PMOSFET 10a is formed so that SiGe does not grow. ₂ It is necessary to cover with. After growing the NMOSFET 10b region, the NMOSFET 10b is ₂ Then, SiGe growth and impurity doping are performed on the PMOSFET 10a region.
[0034]
Next, as shown in FIG. 7, anisotropic etching is performed to expose the side wall SW of SiGe forming the NMOSFET 10b. At this time, it is necessary to perform etching so that the side wall portion SW has a (100) plane or a (110) plane perpendicular to the main surface (001) of the Si substrate 1, or a plane equivalent thereto.
[0035]
After the etching, a Si layer is deposited by a chemical vapor deposition method, and subsequently thermally oxidized, thereby simultaneously forming the gate oxide films 3a and 3b of the p-type and n-type MOSFETs 10a and 10b. The gate oxide films 3a and 3b are not particularly distinguished from the oxide film 3, and the oxide film in the channel region will be described as the gate oxide films 3a and 3b. Also, instead of the Si layer, aluminum oxide (Al ₂ O ₃ ), Hafnium oxide (HfO ₂ ), Zircon (ZrO) ₂ ) May be used. Thereafter, as shown in FIG. 8, a polysilicon layer 4 serving as a gate is deposited.
[0036]
Note that a metal such as SiGe, SiGeC (a mixed crystal of silicon, germanium, and carbon), and Al may be used instead of polysilicon.
FIG. 9 shows a step of forming a gate. The gate electrodes 4a and 4b of the PMOSFET 10a and the NMOSFET 10b are formed by photolithography and anisotropic etching. At this time, the channel direction of the PMOSFET 10a is set to the <100> or <110> direction. It should be noted that the NMOSFET 10b may use a sidewall formed in self-alignment with the sidewall SW as a gate.
[0037]
Next, a PMOSFET portion is formed using the same manufacturing method as that of the related art.
As shown in FIG. 10, a p-type dopant is implanted only into the PMOSFET region to form drain / source regions 5a and 5b. At this time, the SiO 2 is formed by chemical vapor deposition. ₂ After the film is formed, a sidewall may be formed in a self-aligned manner on the sidewall of the gate electrode 4a of the PMOSFET by anisotropic etching of the entire surface, and a p-type dopant may be implanted.
[0038]
Next, as shown in FIG. 11, after depositing the insulating film 6 by the chemical vapor deposition method, contact holes with the source, drain and gate of the PMOSFET 10a and the NMOSFET 10b are formed as shown in FIG. The insulating film 6 is made of, for example, SiO 2 ₂ And a low dielectric constant material may be used. In forming the contact holes, the insulating film 6 may be planarized in advance by a CMP (Chemical Mechanical Polishing) process. In forming a contact hole, in order to configure a CMOS, one contact hole includes two sources or drains of the PMOSFET 10a and the NMOSFET 10b, and is formed so that the source or the drain of the PMOSFET 10a and the NMOSFET 10b are shared. You may.
[0039]
Finally, the wiring metal is sputtered, and the wiring patterns 7a, 7b, 7c, 7d, 7e, and 7f are processed by lithography and etching so that the p-type and n-type gates are connected to the source and drain portions, respectively. Thus, the semiconductor device 10 having the complementary MOSFET of the PMOSFET 10a and the NMOSFET 10b as shown in FIG. 1 can be manufactured.
[0040]
By forming the PMOSFET 10a and the NMOSFET 10b on a common SiGe thin film by such a method, the mobility of holes and electrons is improved, and the current driving capability of the CMOS is improved by an easier process than conventionally proposed. It is possible to do. Further, by forming the NMOSFET 10b in the vertical direction, the gate length can be formed to be about several nm by controlling the film thickness without depending on the existing lithography technique, and the degree of integration can be further improved.
[0041]
Next, a semiconductor device according to a second embodiment of the present invention will be described.
FIG. 13 is a sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention.
[0042]
The semiconductor device 20 according to the second embodiment of the present invention includes a horizontal NMOSFET 20a formed using SiGe on an n-type germanium (Ge) substrate 21 having a (001) plane as a main surface, and a vertical NMOSFET 20a. And a PMOSFET 20b.
[0043]
The NMOSFET 20a includes a p-type SiGe layer 22 formed on a Ge substrate 21 having a (001) plane as a main surface, n-type drain or source regions 25a and 25b having a high impurity concentration, and a gate oxide film 23a. And a gate electrode 24a to be formed.
[0044]
On the other hand, the PMOSFET 20b is formed by implanting ions into the SiGe layer 22 and has p-type drain or source regions 22a and 22b having a high impurity concentration and an n-type channel region 22c, and a gate oxide film formed on the side wall SW. It comprises a gate 24b arranged via 23b.
[0045]
The side wall SW is a (100) plane or a (110) plane perpendicular to the substrate plane (001), or a plane equivalent thereto.
Further, trenches tr21 and tr22 are formed in the semiconductor device 20, and an oxide film 23 is buried in the semiconductor device 20, thereby performing isolation between elements. In the NMOSFET 20a, the wirings 27a and 27c are connected to the drain or source regions 25a and 25b, and the wiring 27b is connected to the gate 24a. On the other hand, in the PMOSFET 20b, the wirings 27d and 27f are connected to the drain or source regions 22a and 22b, and the wiring 27e is connected to the gate 24b. An insulating film 26 for preventing a short circuit is formed between the wirings.
[0046]
Here, the NMOSFET 20a and the gates 24a and 24b of the PMOSFET 20b are connected by wirings 27b and 27e, and one of the drain or source regions 25a and 25b of the NMOSFET 20a and one of the drain or source regions 22a and 22b of the PMOSFET 20b are connected to the wiring 27a. , 27c, 27d and 27f to form a CMOS.
[0047]
The semiconductor device 20 according to the second embodiment of the present invention differs from the semiconductor device 10 according to the first embodiment in that a Ge substrate 21 is used instead of the Si substrate 1. When the SiGe layer 22 is formed on the Ge substrate 21 having the (001) plane as the main surface, the lattice constant of Si is about 4% smaller than the lattice constant of Ge of the substrate. Contrary to 10, tensile strain occurs in the plane of the SiGe layer 22, and compressive strain occurs in the film thickness direction. In the semiconductor device 20 according to the second embodiment of the present invention, a horizontal NMOSFET 20a and a vertical PMOSFET 20b are provided, an n-channel is provided in a <100> direction or a <110> direction, and a (100) plane or a (110) plane. A p-channel in the <001> direction is formed on side wall portion SW of the surface. That is, also in the semiconductor device 20 of the second embodiment using the Ge substrate 21, the p-channel is formed in the direction of the compressive stress and the n-channel is formed in the direction of the tensile stress. Thereby, the mobilities of holes and electrons are increased, and the current driving capability can be improved.
[0048]
In the semiconductor device 20 according to the second embodiment of the present invention, the n-channel is formed in the <100> direction or the <110> direction in the surface of the SiGe layer 22 on the side wall SW that becomes the (100) plane or the (110) plane. Except for manufacturing by doping and processing impurities so as to form a p-channel in the <001> direction, the semiconductor device 10 can be manufactured by substantially the same method as the manufacturing method of the semiconductor device 10 of the above-described first embodiment. Detailed description is omitted.
[0049]
In the above description, the case where SiGe is used as the substrate or a film having a different lattice constant from the substrate material has been described. However, the present invention is not limited to this, and SiGeC or the like may be used as the film.
[0050]
(Supplementary Note 1) In a semiconductor device including complementary field-effect transistors,
A p-type field effect transistor forming a first channel in which holes move in the direction of compressive stress of a film made of a material having a different lattice constant from the substrate or the substrate material;
An n-type field effect transistor forming a second channel through which electrons move in the direction of the tensile stress of the film;
A semiconductor device comprising:
[0051]
(Supplementary Note 2) The first channel and the second channel, wherein one is formed in an in-plane direction of the film, and the other is formed in a direction perpendicular to the surface of the film. 13. The semiconductor device according to claim 1.
[0052]
(Supplementary Note 3) The p-type field-effect transistor includes a silicon germanium layer having the (001) plane as a main surface laminated on a silicon substrate having the (001) plane as a main surface as the substrate. Forming the first channel in either the <100> direction or the <010> direction,
The n-type field effect transistor forms the second channel in a <001> direction on a (100) plane of the silicon germanium layer or a side wall surface equivalent to the (100) plane;
The p-type field effect transistor and the n-type field effect transistor are connected by respective sources or drains, and have a common gate.
2. The semiconductor device according to claim 1, wherein:
[0053]
(Supplementary Note 4) In the p-type field-effect transistor, a silicon germanium layer having the (001) plane as a main surface laminated on a silicon substrate having the (001) plane as a main surface as the substrate is provided. Forming the first channel in either the <110> direction or the <−110>direction;
In the n-type field effect transistor, the second channel is formed in a <001> direction on a surface of a side wall surface serving as a (110) plane or a (-110) plane of the silicon germanium layer,
The p-type field effect transistor and the n-type field effect transistor are connected by respective sources or drains, and have a common gate.
2. The semiconductor device according to claim 1, wherein:
[0054]
(Supplementary Note 5) The p-type field-effect transistor is a silicon germanium layer having a (001) plane as a main surface laminated on a germanium substrate having a (001) plane as a main surface as the substrate. Forming the first channel in the <001> direction on a side wall surface which is a (100) plane or a plane equivalent thereto,
The n-type field effect transistor forms the second channel in the silicon germanium layer in either a <100> direction or a <010> direction,
The p-type field effect transistor and the n-type field effect transistor are connected by respective sources or drains, and have a common gate.
2. The semiconductor device according to claim 1, wherein:
[0055]
(Supplementary Note 6) The p-type field-effect transistor is formed by stacking a silicon germanium layer having the (001) plane as a main surface laminated on a germanium substrate having the (001) plane as a main surface as the substrate. Forming the first channel in the <001> direction on a side wall surface to be a (110) plane or a (−110) plane;
The n-type field-effect transistor forms the second channel in the silicon germanium layer in either a <110> direction or a <-110> direction,
The p-type field effect transistor and the n-type field effect transistor are connected by respective sources or drains, and have a common gate.
2. The semiconductor device according to claim 1, wherein:
[0056]
(Supplementary Note 7) The semiconductor device according to supplementary note 1, wherein a source or a drain of the p-type field-effect transistor and a source or a drain of the n-type field-effect transistor are shared by one contact hole.
[0057]
(Supplementary Note 8) In a method of manufacturing a semiconductor device including complementary field-effect transistors,
Forming a film made of a material having a different lattice constant from the substrate or the substrate material on a substrate or a substrate material,
Forming a p-type field-effect transistor that forms a first channel in which holes move in the direction of compressive stress of the film among strains caused by the difference in lattice constant;
Creating an n-type field effect transistor forming a second channel in which electrons move in the direction of the tensile stress of the film;
A method for manufacturing a semiconductor device, comprising:
[0058]
(Supplementary Note 9) The one of the first channel and the second channel is formed in the in-plane direction of the film, and the other is formed in the direction perpendicular to the surface of the film. The manufacturing method of the semiconductor device described in the above.
[0059]
(Supplementary Note 10) The gate electrode of the p-type field-effect transistor and the gate electrode of the n-type field-effect transistor are formed simultaneously by deposition of silicon and thermal oxidation or chemical vapor deposition of an insulator. The manufacturing method of the semiconductor device described in the above.
[0060]
【The invention's effect】
As described above, in the present invention, a p-type field effect transistor that forms a p-channel in the direction of compressive stress of a substrate or a film made of a material having a different lattice constant from the substrate material, and the direction of tensile stress of the film Since the n-type field effect transistor that forms the second channel through which electrons move is formed, the mobility of holes and electrons is improved, and the current driving capability of the complementary field effect transistor can be improved. Further, since the n-type and p-type field effect transistors are formed using a common film, they can be manufactured by an easy process.
[0061]
In addition, by forming one field-effect transistor in the vertical direction, the gate length can be formed to be about several nm by controlling the film thickness without depending on the existing lithography technology, and the degree of integration is improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A and 2B are diagrams showing an equal energy surface of a conduction band lower end (valley) in a wavenumber space (K space) of a MOSFET, where FIG. 2A is a three-dimensional view, FIG. 2B is a <001> direction projection view, and FIG. C) is a projection view in the <100> direction.
3A and 3B are diagrams illustrating a level difference between valleys of Si and strained SiGe caused by two-dimensional quantization of channel electrons. FIG. 3A illustrates two-dimensional quantization in the <001> direction, and FIG. It is a figure which shows the valley level difference at the time of performing two-dimensional quantization in 100> direction.
FIG. 4 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 7 is a sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 10 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 11 is a cross-sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 12 is a sectional view of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 13 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.
[Explanation of symbols]
1 Si substrate
2 SiGe layer
2a, 2b, 5a, 5b Drain or source region
2c channel area
3 Oxide film
3a, 3b Gate oxide film
4a, 4b Gate electrode
6 Insulating film
7a, 7b, 7c, 7d, 7e, 7f Wiring
10 Semiconductor device
10a PMOSFET
10b NMOSFET
tr1, tr2 trench
SW side wall

Claims (5)

In a semiconductor device including complementary field-effect transistors,
A p-type field effect transistor forming a first channel in which holes move in the direction of compressive stress of a film made of a material having a different lattice constant from a substrate;
A semiconductor device comprising: an n-type field effect transistor forming a second channel through which electrons move in a direction of tensile stress of the film. 2. The semiconductor according to claim 1, wherein one of the first channel and the second channel is formed in an in-plane direction of the film, and the other is formed in a direction perpendicular to the surface of the film. apparatus. The p-type field-effect transistor is formed by stacking a silicon germanium layer having the (001) plane as a main surface laminated on a silicon substrate having the (001) plane as a main surface as the first substrate. Channel is formed in either the <100> direction or the <110> direction,
The n-type field effect transistor forms the second channel in a <001> direction on a (100) plane of the silicon germanium layer or a side wall surface equivalent to the (100) plane;
2. The semiconductor device according to claim 1, wherein the p-type field effect transistor and the n-type field effect transistor are connected by respective sources or drains, and have a common gate. (100) The p-type field effect transistor is a (100) silicon germanium layer having the (001) plane as a main surface laminated on a germanium substrate having the (001) plane as a main surface as the substrate. Forming the first channel in the <001> direction on a surface or a side wall surface which is an equivalent surface thereof;
The n-type field-effect transistor forms the second channel in the silicon germanium layer in either a <100> direction or a <110>direction;
2. The semiconductor device according to claim 1, wherein the p-type field effect transistor and the n-type field effect transistor are connected by respective sources or drains, and have a common gate. In a method of manufacturing a semiconductor device including complementary field-effect transistors,
Forming a film made of a material having a different lattice constant from the substrate on the substrate,
Forming a p-type field-effect transistor that forms a first channel in which holes move in the direction of compressive stress of the film among strains caused by the difference in lattice constant;
Creating an n-type field effect transistor forming a second channel in which electrons move in the direction of the tensile stress of the film;
A method for manufacturing a semiconductor device, comprising:

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