JP2005012087A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005012087A
JP2005012087A JP2003176527A JP2003176527A JP2005012087A JP 2005012087 A JP2005012087 A JP 2005012087A JP 2003176527 A JP2003176527 A JP 2003176527A JP 2003176527 A JP2003176527 A JP 2003176527A JP 2005012087 A JP2005012087 A JP 2005012087A
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Prior art keywords
layer
region
semiconductor device
semiconductor substrate
element region
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Japanese (ja)
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Tomoya Sanuki
朋也 佐貫
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Toshiba Corp
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Toshiba Corp
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Priority to JP2003176527A priority Critical patent/JP2005012087A/en
Priority to US10/804,206 priority patent/US7019380B2/en
Publication of JP2005012087A publication Critical patent/JP2005012087A/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve an element formed on a semiconductor substrate by generating tensile strain on the semiconductor substrate. <P>SOLUTION: An Si layer of an SOI substrate forms a trench on a region separating an element, and forms an element separation region by burying SiN larger than a thermal expansion coefficient of Si as an insulation material in the trench. At an ordinary temperature, tensile directional stress is generated on the element region by contracting the element separation region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は、ＭＯＳ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）型半導体装置に係わり、特にＭＯＳ型半導体装置の素子分離領域の構成に関する。
【０００２】
【従来の技術】
ＭＯＳトランジスタの電流駆動能力等の性能を向上するために、半導体基板に歪みＳｉ層を備え、この歪みＳｉ層にＭＯＳトランジスタを形成する開発が進められている。
【０００３】
この歪みＳｉ層は、Ｓｉに引っ張り歪みを印加することで、Ｓｉのバンド構造を変化させている。歪みＳｉ層の形成方法としては、Ｓｉに十分大きな歪みを加えるために、Ｓｉより格子定数の大きい例えばＳｉＧｅ層を半導体基板に形成し、この上にＳｉ層を結晶成長させることで歪みＳｉを形成する。このように形成された歪みＳｉ層に、例えばＭＯＳトランジスタを形成した場合、キャリアとしての電子或いはホールの移動度を高めることができる。
【０００４】
例えば、上記歪みＳｉ層にゲート長が２０〜３０［ｎｍ］のＭＯＳトランジスタを形成した場合、電流駆動能力の向上率は２０〜３０％と言われている（非特許文献１、非特許文献２参照）。
【０００５】
【非特許文献１】
Ｋ．Ｒｉｍ ｅｔ ａｌ．，ＶＬＳＩ Ｓｙｍｐ．，２００１年，ｐ．５９
【０００６】
【非特許文献２】
Ｋ．Ｒｉｍ ｅｔ ａｌ．，ＶＬＳＩ Ｓｙｍｐ．，２００２年，ｐ．９８
【０００７】
【発明が解決しようとする課題】
ところが、Ｓｉに替えて歪みＳｉを用いる場合、例えばＳｉ層とＳｉＧｅ層との整合性が悪いことにより欠陥や転移が発生してしまう。さらに、製造工程において半導体基板に熱処理を行うと、歪んでいたＳｉの格子結晶が元に戻ってしまうという問題がある。
【０００８】
本発明は、上記のような事情に鑑みてなされたもので、簡単かつ低コストで半導体基板に引っ張り歪みを発生させることができ、これにより上記半導体基板に形成される素子の性能の向上が可能な半導体装置を提供することを目的とする。
【０００９】
【課題を解決するための手段】
上記目的を達成するために本発明は、半導体基板と、前記半導体基板内に形成され、ゲート電極を有するソース／ドレイン領域としての素子領域と、前記素子領域の周囲に形成され、熱膨張係数が前記素子領域の熱膨張係数より大きい絶縁体材料からなる素子分離領域とを具備することを特徴とする。
【００１０】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。
【００１１】
（第１の実施形態）
図１は、本発明の第１の実施形態における半導体基板に形成されたＭＯＳトランジスタの主要部を示す平面図である。なお、上記半導体基板は、例えばＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）基板により構成される。図２は、図１に示したＳＯＩ基板における２−２線に沿った方向の断面図である。
【００１２】
ＳＯＩ基板は、Ｓｉ基板４、ＳｉＯ２などの絶縁体層５、Ｓｉ層６を積層して形成される。このＳＯＩ基板は、例えばＳＩＭＯＸ（Ｓｅｐａｒａｔｉｏｎ ｂｙ Ｉｍｐｌａｎｔｅｄ ＯＸｙｇｅｎ）により形成される。
【００１３】
ＳＯＩ基板のＳｉ層６内に絶縁体層５に達するトレンチＴＲを形成し、このトレンチＴＲ内に絶縁体材料としてＳｉＮを埋め込んで素子分離領域１を形成する。この素子分離領域１は、例えばＳｉＮをプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）により形成する。これにより素子分離領域１の内側に素子領域２が形成される。この素子領域２にはＭＯＳトランジスタが形成される。
【００１４】
すなわち、素子領域２には、ゲート絶縁膜７を介して例えばポリシリコンからなるゲート電極３が形成される。ゲート電極３の両側には、側壁が形成されている。さらに、ゲート電極３の両側には、ソース及びドレイン領域Ｓ／Ｄが形成される。これらソース及びドレイン領域Ｓ／Ｄは、素子領域内に例えば不純物イオンを注入することにより形成される。また、ソース及びドレイン領域には、コンタクトとなる電極（図示せず）が形成され、この電極に図示せぬ配線が接続される。また、素子分離領域１の外側には、例えば他の素子領域６が形成される。図２は、完全空乏型のトランジスタを示しているが、素子領域に形成されるトランジスタは、これに限らず、部分空乏型であってもよい。
【００１５】
素子分離領域１の材料ＳｉＮは、素子領域２の材料Ｓｉより熱膨張係数が大きい。このため、例えば熱処理によりトレンチにＳｉＮを埋め込んだ後、半導体基板の温度が室温まで低下すると、素子分離領域１は素子領域２に比べてより大きく収縮する。このため、素子領域２には、素子分離領域１から引っ張り方向の応力が生じる。
【００１６】
以上詳述したように第１の実施形態では、ＳＯＩ基板のＳｉ層に、Ｓｉよりも熱膨張係数が大きいＳｉＮを用いて素子分離領域を形成している。
【００１７】
したがって本実施形態によれば、素子領域２に対して、素子分離領域１から引っ張り方向の応力を生じさせることができる。よって、素子領域２が伸張することで、素子領域２ａに形成されたＭＯＳトランジスタのキャリアの移動度を向上させることができる。
【００１８】
（第２の実施形態）
第２の実施形態は、素子分離領域を、素子領域に接する第１の層と、この第１の層の内側に形成された第２の層との２層で構成する。第１の層には、絶縁性の材料を用い、上記第２の層には金属等の熱膨張係数が大きい材料を用いて半導体装置を形成する。
【００１９】
図３は、本発明の第２の実施形態における半導体基板に形成されたＭＯＳトランジスタの主要部を示す平面図である。上記半導体基板は、例えばＳＯＩ基板により構成される。図４は、図１に示したＳＯＩ基板における４−４線に沿った方向の断面図である。なお、ＳＯＩ基板の構成と、素子領域に形成されるＭＯＳトランジスタの構成とは、上記第１の実施形態で示した構成と同様であるため説明は省略する。
【００２０】
ＳＯＩ基板のＳｉ層６ａ内に絶縁体層５に達するトレンチＴＲを形成し、このトレンチＴＲ内に素子分離領域を形成する。この素子分離領域は、素子領域２ａに接する第１の層と、この第１の層の内側の第２の層との２層で構成される。素子領域２ａに接する第１の層は、例えば絶縁性材料としてのＳｉＮにより形成される。このＳｉＮ層１０は、例えばプラズマＣＶＤ、或いはＬＰ−ＣＶＤ（Ｌｏｗ Ｐｒｅｓｕｒｅ − Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）により形成される。
【００２１】
ＳｉＮ層１０の内側に第２の層としての例えば金属層１１が形成される。この金属層１１は、例えばＡｌ、Ｃｕ、ＴｉＮ、Ｔｉ、Ｗ、ＴａＮ、Ｃｏ、Ｎｉ等の金属系の材料により形成される。
【００２２】
素子分離領域を構成するＳｉＮ層１０及び金属層１１は、素子領域２ａの材料Ｓｉより熱膨張係数が大きい。このため、例えば熱処理によりＳｉＮ層１０及び金属層１１を埋め込んだ後、半導体基板の温度が室温まで低下すると、ＳｉＮ層１０及び金属層１１は素子領域２ａに比べてより大きく収縮する。このため、素子領域２ａには、素子分離領域から引っ張り方向の応力が生じる。
【００２３】
したがって本実施形態によれば、素子領域２ａに対して、素子分離領域を形成するＳｉＮ層１０から引っ張り方向の応力を生じさせることができる。よって、素子領域２ａが伸張することで、素子領域２ａに形成されたＭＯＳトランジスタのキャリアの移動度を向上させることができる。
【００２４】
さらに、素子分離領域に素子領域の材料より熱膨張係数が大きい金属層１１を形成し、この金属層１１の収縮により、素子領域２ａに対して引っ張り方向の応力を生じさせている。よって、素子領域２ａが伸張することで、素子領域２ａに形成されたＭＯＳトランジスタのキャリアの移動度を向上させることができる。
【００２５】
上記第２の実施形態では、ＳｉＮ層１０の内側に金属系の材料を用いて第２の層を形成している。しかし、第２の層はこれに限らず、例えばサリサイド系のＴｉＳｉ、ＴｉＳｉ２、ＣｏＳｉ、ＣｏＳｉ２、ＮｉＳｉ、ＮｉＳｉ２で構成してもよい。すなわち、素子領域２ａの材料であるＳｉより熱膨張係数が大きい材料であれば同様に適用可能である。
【００２６】
また上記第２の実施形態では、素子領域２ａに接する第１の層にＳｉＮを用いている。しかし、絶縁材料として、例えばＴＥＯＳ等のＳｉＯ２を用いてもよい。
【００２７】
さらに、上記第１、第２の実施形態において、素子領域に形成されるトランジスタの導電型は、Ｐチャネル、Ｎチャネルのいずれでもよく、ＰチャネルＭＯＳトランジスタ、ＮチャネルＭＯＳトランジスタの電流駆動能力を向上させることができる。
【００２８】
さらに、上記第１、第２の実施形態において、半導体基板としてＳＯＩ基板を用いる場合について説明している。しかし、半導体基板としてバルクを用いてもよい。この場合、トレンチの深さを変えることで素子領域に発生させる引っ張り方向の応力を変化させることができる。
【００２９】
この発明は、上記実施形態に限定されるものではなく、その他、本発明の要旨を変更しない範囲において種々変形して実施可能なことは勿論である。
【００３０】
【発明の効果】
以上詳述したようにこの発明によれば、簡単かつ低コストで半導体基板に引っ張り歪みを発生させることができ、これにより上記半導体基板に形成される素子の性能の向上が可能な半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態における半導体基板に形成されたＭＯＳトランジスタの主要部を示す平面図。
【図２】図１に示したＳＯＩ基板における２−２線に沿った方向の断面図。
【図３】本発明の第２の実施形態における半導体基板に形成されたＭＯＳトランジスタの主要部を示す平面図。
【図４】図３に示したＳＯＩ基板における４−４線に沿った方向の断面図。
【符号の説明】
１…素子分離領域、２，２ａ…素子領域、３，３ａ…ゲート電極、４，４ａ…Ｓｉ基板、５，５ａ…絶縁体層、６，６ａ…他の素子領域、７，７ａ…ゲート絶縁膜、１０…ＳｉＮ層、１１…金属層、ＴＲ…トレンチ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS (Metal Oxide Semiconductor) type semiconductor device, and more particularly to a configuration of an element isolation region of a MOS type semiconductor device.
[0002]
[Prior art]
In order to improve the performance of the MOS transistor, such as current drive capability, a development is underway in which a strained Si layer is provided on a semiconductor substrate and a MOS transistor is formed on the strained Si layer.
[0003]
The strained Si layer changes the Si band structure by applying tensile strain to Si. As a method for forming a strained Si layer, in order to apply a sufficiently large strain to Si, for example, a SiGe layer having a lattice constant larger than that of Si is formed on a semiconductor substrate, and a Si layer is grown on this to form strained Si. To do. When, for example, a MOS transistor is formed in the strained Si layer thus formed, the mobility of electrons or holes as carriers can be increased.
[0004]
For example, when a MOS transistor having a gate length of 20 to 30 [nm] is formed in the strained Si layer, the improvement rate of current driving capability is said to be 20 to 30% (Non-Patent Document 1, Non-Patent Document 2). reference).
[0005]
[Non-Patent Document 1]
K. Rim et al. , VLSI Symp. , 2001, p. 59
[0006]
[Non-Patent Document 2]
K. Rim et al. , VLSI Symp. , 2002, p. 98
[0007]
[Problems to be solved by the invention]
However, when strained Si is used instead of Si, for example, defects and transition occur due to poor matching between the Si layer and the SiGe layer. Furthermore, when the semiconductor substrate is heat-treated in the manufacturing process, there is a problem that the strained Si lattice crystal is restored.
[0008]
The present invention has been made in view of the above circumstances, and can generate tensile strain in a semiconductor substrate easily and at low cost, thereby improving the performance of an element formed on the semiconductor substrate. An object of the present invention is to provide a simple semiconductor device.
[0009]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a semiconductor substrate, an element region formed in the semiconductor substrate as a source / drain region having a gate electrode, and formed around the element region, and has a thermal expansion coefficient. And an element isolation region made of an insulating material larger than the thermal expansion coefficient of the element region.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0011]
(First embodiment)
FIG. 1 is a plan view showing a main part of a MOS transistor formed on a semiconductor substrate in the first embodiment of the present invention. The semiconductor substrate is constituted by, for example, an SOI (Silicon On Insulator) substrate. FIG. 2 is a cross-sectional view of the SOI substrate shown in FIG. 1 in the direction along line 2-2.
[0012]
The SOI substrate is formed by laminating an Si substrate 4, an insulator layer 5 such as SiO 2, and an Si layer 6. This SOI substrate is formed by, for example, SIMOX (Separation by Implanted Oxygen).
[0013]
A trench TR reaching the insulator layer 5 is formed in the Si layer 6 of the SOI substrate, and an element isolation region 1 is formed by embedding SiN as an insulator material in the trench TR. In the element isolation region 1, for example, SiN is formed by plasma CVD (Chemical Vapor Deposition). Thereby, the element region 2 is formed inside the element isolation region 1. In this element region 2, a MOS transistor is formed.
[0014]
That is, a gate electrode 3 made of, for example, polysilicon is formed in the element region 2 via the gate insulating film 7. Side walls are formed on both sides of the gate electrode 3. Furthermore, source and drain regions S / D are formed on both sides of the gate electrode 3. These source and drain regions S / D are formed, for example, by implanting impurity ions into the element region. Further, an electrode (not shown) to be a contact is formed in the source and drain regions, and a wiring (not shown) is connected to this electrode. Further, for example, another element region 6 is formed outside the element isolation region 1. Although FIG. 2 shows a fully depleted transistor, the transistor formed in the element region is not limited to this and may be a partially depleted transistor.
[0015]
The material SiN of the element isolation region 1 has a larger thermal expansion coefficient than the material Si of the element region 2. For this reason, for example, when the temperature of the semiconductor substrate is lowered to room temperature after SiN is buried in the trench by heat treatment, the element isolation region 1 contracts more than the element region 2. For this reason, in the element region 2, a tensile stress is generated from the element isolation region 1.
[0016]
As described above in detail, in the first embodiment, the element isolation region is formed in the Si layer of the SOI substrate using SiN having a thermal expansion coefficient larger than that of Si.
[0017]
Therefore, according to the present embodiment, stress in the pulling direction from the element isolation region 1 can be generated in the element region 2. Therefore, the expansion of the element region 2 can improve the carrier mobility of the MOS transistor formed in the element region 2a.
[0018]
(Second Embodiment)
In the second embodiment, the element isolation region is composed of two layers: a first layer in contact with the element region and a second layer formed inside the first layer. An insulating material is used for the first layer, and a semiconductor device is formed using a material having a large coefficient of thermal expansion such as a metal for the second layer.
[0019]
FIG. 3 is a plan view showing the main part of the MOS transistor formed on the semiconductor substrate according to the second embodiment of the present invention. The semiconductor substrate is composed of, for example, an SOI substrate. 4 is a cross-sectional view in the direction along line 4-4 of the SOI substrate shown in FIG. Note that the configuration of the SOI substrate and the configuration of the MOS transistor formed in the element region are the same as the configuration shown in the first embodiment, and a description thereof will be omitted.
[0020]
A trench TR reaching the insulator layer 5 is formed in the Si layer 6a of the SOI substrate, and an element isolation region is formed in the trench TR. This element isolation region is composed of two layers, a first layer in contact with the element region 2a and a second layer inside the first layer. The first layer in contact with the element region 2a is formed of, for example, SiN as an insulating material. The SiN layer 10 is formed by, for example, plasma CVD or LP-CVD (Low Pre-Chemical Vapor Deposition).
[0021]
For example, a metal layer 11 as a second layer is formed inside the SiN layer 10. The metal layer 11 is formed of a metal-based material such as Al, Cu, TiN, Ti, W, TaN, Co, or Ni.
[0022]
The SiN layer 10 and the metal layer 11 constituting the element isolation region have a thermal expansion coefficient larger than that of the material Si of the element region 2a. For this reason, for example, when the temperature of the semiconductor substrate is lowered to room temperature after the SiN layer 10 and the metal layer 11 are embedded by heat treatment, the SiN layer 10 and the metal layer 11 contract more greatly than the element region 2a. For this reason, stress in the tensile direction is generated from the element isolation region in the element region 2a.
[0023]
Therefore, according to this embodiment, stress in the tensile direction can be generated from the SiN layer 10 forming the element isolation region in the element region 2a. Therefore, the expansion of the element region 2a can improve the carrier mobility of the MOS transistor formed in the element region 2a.
[0024]
Furthermore, a metal layer 11 having a thermal expansion coefficient larger than that of the material of the element region is formed in the element isolation region. Due to the shrinkage of the metal layer 11, a tensile stress is generated on the element region 2a. Therefore, the expansion of the element region 2a can improve the carrier mobility of the MOS transistor formed in the element region 2a.
[0025]
In the second embodiment, the second layer is formed using a metal material inside the SiN layer 10. However, the second layer is not limited thereto, and may be composed of, for example, salicide-based TiSi, TiSi 2 , CoSi, CoSi 2 , NiSi, or NiSi 2 . That is, any material having a larger thermal expansion coefficient than Si, which is the material of the element region 2a, can be similarly applied.
[0026]
In the second embodiment, SiN is used for the first layer in contact with the element region 2a. However, for example, SiO 2 such as TEOS may be used as the insulating material.
[0027]
Furthermore, in the first and second embodiments, the conductivity type of the transistor formed in the element region may be either P-channel or N-channel, and the current drive capability of the P-channel MOS transistor and N-channel MOS transistor is improved. Can be made.
[0028]
Furthermore, in the first and second embodiments, the case where an SOI substrate is used as the semiconductor substrate has been described. However, a bulk may be used as the semiconductor substrate. In this case, the tensile stress generated in the element region can be changed by changing the depth of the trench.
[0029]
The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the scope of the present invention.
[0030]
【The invention's effect】
As described above in detail, according to the present invention, there is provided a semiconductor device capable of generating tensile strain in a semiconductor substrate easily and at low cost, and thereby improving the performance of elements formed on the semiconductor substrate. can do.
[Brief description of the drawings]
FIG. 1 is a plan view showing a main part of a MOS transistor formed on a semiconductor substrate according to a first embodiment of the present invention.
2 is a cross-sectional view in the direction along line 2-2 in the SOI substrate shown in FIG. 1;
FIG. 3 is a plan view showing a main part of a MOS transistor formed on a semiconductor substrate according to a second embodiment of the present invention.
4 is a cross-sectional view in the direction along line 4-4 in the SOI substrate shown in FIG. 3;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Element isolation region, 2, 2a ... Element region, 3, 3a ... Gate electrode, 4, 4a ... Si substrate, 5, 5a ... Insulator layer, 6, 6a ... Other element regions, 7, 7a ... Gate insulation Membrane, 10 ... SiN layer, 11 ... metal layer, TR ... trench.

Claims (12)

半導体基板と、
前記半導体基板の素子領域の周囲に形成され、熱膨張係数が前記素子領域の熱膨張係数より大きい絶縁体材料からなる素子分離領域と
を具備することを特徴とする半導体装置。A semiconductor substrate;
A semiconductor device comprising: an element isolation region formed around an element region of the semiconductor substrate and made of an insulating material having a thermal expansion coefficient larger than that of the element region. 前記半導体基板は、ＳＯＩ構造からなることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the semiconductor substrate has an SOI structure. 前記素子分離領域は、ＳｉＮからなることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the element isolation region is made of SiN. 前記素子分離領域は、前記素子領域の周囲に形成されたトレンチと、前記トレンチ内に形成された前記ＳｉＮ層とからなることを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the element isolation region includes a trench formed around the element region and the SiN layer formed in the trench. 半導体基板と、
前記半導体基板の素子領域の周囲に形成され、前記素子領域に接する面に絶縁体からなる第１の層を有し、前記第１の層の内側に熱膨張係数が前記素子領域の熱膨張係数より大きい伝導体材料からなる第２の層を有する素子分離領域と
を具備することを特徴とする半導体装置。A semiconductor substrate;
The semiconductor substrate has a first layer formed of an insulator on a surface in contact with the element region, the thermal expansion coefficient of the element region being within the first layer. And a device isolation region having a second layer made of a larger conductor material. 前記半導体基板は、ＳＯＩ構造からなることを特徴とする請求項５に記載の半導体装置。The semiconductor device according to claim 5, wherein the semiconductor substrate has an SOI structure. 前記伝導体材料は、金属からなることを特徴とする請求項５に記載の半導体装置。The semiconductor device according to claim 5, wherein the conductor material is made of metal. 前記伝導体材料は、Ａｌ、Ｃｕ、ＴｉＮ、Ｔｉ、Ｗ、ＴａＮ、Ｃｏ、Ｎｉのいずれか１つからなることを特徴とする請求項７に記載の半導体装置。The semiconductor device according to claim 7, wherein the conductor material is made of any one of Al, Cu, TiN, Ti, W, TaN, Co, and Ni. 前記伝導体材料は、サリサイド系の材料からなることを特徴とする請求項５に記載の半導体装置。The semiconductor device according to claim 5, wherein the conductor material is a salicide-based material. 前記伝導体材料は、ＴｉＳｉ、ＴｉＳｉ２、ＣｏＳｉ、ＣｏＳｉ２、ＮｉＳｉ、ＮｉＳｉ２のいずれか１つからなることを特徴とする請求項９に記載の半導体装置。The semiconductor device according to claim 9, wherein the conductor material is made of any one of TiSi, TiSi 2 , CoSi, CoSi 2 , NiSi, and NiSi 2 . 前記絶縁体は、ＳｉＮからなることを特徴とする請求項５に記載の半導体装置。The semiconductor device according to claim 5, wherein the insulator is made of SiN. 前記素子分離領域は、前記素子領域の周囲に形成されたトレンチと、前記トレンチの内面に形成された前記ＳｉＮからなる第１の層と、前記第１の層の内側に形成された前記伝導体材料ことを特徴とする請求項１１に記載の半導体装置。The element isolation region includes a trench formed around the element region, a first layer made of SiN formed on the inner surface of the trench, and the conductor formed inside the first layer. The semiconductor device according to claim 11, wherein the material is a material.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007142429A (en) * 2005-11-21 2007-06-07 Internatl Business Mach Corp <Ibm> Transistor having dielectric stressor elements to apply shearing stress at different depths from semiconductor surface
JP2007184418A (en) * 2006-01-06 2007-07-19 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2010123633A (en) * 2008-11-17 2010-06-03 Toshiba Corp Semiconductor device
KR101037451B1 (en) * 2005-01-15 2011-05-26 어플라이드 머티어리얼스, 인코포레이티드 Substrate having silicon germanium material and stressed silicon nitride layer
JP2013008992A (en) * 2012-08-27 2013-01-10 Sony Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101037451B1 (en) * 2005-01-15 2011-05-26 어플라이드 머티어리얼스, 인코포레이티드 Substrate having silicon germanium material and stressed silicon nitride layer
JP2007142429A (en) * 2005-11-21 2007-06-07 Internatl Business Mach Corp <Ibm> Transistor having dielectric stressor elements to apply shearing stress at different depths from semiconductor surface
JP2007184418A (en) * 2006-01-06 2007-07-19 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2010123633A (en) * 2008-11-17 2010-06-03 Toshiba Corp Semiconductor device
JP2013008992A (en) * 2012-08-27 2013-01-10 Sony Corp Semiconductor device

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