JP2003092399A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the configuration and maintenance of an exclusive manufacturing line leads to financial burden since it is necessary to install a semiconductor manufacturing line using different kinds of materials such as Ge separately from a normal silicon semiconductor manufacturing line when elements which are unwelcome to the normal silicon semiconductor element manufacturing line are included in the manufacturing process of a semiconductor element including Ge or C. SOLUTION: A semiconductor including different kinds of materials such as Ge or C is formed only in a channel region where the performance of a semiconductor element is decided by a selective epitaxial technology, and the traveling time of a carrier is shortened so that the high performance of the semiconductor element can be realized. At the same time, the different kinds of materials such as Ge or C are not used outside the channel region so that the possibility of the mutual contamination of Ge or C outside the channel region or a gate insulating film formation process can be minimized. Thus, it is possible to provide a high performance and economical semiconductor element by sharing a normal silicon semiconductor manufacturing line in a plurality of semiconductor manufacturing devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which functions as a MISFET having an active region formed by epitaxial growth.

[0002]

2. Description of the Related Art A semiconductor element represented by a MOSFET using a silicon semiconductor is integrated on one substrate and can provide various functions. Therefore, as represented by a computer, it is no longer used in daily life. It is becoming essential. The speed of technological progress of this silicon semiconductor is remarkable, and even now, there is a demand for higher performance and lower cost integrated circuits.

One of the effective means for improving the performance of the integrated circuit is to improve the performance of the semiconductor element itself, and up to now, the miniaturization of the semiconductor element has achieved higher performance and lower cost. However, the rate of performance improvement due to miniaturization has slowed down, and it is becoming more promising to increase the moving speed of carriers in a silicon crystal as one of the means for the next higher performance.

Movement speed of carriers in the silicon crystal
As a method of increasing the value, disclosed in Japanese Patent Laid-Open No. 10-214906.
As described above, Si is used as a channel material for semiconductor devices.
_1-XGe _X(0 ≦ X ≦ 1) or Si_1-XYGe_XC_Y(0 ≦ X + Y ≦ 1) etc.
Method using seed semiconductor material and Japanese Patent Laid-Open No. 09-082944
As disclosed in,_1-XGe _X
Introduce a material to strain the crystal in the channel region of a semiconductor device
There is a way to get it.

As a conventional technique, a method using the selective epitaxial method will be specifically described with reference to FIG.

FIG. 1A shows a MOSF having a Si _1-X Ge _X channel region formed by a conventional selective epitaxial method.
The cross-sectional structure of ET is shown. As shown in FIG.
An element isolation oxide film 2 made of LOCOS isolation or trench isolation for electrical insulation from other elements is formed on the surface of the silicon substrate 1. On the silicon substrate 1, a selective epitaxial portion 101 made of SiGe is formed in a portion not covered with the element isolation oxide film 2. A gate insulating film 10 is formed on a part of the selective epitaxial region 101, and a gate polysilicon 11 is formed on the gate insulating film 10. A sidewall protection film 15 is formed around the gate polysilicon 11, and impurity-doped source / drain portions 14 are formed in the selective epitaxial portions 101 on both sides of the sidewall protection film 15. Immediately below the sidewall protective film 15, an extension portion 12 which is a junction shallower than the source / drain portion 14 is formed in order to improve the performance of the transistor. Gate polysilicon 11
Also, a silicide metal such as titanium silicide or cobalt silicide is formed on the source / drain portion 14 in order to reduce the parasitic resistance of the transistor. The interlayer insulating film 1 is formed so as to cover the upper part of this transistor.
7 is formed, a tungsten plug 18 and a metal wiring 19 are formed in order to draw out electrodes from the source, drain and gate of the transistor.

In the transistor manufacturing method by the selective epitaxial method, after the element isolation oxide film 2 is formed on the semiconductor substrate 1, Si _1-X Ge _X is formed in the active region of the element by the selective epitaxial method as shown in FIG. 1B. Etc. to grow crystals. After this crystal growth, a gate insulating film forming step, a gate pattern forming step, an extension forming step, a sidewall protective film forming step, a source / drain forming step, a salicide forming step, an interlayer insulating film forming step, a tungsten plug forming step, a metal wiring Each process is performed in the order of the forming process.

[0008]

However, in the semiconductor device as described above, the Si _{1-
Since the X} Ge _X crystal is formed, the steps from the gate insulating film forming step to the source / drain forming step in the MOSFET forming step are exposed to the problem of impurity contamination of silicon such as Ge.

In such a case, there arises a problem of cross-contamination of an unfavorable element such as Ge through the manufacturing apparatus used. For example, when Ge is mixed in the gate oxide film which is the gate insulating film, there is a concern that reliability failure such as a decrease in breakdown voltage and a decrease in life may occur.

Therefore, such a method for improving the performance of a semiconductor device is considered to be an effective means, but it contains an element which is not desired to be introduced into a silicon semiconductor manufacturing line sensitive to impurity contamination, It is necessary to install a semiconductor manufacturing line that uses different materials such as Ge separately from a normal silicon semiconductor manufacturing line. However, it is economically burdensome to build, own, and maintain these manufacturing lines. Even if a pure silicon semiconductor element and a heterogeneous material semiconductor element such as Ge are partially produced using the same production apparatus, the economical advantage thereof is great.

In view of this point, an object of the present invention is to form a heterogeneous material such as Ge only in a specific portion of a semiconductor element to realize high performance of the semiconductor element and become a pollutant for a manufacturing line. Minimize exposure of dissimilar materials such as Ge,
It is to economically provide a high-performance semiconductor device by using the same manufacturing apparatus as a pure silicon semiconductor device in most of the steps.

[0012]

The semiconductor device of the present invention comprises:
A semiconductor substrate, an element isolation part provided in a part of the semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and the semiconductor substrate A source / drain region of the first conductivity type provided on both sides of the gate electrode and a region formed between the source / drain region of the semiconductor substrate by a selective epitaxial method. A channel region made of a first semiconductor, and the semiconductor substrate provided below the channel region.
A second conductivity type body region made of a second semiconductor having a larger potential for carriers at the band edge where the carriers run than the first semiconductor is provided.

In the semiconductor element of the present invention, a heterogeneous material such as Ge is formed only in the channel region that determines the performance of the semiconductor element, and the performance of the semiconductor element is improved by shortening the transit time of carriers. At the same time, since a heterogeneous material such as Ge is not used outside the channel region, it is possible to minimize the possibility of cross-contamination of Ge or the like except in the channel region and the gate insulating film forming step.

A method of manufacturing a semiconductor device according to the present invention comprises:
A step of forming an element isolation region on a semiconductor substrate, a step of forming a replacement gate insulating film, a step of etching a planned gate region of the replacement gate insulating film to form a channel opening, and a self-alignment through the channel opening. Forming a body region of the second conductivity type in which ions are implanted into the substrate and carriers travel more than the channel region and the potential for carriers at the band edge is large, and a heterogeneous material such as Ge is selectively epitaxially crystallized only in the channel opening. Growing, forming a channel region, forming a gate insulating film on the channel region, forming a gate conductive film on the gate insulating film, removing the replacement gate insulating film, extension A step of forming a sidewall portion, a step of forming a sidewall protective film, a step of forming a source / drain region, and Forming a side film includes a step of forming an interlayer insulating film, forming a tungsten plug, and forming a metal wiring.

According to the method of manufacturing a semiconductor device of the present invention,
Since the channel region is opened and the heterogeneous material such as Ge is crystal-grown only in the channel region, dedicated equipment is required for the crystal growth device and the gate insulating film forming device. No pollutant is formed, and common manufacturing equipment for pure silicon semiconductor devices can be used in common.

In addition, since the second conductivity type body region having a larger potential for carriers at the band edge where carriers travel than in the channel region can be formed by implanting ions in a self-aligned manner after opening the channel region, the channel region can be formed. In addition to enabling efficient carrier collection, a high-concentration second-conductivity-type region is not formed below the source / drain, so the parasitic capacitance between the source / drain-body can be reduced. The resistance of the body region can be reduced and the parasitic capacitance can be reduced at the same time, and the speed of the semiconductor element can be increased.

Further, since the channel region contains impurities at a concentration lower than that of the body region by a factor of 1/10 or less, an increase in threshold value is suppressed and impurity scattering is suppressed, so that carriers travel. The decrease in speed is suppressed.

Since the gate electrode is made of polysilicon or polysilicon germanium containing the first conductivity type impurity, a built-in potential is formed between the gate electrode and the channel region, which is suitable for confining carriers. A band structure is obtained. Further, when a low resistance material such as metal is used as the gate electrode, it is effective in increasing the speed of the semiconductor element. Therefore, it is preferable that the gate electrode is composed of polysilicon containing a first conductivity type impurity or a complex of polysilicon germanium and a metal.

The first semiconductor forming the channel region contains at least Si as a component element, and a part of the semiconductor layer is a region for preventing diffusion of impurities into the channel. By further including a region containing carbon in a concentration of 0.01% or more and 2% or less,
It is possible to obtain a semiconductor device in which diffusion of impurities from the body region containing a high concentration of impurities to the channel region is suppressed, and high-speed operation with less impurity scattering in the channel region is possible.

Since the first semiconductor is a semiconductor containing Si and Ge as constituent elements and the second semiconductor is Si, the band offset generated at the valence band edge of the first semiconductor pair is used. As a result, a channel region suitable for the p-channel in which the holes travel can be obtained.

By using a Si cap layer provided between the gate insulating film and the channel region, a region of the channel region in contact with a band offset generated between the cap layer and the channel region can be used as a channel. In addition, the gate insulating film can be formed of a silicon oxide film having good electric characteristics obtained by oxidizing the surface of the cap layer.

The source / drain regions are p-type source / source regions.
A drain region, the channel region is a p-channel channel region, the body region may be an n-type body region, the source / drain region is an n-type source / drain region, and the channel The region may be a channel region for n channel, and the body region may be a p-type body region. Then, by including these, a complementary transistor can be formed.

The first semiconductor is a semiconductor containing Si, Ge and C as constituent elements, and the second semiconductor is S.
Since i is i, a channel region that can be used as both an n-channel and a p-channel can be obtained by utilizing the band offsets of the conduction band edge and the valence band edge formed in the Si / SiGeC junction.

Although the description has been made based on the bulk substrate as the semiconductor substrate, the SOI (Silic
on On Insulator) substrate can also be used. In this case, a higher performance transistor can be provided.

Further, the transistor of the present invention is a DT-MOS (Dynamic Th) which requires a high-concentration body portion.
threshold MOSFET) and VT-MOS (Va
It is suitable for a high-performance circuit of a type in which the potential of the body is positively changed according to the operation of a circuit represented by a riable threshold MOSFET.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) In this embodiment, Si _1-X Ge _X (0
≦ X ≦ 1), an example of a MOSFET using a Si / Si _1-X Ge _X heterojunction will be described.

FIG. 2 shows a MOSFET according to this embodiment.
3 is a cross-sectional view schematically showing the structure of FIG. On the surface of the silicon substrate 1, LOCOS for electrical isolation from other elements
Element isolation oxide film 2 formed by isolation or trench isolation
Are formed. On a part of the silicon substrate 1, M
In the part that functions as the channel of OSFET, Si _{1- X} G
Selective epitaxial channel portion 9 made of a material containing e _X
Are formed. A gate insulating film 10 is formed on the selective epitaxial channel portion 9, and a gate polysilicon 11 is formed on the gate insulating film 10. A sidewall protection film 1 is formed around the gate polysilicon 11.
5 is formed, and source / drain portions 14 doped with impurities are formed on both sides of the sidewall protective film 15. Immediately below the sidewall protective film 15, an extension portion 12 which is a junction shallower than the source / drain portion 14 is formed in order to improve the performance of the transistor. A silicide portion 16 made of cobalt silicide is formed on the gate polysilicon 11 and the source / drain portion 14 in order to reduce the parasitic resistance of the transistor. The interlayer insulating film 1 is formed so as to cover the upper part of this transistor.
7 is formed, a tungsten plug 18 and a metal wiring 19 are formed in order to draw out electrodes from the source, drain and gate of the transistor.

3 (a)-(d) and FIG. 4 (e)-
(H) and FIGS. 5 (i) to (l) show the MO in the present embodiment.
It is the figure which showed the process cross section of SFET typically.

As shown in FIG. 3A, after the element isolation oxide film 2 which is an element isolation region is formed on the silicon substrate 1 by the LOCOS method or the trench method, the active area on the silicon substrate 1 is thermally oxidized to a thickness. A pad oxide film 4 made of a thermal oxide film having a thickness of 10 nm is formed, and a replacement nitride film 3 made of a silicon nitride film having a thickness of 200 nm is further formed on the element isolation oxide film 2 and the pad oxide film 4 by the LP-CVD method. Form. Replacement nitride film 3 in a region where a gate electrode will be formed in a later step by photolithography and dry etching
To remove. At this time, part of the replacement nitride film 3 is etched by dry etching, and the dry etching is automatically stopped by using the pad oxide film 4 as a stopper.

Next, as shown in FIG. 3B, a 50 keV dose amount of 2 × 10 is self-aligned with the entire surface of the silicon substrate 1.
Ion implantation of P is performed under the condition of ¹³ C / cm ⁻² to form a high concentration body portion 5 below the opening of the replacement nitride film 3. After that, annealing is performed at 850 ° C. for 30 minutes in a nitrogen atmosphere to carry out damage recovery of the silicon substrate 1 damaged by activation of the dopant and ion implantation.

Next, as shown in FIG. 3C, the pad oxide film 4 exposed in the opening of the replacement nitride film 3 is removed by etching to form a channel opening 6, and the silicon substrate 1 is exposed. Let Both dry etching and wet etching can be used for this etching, but wet etching is preferable because the replacement nitride film 3 is not affected by hydrofluoric acid.

Next, as shown in FIG. 3D, a heat treatment is performed in an oxidizing atmosphere to thermally oxidize the surface of the silicon substrate 1 exposed in the channel opening 6 by 60 nm to form a channel sacrificial oxide portion 7. To do. At this time, if the thickness of the channel sacrificial oxidation portion 7 is set to about 60 nm, the interface between the oxide film and silicon is located below about 30 nm from the surface of the silicon substrate 1.

Next, as shown in FIG. 4 (e), the channel sacrificial oxide portion 7 is removed by etching to form a channel opening B7 recessed below the surface of the other silicon substrate 1.

Next, as shown in FIG. 4 (f), Ge is selectively formed in the recessed channel opening B7 by the UHV-CVD method.
Epitaxial growth is performed to form the selective epitaxial channel portion 9. In detail, in the selective epitaxial channel portion 9, the thickness of the Si buffer layer is about 10 nm from below, the thickness of the Si _1-X Ge _X (X = 0.2) film is about 15 nm, and the thickness of the Si cap film is about 10 nm. Is about 5 nm
Is. As described above, the thickness of the selective epitaxial channel portion 9 is 30 nm in total, and the channel opening B7 is depressed by about 30 nm by the process shown in FIG.
The surface of the selective epitaxial channel portion 9 has substantially the same height as the surface of the surrounding silicon substrate 1.

Next, as shown in FIG. 4G, the surface of the selective epitaxial channel portion 9 is formed to a thickness of 2n by the RTA method.
A gate insulating film 10 is formed by forming an oxynitride film of about m. Although the RTA method is used here, the CVD method or the like may be used. The material forming the gate insulating film 10 is an oxynitride film here, but an oxide film, a nitride film, or other high dielectric film or ferroelectric film can also be used.

After that, as shown in FIG. 4H, non-doped polysilicon is deposited on the entire surface of the wafer by the LP-CVD method, and an acceleration energy of 8 keV is applied to this polysilicon.
B is ion-implanted by an ion-implantation method under the condition of a dose amount of 5 × 10 ¹⁵ C / cm ^-2 , and after thermal annealing, polysilicon in the planar portion is removed by CMP (Chemical Mechanical Polishing) method. Polysilicon 11 is formed.

Next, as shown in FIG. 5I, the replacement nitride film 3 is selectively removed, and the acceleration energy 8 is self-aligned.
BF ₂ is ion-implanted by the ion-implantation method under the condition that the keV dose amount is 2 × 10 ¹³ C / cm ⁻² , and the extension portion 1
Form 2.

Next, as shown in FIG. 5 (j), an oxide film is deposited on the entire surface of the wafer by the LP-CVD method, and the side wall protective film 15 is formed by anisotropic etching such as dry etching. After this, again, the self-aligned acceleration energy 8
The source / drain portion 14 is formed by ion-implanting B by the ion-implantation method under the condition that the keV dose amount is 5 × 10 ¹⁵ C / cm ⁻² .

Thereafter, as shown in FIG. 5 (k), the surfaces of the gate polysilicon 11 and the source / drain portions 14 are converted into cobalt silicide by a general salicide technique to form silicide portions 16, and then, as shown in FIG. As shown in FIG. 5L, an interlayer insulating film 17 is formed, contact holes are opened, a tungsten plug 18 is formed, and finally a metal wiring 19 is formed.

In the steps shown in FIGS. 3 (a) to 3 (d) and FIG. 4 (e), since the Si _1-X Ge _X material has not been used yet, equipment for producing a pure silicon semiconductor device is used. However, the problem of contamination of Ge and the like does not occur, and the conventional manufacturing equipment can be shared.

In the step shown in FIG. 4 (f), since it is necessary to perform epitaxial crystal growth containing Ge and the like, UHV-C which is not used in the pure silicon semiconductor element manufacturing step is used.
A VD device is required to manufacture the semiconductor device of the present invention.

In the step shown in FIG. 4G, since it is necessary to directly form the gate insulating film on the crystal containing Ge or the like, it is desirable to use a dedicated gate insulating film forming apparatus.

After the step shown in FIG. 4H, since the upper part of the crystal containing Ge or the like is covered with the gate insulating film or the like, Ge or the like is no longer present outside the semiconductor element and contaminates the manufacturing apparatus. Therefore, even if the equipment for producing the pure silicon semiconductor element is used, the problem of Ge contamination does not occur, and the conventional production equipment can be shared.

According to the semiconductor element having the selective epitaxial channel of the present embodiment, most of the manufacturing equipment can be made pure silicon semiconductor by improving the performance of the semiconductor element by increasing the carrier traveling speed in the channel region by providing a small number of dedicated equipment. Since it can be manufactured while being shared with the device, its economic effect is great.

[0045] Instead of the Si _1-X Ge _X channel region of the present embodiment, the C 0.01% ~2% (e.g. about 0.1%) containing Si _1-X Ge _X, i.e. Si _{1- An XY} Ge _X C _Y (0 ≦ X + Y ≦ 1 and 0 <Y ≦ 0.02) layer or a Si _1-X C _X (0 <X ≦ 0.02) layer may be used.

(Second Embodiment) In the present embodiment, Si _1-XY Ge _X C _Y (0 ≦ X + Y) is used as a material forming the channel region.
≦ 1 and 0 <Y ≦ 0.02), and an example of a MOSFET using a Si / Si _1-XY Ge _X C _Y heterojunction will be described.

FIG. 6 shows a MOSFET according to this embodiment.
3 is a cross-sectional view schematically showing the structure of FIG. Similar to the first embodiment, the element isolation oxide film 2 formed by LOCOS isolation or trench isolation for electrical isolation from other elements is formed on the surface of the silicon substrate 1. A selective epitaxial channel portion 9 made of a material containing Si _1-XY Ge _X C _Y is formed on a portion of the silicon substrate 1 which functions as a channel of the MOSFET. A gate insulating film 1 is formed on the selective epitaxial channel portion 9.
0 is formed, and gate polysilicon 11 is formed on the gate insulating film 10. A sidewall protective film 15 is formed around the gate polysilicon 11,
Source / drain portions 14 doped with impurities are formed on both sides of the sidewall protective film 15. Side wall protection film 15
Immediately underneath, an extension portion 12 which is a junction shallower than the source / drain portion 14 is formed in order to improve the performance of the transistor. A silicide portion 16 made of cobalt silicide is formed on the gate polysilicon 11 and the source / drain portion 14 in order to reduce the parasitic resistance of the transistor. An interlayer insulating film 17 is formed so as to cover the upper part of the transistor, and a tungsten plug 18 and a metal wiring 19 are formed so as to draw out electrodes from the source, drain and gate of the transistor.

7A to 7D and 8E to 8E.
(H) and FIGS. 9 (i) to 9 (j) show the MO in the present embodiment.
It is the figure which showed the process cross section of SFET typically.

As shown in FIG. 7A, after the element isolation oxide film 2 which is the element isolation region is formed on the silicon substrate 1 by the LOCOS method or the trench method, the element isolation oxide film 2 and the active region of the silicon substrate 1 are formed. A 250 nm-thick replacement oxide film 23 made of a silicon oxide film is formed thereon by LP-CVD. By the photolithography method and the dry etching method, the replacement oxide film 23 in the region where the gate electrode is formed is removed in a later step. At this time, part of the replacement oxide film 23 is etched by oxide film dry etching, and dry etching is automatically stopped using the silicon substrate 1 as a stopper.

Next, as shown in FIG. 7B, a 50 keV dose amount of 2 × 10 is self-aligned with the entire surface of the silicon substrate 1.
Ion implantation of P is performed under the condition of ¹³ C / cm ⁻² to form the high-concentration body portion 5 below the opening of the replacement oxide film 23. After that, annealing is performed at 850 ° C. for 30 minutes in a nitrogen atmosphere to carry out damage recovery of the silicon substrate 1 damaged by activation of the dopant and ion implantation.

Next, as shown in FIG. 7C, the silicon substrate 1 exposed in the opening of the replacement oxide film 23 is etched by dry etching to form the channel opening 6, and one of the silicon substrate 1 is formed. Dig into the section.

Next, as shown in FIG. 7D, heat treatment is performed in an oxidizing atmosphere to thermally oxidize the surface of the silicon substrate 1 exposed in the channel opening 6 by 10 nm to form the dry etching sacrificial oxide portion 27. Form. By this thermal oxidation, crystal defects on the surface of the silicon substrate 1 exposed in the channel opening 6 caused by dry etching are taken into the oxide film, and minor defects in the crystal are repaired by heat.

Next, as shown in FIG. 8E, the dry etching sacrificial oxide portion 27 is removed by wet etching to form a channel opening B7 recessed below the surface of the other silicon substrate 1. By using wet etching, the channel opening B7 can be formed without causing crystal defects on the surface of the silicon substrate 1.

Next, as shown in FIG. 8F, Ge is selectively formed in the recessed channel opening B7 by the UHV-CVD method.
Epitaxial crystal growth including C and C is performed to form the selective epitaxial channel portion 9. Specifically, the selective epitaxial channel portion 9 has a Si buffer layer having a thickness of about 10 nm from below, and Si _1-XY Ge _X C _Y (X = 0.28).
The thickness of the Y = 0.02) film is about 15 nm, and the thickness of the Si cap film is about 5 nm. As described above, the thickness of the selective epitaxial channel portion 9 is 30 nm in total.
By the process shown in (d), the channel opening B7 is set to about 30.
When processed so as to have a depression of nm, the surface of the selective epitaxial channel portion 9 becomes substantially the same height as the surface of the surrounding silicon substrate 1.

Next, as shown in FIG. 8 (g), the surface of the selective epitaxial channel portion 9 is formed to a thickness of 2n by the RTA method.
A gate insulating film 10 is formed by forming an oxynitride film of about m.

After that, as shown in FIG. 8H, non-doped polysilicon is deposited on the entire surface of the wafer by the LP-CVD method, and an acceleration energy of 8 keV is applied to this polysilicon.
B is ion-implanted by an ion-implantation method under the condition of a dose amount of 5 × 10 ¹⁵ C / cm ^-2 , and after thermal annealing, polysilicon in the planar portion is removed by CMP (Chemical Mechanical Polishing) method. Polysilicon 11 is formed.

Next, as shown in FIG. 9I, the replacement oxide film 23 is selectively removed by etching, and the acceleration energy is 8 keV and the dose amount is 2 × 10 ¹³ C / cm ^-2 in a self-aligned manner.
BF ₂ is ion-implanted by the ion implantation method under the following conditions,
The extension part 12 is formed. In this process, either dry etching or wet etching can be used, but from the viewpoint of controllability, wet etching must control the etching amount by the etching time, whereas dry etching does not. By using an etching end point detection method such as an optical method, it is easy to automatically stop etching when the active region of the MOSFET on the silicon substrate 1 is exposed. Therefore, it is preferable to use dry etching in this step.

After that, as in the first embodiment, the sidewall protection film 15 is formed, the source / drain portions 14 are formed,
A silicide portion 16 is formed, an interlayer insulating film 17 is formed as shown in FIG. 9 (j), a contact hole is opened,
Tungsten plug 18 is formed, and finally metal wiring 1
9 is formed.

Also in the present embodiment, FIG.
In the steps shown in (d) and FIG. 8 (e), since materials such as Ge are not used yet, even if a facility for manufacturing a pure silicon semiconductor element is used, the problem of contamination with Ge or the like does not occur, Conventional manufacturing equipment can be shared.

In the step shown in FIG. 8 (f), it is necessary to perform epitaxial crystal growth containing Ge, C, etc., so that UH not used in the pure silicon semiconductor element manufacturing step is used.
A V-CVD apparatus is required to manufacture the semiconductor device of the present invention.

In the step shown in FIG. 8G, since it is necessary to directly form the gate insulating film on the crystal containing Ge, C, etc., it is desirable to use a dedicated gate insulating film forming apparatus. When the deposited film is used as the gate insulating film, it is not always necessary.

After the step shown in FIG. 8H, Ge and C are used.
Since the upper part of the crystal including etc. is covered with the gate insulating film etc., the possibility that Ge etc. will go out of the semiconductor element and pollute the manufacturing apparatus is extremely low, so that the pure silicon semiconductor element is manufactured. Even if the equipment is used, the problem of contamination of Ge and the like does not occur, and the conventional manufacturing equipment can be shared.

According to the semiconductor element having the selective epitaxial channel of the present embodiment, most of the manufacturing equipment can be made pure silicon semiconductor by improving the performance of the semiconductor element by increasing the carrier traveling speed in the channel region by providing a small number of dedicated equipment. Since it can be manufactured while being shared with the device, its economic effect is great.

In place of the Si _1-XY Ge _X C _Y channel region of this embodiment, a Si _1-X Ge _X layer or a Si _{1- X} C _X (0 <X ≦ 0.02)
It goes without saying that layers may be used.

(Third Embodiment) In this embodiment, Si _1-X C _X (0 <X ≦ 0.0 is used as a material for forming the channel region.
2), MOS using Si / Si _1-X C _X heterojunction
An example of the FET will be described.

FIG. 10 shows the MOSFE of this embodiment.
It is sectional drawing which shows the structure of T typically. Similar to the first embodiment, the element isolation oxide film 2 formed by LOCOS isolation or trench isolation for electrical isolation from other elements is formed on the surface of the silicon substrate 1. A selective epitaxial channel portion 9 made of a material containing SiC is formed on a portion of the silicon substrate 1 which functions as a channel of the MOSFET. A gate insulating film 10 is formed on the selective epitaxial channel portion 9, and a gate polysilicon 11 is formed on the gate insulating film 10. Gate polysilicon 1
Gate metal 3 is formed on the upper part of 1 through barrier metal 35.
6 is formed. Sidewall protective films 15 are formed on the sides of the gate polysilicon 11, the barrier metal 35, and the gate metal 36, and impurity-doped source / drain portions 14 are formed on both sides of the sidewall protective film 15. There is. A silicide portion 16 made of nickel silicide is formed on the source / drain portion 14 in order to reduce the parasitic resistance of the transistor. An interlayer insulating film 17 is formed so as to cover the upper portion of this transistor,
A tungsten plug 18 and a metal wiring 19 are used to draw electrodes from the source, drain, and gate of the transistor.
Are formed.

11A to 11D, 12E to 12E.
13 (i) to 13 (j) show M in the present embodiment.
3 is a schematic view showing a process cross section of an OSFET.

As shown in FIG. 11A, the silicon substrate 1
After forming the element isolation oxide film 2 which is the element isolation region on the upper surface by the LOCOS method or the trench method, the element isolation oxide film 2 is formed.
Then, a replacement oxide film 23 of a silicon oxide film having a film thickness of 250 nm is formed on the active region of the silicon substrate 1 by the LP-CVD method. By the photolithography method and the dry etching method, the replacement oxide film 23 in the region where the gate electrode is formed is removed in a later step. At this time, part of the replacement oxide film 23 is etched by oxide film dry etching, and dry etching is automatically stopped using the silicon substrate 1 as a stopper.

Next, as shown in FIG. 11B, the entire surface of the silicon substrate 1 is self-aligned with a 20 keV dose amount of 4 × 1.
Ion implantation of B is performed under the condition of 0 ¹³ C / cm ⁻² to form the high-concentration body portion 5 below the opening of the replacement oxide film 23.
After that, annealing is performed at 850 ° C. for 30 minutes in a nitrogen atmosphere to carry out damage recovery of the silicon substrate 1 damaged by activation of the dopant and ion implantation.

Next, as shown in FIG. 11C, epitaxial crystal growth containing C is selectively performed in the channel opening 6 by the UHV-CVD method to form a selective epitaxial channel portion 9. In detail, in the selective epitaxial channel portion 9, the thickness of the Si buffer layer is about 5 nm from below, the thickness of the SiC film is about 15 nm, and S
The i-cap film has a thickness of about 5 nm.

Next, as shown in FIG. 11D, the surface of the selective epitaxial channel portion 9 is formed to a thickness of 2 by the RTA method.
An oxynitride film having a thickness of about nm is formed to be the gate insulating film 10.

Thereafter, as shown in FIG. 12E, non-doped polysilicon is deposited on the entire surface of the wafer by the LP-CVD method, and an acceleration energy of 10 k is applied to the polysilicon.
By implanting P ions by the ion implantation method under the condition of eV dose amount of 5 × 10 ¹⁵ C / cm ⁻² , thermal annealing, and then removing the polysilicon in the plane portion by the CMP (chemical mechanical polishing) method, Gate polysilicon 11 is formed.

Next, as shown in FIG. 12 (f), TiN having a thickness of 10 nm to be the barrier metal 35 is formed by the CVD method.
Then, 100 nm thick tungsten to be the gate metal 36 is deposited by the CVD method, and the barrier metal 35 and the gate metal 36 are patterned so as to cover the upper portion of the gate polysilicon 11 by the photolithography method and the dry etching method. .

Next, as shown in FIG. 12G, the replacement oxide film 23 is removed by anisotropic etching to form a sidewall protective film 15 under the gate polysilicon 11. In this dry etching, by using an etching end point detection method such as an optical method, the MOSFET on the silicon substrate 1 is
It is easy to automatically stop the etching when the active region is exposed. Therefore, it is preferable to use dry etching in this step.

Next, as shown in FIG. 12 (h), the acceleration energy is 20 keV and the dose amount is 5 × 10 ¹⁵ C / cm in a self-aligning manner.
^-As is ion-implanted under the condition of ^-2 ,
The source / drain portion 14 is formed. At this time, the tilt angle for ion implantation is set to 25 ° to 45 ° and the wafer is set to 4 °.
By implanting a total of four times (four rotations) while rotating once, it is possible to extend the source / drain region to the lower part of the sidewall protection film 15 and reduce the parasitic resistance of the MOSFET.

After that, as shown in FIG. 13 (i), the surface of the source / drain portion 14 is nickel-silicided by the salicide technique to form a silicide portion 16, and then an interlayer insulating film 17 is formed to form a contact. A hole is opened, a tungsten plug 18 is formed, and finally a metal wiring 19 is formed to form a MOSFET as shown in FIG.

The Si of the present embodiment is_1-XC_XChannel area
Instead of Si_1-XGe_XLayers and Si_1-XYGe _XC_YYou can use layers
Needless to say

Also in the present embodiment, FIG.
In the step shown in (b), since materials such as Ge and C are not used yet, even if a facility for manufacturing a pure silicon semiconductor element is used, the problem of contamination of Ge and C does not occur, and the conventional method is used. Manufacturing facilities can be shared.

In the step shown in FIG. 11 (c), since it is necessary to perform epitaxial crystal growth containing Ge, C, etc., UH which is not used in the pure silicon semiconductor element manufacturing step is used.
A V-CVD apparatus is required to manufacture the semiconductor device of the present invention.

In the step shown in FIG. 11D, since it is necessary to directly form the gate insulating film on the crystal containing Ge, C, etc., it is desirable to use a dedicated gate insulating film forming apparatus. When the deposited film is used as the gate insulating film, it is not always necessary.

In the step shown in FIG. 12 (e), since the upper part of the crystal containing Ge, C, etc. is covered with the gate insulating film, etc., Ge, C, etc. come out of the semiconductor element, and the manufacturing apparatus is Since the possibility of contamination is extremely low, the problem of contamination of Ge, C, etc. does not occur even if the equipment for producing a pure silicon semiconductor element is used, and the conventional production equipment can be shared.

After the step shown in FIG. 12 (f), since the upper part of the crystal containing Ge, C, etc. is covered with the gate insulating film and the like, and the manufacturing equipment in consideration of metal contamination is used, the usual process is performed. Equipment for manufacturing a pure silicon semiconductor device having a metal gate can be shared.

According to the semiconductor element having the selective epitaxial channel of the present embodiment, most of the manufacturing equipment can be made pure silicon semiconductor by improving the performance of the semiconductor element by increasing the carrier traveling speed in the channel region by providing a small number of dedicated equipment. Since it can be manufactured while being shared with the device, its economic effect is great. In particular, since the resistance of the gate polysilicon 11 can be reduced by the metal gate 36,
High frequency MOSFET and MOSFE for ultra high speed logic
Suitable for T applications.

[0084]

According to the present invention, the performance of a semiconductor device can be improved by increasing the carrier traveling speed in the channel region while avoiding the influence of contamination such as Ge and C. Therefore, only a small number of dedicated facilities are provided. It is possible to manufacture while sharing most of the manufacturing equipment with pure silicon semiconductor devices, and a single production line is a normal performance pure silicon semiconductor device and a high performance semiconductor device having an epitaxial channel region such as Ge or C. It becomes possible to provide a high performance and low cost semiconductor device. Further, according to the present invention, since the high-concentration body portion and the low-concentration channel portion can be manufactured without increasing the number of masks, a DT-MOS (Dynamic Thre) in which a high-concentration body portion is required.
hold MOSFET) and VT-MOS (Vari)
It is possible to economically provide a high-performance semiconductor element of a type in which the potential of the body is positively changed according to the operation of a circuit typified by an Able Threshold MOSFET).

[Brief description of drawings]

FIG. 1 is a view showing a structural cross-section of a semiconductor element in a conventional example and a cross-section during a manufacturing process of a semiconductor element in a conventional example.

FIG. 2 is a sectional structural view of the semiconductor device of the first embodiment.

FIG. 3 is a process cross-sectional view relating to the method for manufacturing the semiconductor element of the first embodiment.

FIG. 4 is a process cross-sectional view relating to the method of manufacturing the semiconductor element of the first embodiment.

FIG. 5 is a process cross-sectional view relating to the method of manufacturing the semiconductor element of the first embodiment.

FIG. 6 is a sectional structural view of a semiconductor device of a second embodiment.

FIG. 7 is a process cross-sectional view relating to the manufacturing method of the semiconductor element of the second embodiment.

FIG. 8 is a process cross-sectional view relating to the method of manufacturing the semiconductor element of the second embodiment.

FIG. 9 is a process cross-sectional view relating to the method of manufacturing the semiconductor element of the second embodiment.

FIG. 10 is a sectional structural view of a semiconductor device according to a third embodiment.

FIG. 11 is a process cross-sectional view relating to the method for manufacturing a semiconductor device of the third embodiment.

FIG. 12 is a process cross-sectional view relating to the manufacturing method of the semiconductor element of the third embodiment.

FIG. 13 is a process cross-sectional view relating to the method for manufacturing a semiconductor device of the third embodiment.

[Explanation of symbols]

1 Silicon substrate 2 element isolation oxide film 3 Replacement nitride film 4 Pad oxide film 5 High concentration body 6 channel opening 7 Channel sacrificial oxidation part 8 channel opening B 9 Selective epitaxial channel section 10 Gate insulating film 11 Gate polysilicon 12 Extension section 14 Source / Drain 15 Side wall protective film 16 Silicide part 17 Interlayer insulation film 18 Tungsten plug 19 Metal wiring 23 Replacement oxide film 27 Dry etching sacrificial oxide film 35 Barrier metal 36 gate metal 101 selective epitaxial part

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F140 AA00 AA05 AB01 AC01 AC28                       BA01 BA02 BA05 BB06 BB13                       BB18 BC13 BC15 BD04 BD05                       BD07 BD09 BE10 BE19 BF04                       BF11 BF18 BF20 BF21 BF27                       BF60 BG08 BG12 BG28 BG32                       BG34 BG36 BG40 BH14 BH40                       BJ08 BJ11 BJ17 BJ27 BK13                       BK14 CB01 CB04 CE07 CF04

Claims (19)

[Claims] 1. A semiconductor substrate, an element isolation portion provided on a part of the semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a gate electrode provided on the gate insulating film. A source / drain region of the first conductivity type provided on both sides of the gate electrode in the semiconductor substrate, and an epitaxial method provided in a region of the semiconductor substrate located between the source / drain regions. A channel region formed of the first semiconductor, and a second semiconductor that is provided below the channel region of the semiconductor substrate and has a larger potential for carriers at a band edge in which carriers travel than the first semiconductor. A semiconductor device having a body region of the second conductivity type. 2. The semiconductor device according to claim 1, wherein a carrier at a band edge, which is provided between the channel region and the gate insulating film in the semiconductor substrate and in which carriers travel than the first semiconductor, is used. A semiconductor device further comprising a cap layer made of a semiconductor having a large potential. 3. The semiconductor device according to claim 1, wherein the first semiconductor is formed between the source / drain regions by a selective epitaxial method. 4. The semiconductor device according to claim 1, wherein the channel region contains a low concentration impurity that is 1/10 or less that of the body region. . 5. The semiconductor device according to claim 1, wherein the gate electrode is polysilicon, polysilicon germanium or metal containing a first conductivity type impurity, or a composite thereof. A semiconductor device comprising: 6. The semiconductor device according to claim 1, wherein the first semiconductor forming the channel region contains at least Si as a component element, and a part of the epitaxial semiconductor layer is formed. Is a region for preventing diffusion of impurities into the channel, and is 0.01
A semiconductor device further comprising a region containing carbon in a concentration of not less than 2% and not more than 2%. 7. The semiconductor device according to claim 1, wherein the first semiconductor is a semiconductor containing Si (silicon) and Ge (germanium) as component elements, and the second semiconductor The semiconductor device is a semiconductor device characterized by being Si. 8. The semiconductor device according to claim 1, wherein the first semiconductor is a semiconductor containing Si and C (carbon) as component elements, and the second semiconductor is A semiconductor device comprising Si. 9. The semiconductor device according to claim 1, wherein the first semiconductor is a semiconductor containing Si, Ge and C as component elements, and the second semiconductor is Si. A semiconductor device characterized by: 10. The semiconductor device according to claim 7, further comprising a cap layer made of Si formed between the gate insulating film and the channel region and formed by a selective epitaxial method. A semiconductor device characterized by being provided. 11. The semiconductor device according to claim 7, wherein the source / drain regions are p-type source / drain regions, and the channel region is a p-channel channel region. The semiconductor device, wherein the body region is an n-type body region. 12. The semiconductor device according to claim 7, wherein the source / drain regions are n-type source / drain regions, and the channel region is an n-channel channel region. The semiconductor device, wherein the body region is a p-type body region. 13. A semiconductor substrate, an element isolation portion provided on a part of the semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a gate electrode provided on the gate insulating film. A first conductive type source / drain region provided on both sides of the gate electrode of the semiconductor substrate, and an epitaxial method provided on a region of the semiconductor substrate located between the source / drain regions. A channel region formed of the first semiconductor,
A second conductivity type body region, which is provided below the channel region of the semiconductor substrate and is made of a second semiconductor having a larger potential for carriers at a band edge in which carriers travel than the first semiconductor, is provided. A method of manufacturing a semiconductor device, comprising: a step (A) of forming the element isolation portion on the semiconductor substrate; a step (B) of forming a replacement gate insulating film; and a gate planned region of the replacement gate insulating film. And (C) to form a channel opening by etching, a step (D) of selectively epitaxially growing crystal in the channel opening to form the channel region, and a gate insulating film formed on the channel region. (E), forming a gate conductive film on the gate insulating film (F), and removing the replacement gate insulating film ( ), A step of forming a sidewall protection film (H), a method of manufacturing a semiconductor device characterized in that it comprises a step (I) to form the source and drain regions. 14. The method of manufacturing a semiconductor device according to claim 13, wherein ions are self-aligned through the channel opening after forming the channel opening and before forming the gate insulating film. A method of manufacturing a semiconductor device, comprising the step (C-1) of forming the body region of the second conductivity type, which has a greater potential for carriers at the band edge where the carriers travel than in the channel region. . 15. The method of manufacturing a semiconductor device according to claim 13, wherein the channel opening is formed after the channel opening is formed and before the channel region is formed by a selective epitaxial method. A step (C-2A) of removing the oxide film by selective oxidation and etching of the portion, and positioning the upper end of the channel opening below the upper end of the semiconductor substrate (C-2A). 16. The method of manufacturing a semiconductor device according to claim 13, wherein the channel opening is formed after the channel opening is formed and before the channel region is formed by a selective epitaxial method. A method of manufacturing a semiconductor device, comprising: a step (C-2B) of digging a portion by dry etching to position an upper end of the channel opening below an upper end of a semiconductor substrate. 17. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (E) of forming a gate insulating film on the channel region, the cap layer made of Si is oxidized or A method of manufacturing a semiconductor device, comprising forming a gate insulating film by nitriding. 18. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (E) of forming a gate insulating film on the channel region, the gate is formed by a chemical deposition method such as CVD. A method for manufacturing a semiconductor device, which comprises forming an insulating film. 19. The method of manufacturing a semiconductor device according to claim 17, wherein a step (D) of selectively epitaxially growing crystals in the channel opening to form the channel region and a gate insulating film are performed. A semiconductor device manufacturing method characterized in that only in a forming step (E), a manufacturing apparatus dedicated to a Si semiconductor device containing Ge and C as constituent elements is used, and other steps are shared with another semiconductor device manufacturing apparatus.