JP2002280547A - Mis semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure high current driving power while suppressing a short channel effect of a finely patterned MIS type semiconductor device. SOLUTION: The MIS device comprises source-drain regions 2 and 3 provided in the active region of an Si substrate while being doped heavily with n-type impurities, extensions 6 and 7 extending from the source-drain regions 2 and 3 toward a region beneath a gate electrode 5 while being doped relatively heavily with the n-type impurities, and two threshold level control pockets 12 contiguous to the extensions 6 and 7 and doped with p-type impurities. The upper part of the threshold level control pocket 12 serves as a channel region lightly doped with the p-type impurities. Since the threshold level control pocket 12 does not touch the source-drain regions 2 and 3, junction capacity is reduced and an operating and speed is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MISFET structure, and more particularly to a measure for improving a current driving force when miniaturized.

[0002]

2. Description of the Related Art In recent years, in order to further increase the integration of a VLSI, the size of a MIS device which is a semiconductor device having a MISFET structure used for the VLSI has been increasingly miniaturized. Or design rules extend from quarter micron to sub-quarter micron range. At the research level, MIS devices having a gate length of 0.1 μm or less have been prototyped. With such miniaturization of the MIS device, the electrical characteristics of the MIS device may be deteriorated due to the short channel effect. The deterioration of the electric characteristics due to the short channel effect causes the deterioration of the reliability of the MIS device, and is a serious problem.

On the other hand, in VLSI technology, which is indispensable for the future multimedia society, it is important to achieve high speed operation and low power consumption simultaneously with high integration of semiconductor devices.

In order to improve the function of suppressing the short channel effect accompanying the miniaturization of the MIS device and to realize the high-speed operation, for example, a method described in the literature (1993 International On Electron Devices Meeting Meeting Technical Digest) has been proposed. (1993 International
al Electron Devices Meeting Technical Digest) pp88
3-886 K. Takeuchi et al.), A MIS device (MISFET) having a gate length in a submicron region and having a local channel structure has been proposed.

FIG. 10 is a sectional view of a conventional n-channel MIS device having a local channel structure. As shown in FIG. 1, the MIS device includes a source region 102 and a drain region 103 formed at a distance from each other in a Si substrate 101 and containing a high-concentration n-type impurity. Extension 106, drain extension 107, p-type local channel region 110 containing p-type impurities, gate insulating film 104 provided on Si substrate 101, and gate insulating film 10
4 and a gate electrode 105 provided on
5 and a sidewall 108 made of a silicon oxide film provided on the side surface.

In the MIS device having the local channel structure, the source extension 106 and the drain extension 1 containing high-concentration n-type impurities are formed.
07, the source / drain parasitic resistance is smaller than that of the conventional LDD structure. Therefore, this MIS device does not cause a decrease in drain current due to source / drain parasitic resistance,
A decrease in threshold voltage due to the short channel effect is suppressed. Further, in the MIS device, the p-type local channel region 110 includes the source region 102 and the drain region 103.
Does not exist below the source region 10.
2 and the Si substrate 101 and the junction capacitance between the drain region 103 and the Si substrate 101 are reduced. That is, high-speed operation can be achieved by reducing the source / drain parasitic resistance.

As described above, the conventional MIS device having a local channel structure achieves high-speed operation by a p-type local channel structure while suppressing a decrease in threshold voltage due to a short channel effect by extension. .

[0008]

However, as described below, it is difficult to apply the above-mentioned conventional local channel structure to a MIS device having a gate length of 0.1 μm or less.

First, an MI having a gate length of 0.1 μm or less is used.
For the S device, the tolerance for the decrease in the threshold voltage due to the short channel effect becomes stricter, so it is necessary to suppress the decrease in the threshold voltage. In order to suppress a decrease in the threshold voltage of the transistor, it is necessary to increase the impurity concentration in the channel region. However, in the conventional MIS device having the local channel structure, when the impurity concentration of the p-type local channel region 110 is increased, the p-type local channel region 110, the source region 102, the source extension 106, the drain region 103, and the drain The junction capacitance with the extension 107 increases. As a result, the operation speed of the MIS device decreases.

Second, when the impurity concentration of the region located below the source extension 106 and the drain extension 107 in the p-type local channel region 110 becomes high, the junction leak current increases. This increase in junction leakage current causes an increase in power consumption during standby of the VLSI.

Third, in the p-type local channel region 110 containing a relatively high concentration of p-type impurities, carrier mobility may be reduced due to carrier scattering effect of the impurities. This decrease in carrier mobility causes a decrease in operation speed and a decrease in saturation current value of the transistor.

In the process of manufacturing a conventional MIS device having a local channel region, a photoresist having an opening only near the center of the active region is formed on the Si substrate 101 before the gate electrode 105 is formed. A p-type local channel region 110 needs to be formed by forming a film and performing ion implantation of a p-type impurity using the photoresist film as an implantation mask. Therefore, in the CMIS device, it is necessary to add two lithography steps to the normal process,
This leads to an increase in manufacturing costs. Moreover, since it is necessary to align the mask used in the lithography step with the mask used in the lithography step for forming the gate electrode, the structure of the conventional MIS device having the local channel structure is reduced to 0.1 μm. It is difficult to apply to a fine MIS device having the following gate length in manufacturing.

An object of the present invention is to provide a means for suppressing the short channel effect without increasing the parasitic resistance of the source / drain or extension or the junction capacitance, and to reduce the current while miniaturizing. An object of the present invention is to provide a semiconductor device having a high driving force and a manufacturing method thereof.

[0014]

According to a first MIS type semiconductor device of the present invention, there is provided a semiconductor substrate having a main surface, a first conductivity type source region formed in the semiconductor substrate, A drain region of the first conductivity type, which is separated from the source region by a certain distance, and a channel formed on the main surface side surface of the semiconductor substrate and located between the source region and the drain region. A region, a gate insulating film formed on the main surface of the semiconductor substrate and covering the channel region, a gate electrode formed on the gate insulating film, and the source region and the channel region in the semiconductor substrate. A source extension of a first conductivity type, the junction depth of which is smaller than the junction depth of the source region, and the drain region and the channel in the semiconductor substrate. Is provided between the LE region, a drain extension of the first conductivity type shallower than the junction depth of the junction depth above the drain region, is formed below the channel region in the above semiconductor substrate, the source
A second conductivity type threshold control region provided in contact with the extension and a part of each lower portion of the drain extension, while being separated from the source / drain region.

Thus, the threshold control region does not necessarily contact the entire lower part of the extension.
The junction capacitance at the pn junction below the extension is reduced. Also, since the threshold control region is not in contact with the source / drain regions, the threshold voltage around the source / drain regions
The junction capacitance at the n junction is reduced. Further, since there is almost no high-concentration second conductivity type region below the first conductivity type extension, the junction leakage current between the extension and the substrate region is also reduced. Further, since the threshold control region including the impurity has a structure that does not reach the surface of the semiconductor substrate, the effect that carriers traveling in the channel are scattered by the impurity is suppressed. Therefore, the carrier mobility of the MIS device of the present embodiment is larger than that of the conventional MIS device having a local channel structure, and the current driving force is improved. On the other hand, in a region located below the gate electrode, the second
Since the conductivity type threshold control region remains, the function of preventing the short channel effect is ensured. Therefore, it is possible to avoid the deterioration of the saturation current value while suppressing the occurrence of the short channel effect.

It is preferable that the peak of the impurity concentration in the threshold control region is located at a depth substantially equal to the junction depth of the source extension and the drain extension.

It is preferable that a region having the largest number of crystal defects exists near the lower part of the source extension and the drain extension.

According to a second MIS type semiconductor device of the present invention, there is provided a semiconductor substrate having a main surface, a first conductivity type source region formed in the semiconductor substrate, and a source region formed in the semiconductor substrate. A first conductivity type drain region separated by a certain distance from the region, a channel region formed on the main surface side of the semiconductor substrate and located between the source region and the drain region, A gate insulating film formed on the main surface of the semiconductor device and covering a portion excluding an end of the channel region; a gate electrode formed on the gate insulating film; and the source region and the channel region in the semiconductor substrate. A source extension of a first conductivity type, the junction depth of which is smaller than the junction depth of the source region, and the drain region and the channel in the semiconductor substrate. Is provided between the LE region, a drain extension of the first conductivity type shallower than the junction depth of the junction depth above the drain region, is formed below the channel region in the above semiconductor substrate, the source
A second conductivity type threshold control which is divided into a portion contacting a part of a lower portion of the extension and a portion contacting a portion of a lower portion of the drain extension, and is provided apart from the source / drain region. Area.

According to this, the same operation and effect as those of the first MIS type semiconductor device can be obtained.

Preferably, the peak of the impurity concentration of the threshold control region is located at a depth substantially equal to the junction depth of the source extension and the drain extension.

It is preferable that a region having the largest number of crystal defects exists near the lower part of the source extension and the drain extension.

According to a first method of manufacturing a MIS type semiconductor device of the present invention, a concentration profile is obtained in which impurity ions of the second conductivity type are implanted into an active region of a semiconductor substrate to have a low concentration at a surface portion and a high concentration at a deep portion. (A) forming a second conductivity type region having the following steps: (b) sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate; and (b) forming a first conductivity type region using the gate electrode as a mask. Implanting impurity ions into the active region to form a first conductivity type region having an amorphous region shallower than the depth of the second conductivity type region on both sides of the gate electrode in the semiconductor substrate ( c) activating the first and second conductivity type regions by heat treatment and recovering the amorphous region at the same time as the source extension region and the drain extension region. And Deployment region, and a (d) forming a threshold control area in contact with part of the lower portion of the source extension region and drain extension regions.

According to this method, the depth of the amorphized region of the first conductivity type region formed in the step (c) is smaller than the depth of the second conductivity type region formed in the step (a). When heat treatment is performed in (d), lattice defects concentrate near the interface between the amorphous region and the region having relatively good crystallinity in the process of recovering the amorphous region. As a result, the high-concentration second conductivity type region existing below the first conductivity type region disappears. On the other hand, in a region of the semiconductor substrate between the source extension and the drain extension, that is, in a region located below the gate electrode, since the first conductivity type region is not formed, the threshold control region Remain, and the function of preventing the short channel effect is secured. That is, the MIS having a high function of suppressing the short channel effect and having a high saturation current value
A semiconductor device is obtained.

In the step (c), the peak position of the first conductivity type impurity concentration in the first conductivity type region is higher than the peak position of the second conductivity type impurity concentration in the second conductivity type region. It is preferable to form the first conductivity type region as described above.

According to a second method of manufacturing a MIS type semiconductor device of the present invention, there is provided a step (a) of sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate, and using the gate electrode as a mask, Implanting impurity ions of the second conductivity type into the active region, and forming a second conductivity type region having a concentration profile of low concentration at the surface portion and high concentration at the deep portion on both sides of the gate electrode ( b) implanting impurity ions of the first conductivity type into the active region using the gate electrode as a mask, and shallower on both sides of the gate electrode in the semiconductor substrate than the depth of the second conductivity type region; (C) forming a first conductivity type region having an amorphized region, and activating the first and second conductivity type regions and simultaneously recovering the amorphized region by heat treatment. Ri, and the source extension region and a drain extension regions, the source
And (d) forming a pair of threshold control regions that are in contact with a part of each lower portion of the extension region and the drain extension region and that are separated from each other.

According to this method, the same function and effect as those of the first method of manufacturing the MIS semiconductor device can be obtained.

In the step (c), the peak position of the first conductivity type impurity concentration in the first conductivity type region is higher than the peak position of the second conductivity type impurity concentration in the second conductivity type region. It is preferable to form the first conductivity type region as described above.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment)-Structure of MIS Device-FIG. 1 shows a MISFET according to a first embodiment of the present invention.
It is sectional drawing of the MIS device which has a structure. As shown in the figure, the MIS device of the present embodiment is a Si substrate 1
And an element isolation oxide film 9 provided near the surface of the Si substrate 1 and surrounding the active region; a source region 2 and a drain region 3 containing high-concentration n-type impurities provided separately from each other in the active region. A gate insulating film 4 provided on a region located between the source region 2 and the drain region 3 in the Si substrate 1; a gate electrode 5 provided on the gate insulating film 4; And a source extension 6 containing a relatively high concentration of n-type impurities extending from the source region 2 to a region below the gate electrode 5 in the Si substrate 1. A drain extension 7 including a relatively high concentration of n-type impurity extending from the drain region 3 to a region below the gate electrode 5 in the Si substrate 1; The threshold control area 11 including a p-type impurity that is interposed between the source extension 6 and drain extension 7 in the substrate 1, S
A low-concentration channel region 15 containing a low-concentration p-type impurity is provided in a region between the threshold control region 11 and the gate insulating film 4 in the i-substrate 1.

Here, the junction depth (depth to the pn junction) of the source extension 6 and the drain extension 7 is determined by the source region 2 and the drain region 3.
Shallower than the junction depth. Also, the threshold control area 11
Is deeper than the junction depth of the source extension 6 and the drain extension 7, but is shallower than the junction depth of the source region 2 and the drain region 3.
Further, the threshold control region 11 is not in contact with the source region 2 and the drain region 3. That is, the threshold control region 11 is not in contact with the entire lower portion of the source extension 6 and the drain extension 7.

With the above configuration, the present embodiment has the following operational effects.

First, the threshold control region 11 is not in contact with the entire lower part of the source extension 6, and most of the lower part of the source extension 6 is S
It is in contact with a substrate region (p well or the like) containing a low-concentration p-type impurity in i substrate 1. Therefore, in the MIS device according to the present embodiment, as compared with the conventional MIS device in which the p-type local channel region 110 is entirely in contact with the lower portion of the source extension 102 (see FIG. 10), The junction capacitance of the pn junction is reduced.

Similarly, in the MIS device of the present embodiment, the junction capacitance at the pn junction below the drain extension 7 is reduced.

The threshold control region 11 is not in contact with the source region 2, and the source region 2 is a source region 6 of the same conductivity type or a substrate region containing a low-concentration p-type impurity in the Si substrate 1. (Such as a p-well).
Therefore, as compared with the conventional MIS device in which the p-type local channel region 110 is in contact with the source region 102 (see FIG. 10), the junction capacitance of the pn junction around the source region 2 in the MIS device of the present embodiment. Is reduced.

Similarly, in the MIS device of the present embodiment, the junction capacitance at the pn junction around the drain region 3 is reduced. Therefore, the operation speed of the MIS device is improved.

Second, since there is almost no high-concentration p-type region below the source extension 6 and the drain extension 7, the junction leakage current between the source extension 6 and the drain extension 7 and the substrate region is also reduced. Become smaller.

Third, the threshold control region 11 containing a high concentration p-type impurity for suppressing the short channel effect is
Since the structure does not reach the surface of the i-substrate 1 and most of the carriers travel in the low-concentration channel region 15 during operation, the effect that the carriers are scattered by impurities is suppressed. Therefore, the carrier mobility of the MIS device of the present embodiment is larger than that of the conventional MIS device having a local channel structure, and the current driving force is improved.

Therefore, it is possible to realize a transistor having a high current drivability while securing the function of preventing the short channel effect.

-Manufacturing Method- FIGS. 2A to 3B show n in the first embodiment.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a MIS device having a MISFET structure. Here, only the manufacturing process in the nMISFET formation region will be described, but the manufacturing process in the pMISFET formation region can be similarly performed by reversing the conductivity type of the impurity to be introduced.

First, in the step shown in FIG. 2A, a trench-type element isolation surrounding the active region is formed on the surface of the Si substrate 1 by a known technique using photolithography, dry etching, burying of an oxide film, or the like. An oxide film 9 is formed.

Next, using a resist mask covering the pMISFET formation region as an implantation mask, low-concentration p-type impurity ions (for example, boron ions) are implanted at a high energy to form a p-well. By implanting (medium concentration) p-type impurity ions, a p-type doped layer 11x (second conductivity type region) is formed. As a specific example of the method, indium ions (In ⁺ ) are charged at an acceleration voltage of 20 to 100 keV and a dose of 6.0 × 10 ^12.
The implantation is performed under the condition of cm ^{−2 to} 1.0 × 10 ¹³ cm ⁻² . In particular, the acceleration voltage is 50 keV and the dose is 8.0 × 10 ¹²
A degree of cm ^-2 is preferred.

Next, before forming the gate insulating film, a heat treatment for activating In is performed at, for example, 1000 ° C. for 10 seconds. In many cases, a punch-through stopper is formed in a region deeper than the p-type doped layer 11x. In this case, p-type impurity ions for forming a punch-through stopper are also implanted in this state.

At this time, the junction depth of the p-type doped layer 11x
Is about 100 nm, and the depth of the peak position of the impurity concentration is
The length is about 50 nm. And acceleration during ion implantation
Because of the high voltage, the
Due to the extremely low concentration of J, the surface of the active area
The portion is a low-concentration p-type region 15x. In addition, p-type
Impurity concentration of indium in the loop layer 11x
Is 1.0 × 10¹⁸cm ^-3And the low-concentration p-type region 1
5 × impurity concentration is about 1.0 × 10¹⁷cm^-3Below
You. The p-type impurity implanted at this time is limited to indium.
Although not specified, especially heavy elements such as indium
Low impurity concentration on the surface of active region by using
Form a low-concentration p-type region and have a high peak concentration below it
A threshold control region can be formed.

Before forming the isolation oxide film 9, a p-well doped with a low-concentration p-type impurity and an n-well doped with a low-concentration n-type impurity are formed in the Si substrate 1. May be formed, and ion implantation for forming the p-type doped layer 11x and the low-concentration p-type region 15x may be performed subsequent to the ion implantation for the p-well.

Next, in the step shown in FIG. 2B, after an oxide film and a conductor film are sequentially deposited on the surface of the active region, the conductor film and the oxide film are patterned to form a gate insulating film 4 and a gate electrode. 5 is formed. Next, using the gate electrode 5 as a mask, an n-type impurity is ion-implanted into the active region, so that the n-type doped layer 6x,
7x (first conductivity type region) is selectively formed. At this time, ion implantation is performed to such an extent that a shallow region in the active region becomes amorphous. For example, when arsenic is implanted at an implantation energy of 4 keV and a high dose of about 8.0 × 10 ¹⁴ cm ⁻² , the n-type doped layers 6x and 7x are made amorphous. The depth of the amorphized regions of the n-type doped layers 6x and 7x is about 40 nm, and is formed slightly shallower than the depth (about 50 nm) of the peak concentration position of the p-type doped layer 11x. At this time, the p-type doped layer 11
Most of the x regions located on both sides of the gate electrode 5 are composed of n-type doped layers 6x and 7x containing high-concentration n-type impurities.
Changes to However, since the implantation energy at the time of ion implantation of the p-type impurity is larger than the implantation energy at the time of ion implantation of the n-type impurity, a part of the p-type doped layer 11x remains below the n-type doped layers 6x and 7x. ing.

Next, in the step shown in FIG. 3A, a heat treatment for activating the impurities in the p-type doped layer 11x, the n-type doped layers 6x and 7x and the low concentration p-type region 15x is performed, and the source is formed. The extension 6, the drain extension 7, the threshold control region 11, and the low concentration channel region 15 are formed. At this time, the amorphous region of the active region is recrystallized, and crystal defects occur in the recrystallized region. Since this crystal defect causes accelerated diffusion of impurities, n-type doped layers 6x and 7x of p-type doped layer 11x in the state shown in FIG.
It is considered that the p-type impurity (indium) in the region remaining under x is attracted to crystal defects in the source extension 6 and the drain extension 7. As a result, the threshold control region 11 is formed only between the source extension 6 and the drain extension 7, and the threshold control region 11
A low concentration channel region 15 is formed on the substrate.

Thereafter, in a step shown in FIG. 3B, a silicon oxide film is deposited and the silicon oxide film is etched back by anisotropic etching to form sidewalls 8 on the side surfaces of the gate electrode 5. I do. Thereafter, n-type impurity ions such as arsenic, phosphorus or antimony are implanted into the active region using the gate electrode 5 and the side walls 8 as a mask. As a result, the source
Outside the extension 6 and the drain extension 7, an n-type source region 2 and an n-type drain region 3 whose junction depth is deeper than the source extension 6 and the drain extension 7 are formed.

According to the manufacturing method of this embodiment, FIG.
In the step shown in FIG. 2A, a p-type impurity having a medium concentration is ion-implanted with a relatively large implantation energy. 15x can be formed. Since this ion implantation can be performed using the same mask as the ion implantation for forming the p-well (or punch-through stopper), the photolithography process does not increase.

At this time, by using a heavy element such as indium, a low-concentration p-type region having a low impurity concentration is formed on the surface of the active region, and a threshold control region having a high peak concentration is formed therebelow. can do.

Next, in the step shown in FIG. 2B, when the n-type impurity (arsenic) is ion-implanted, the n-type doped layer 6
The peak position of the impurity concentration in x, 7x is the p-type doped layer 1
By implanting ions so as to be shallower than the peak position of the impurity concentration in 1x, a part of the p-type doped layer 11x is left below the n-type doped layers 6x and 7x. Then, if annealing for activating impurities is performed in the step shown in FIG. 3A, crystal defects are generated when the amorphous region is recrystallized, and the crystal defects increase in impurities. It is thought to cause rapid diffusion. As a result, in the p-type doped layer 11x, the region including the high-concentration p-type impurity existing below the source extension 6 and the drain extension 7 disappears, and the source extension 6 and the drain extension 7 are removed. The threshold control region 11 is formed only in between. Then, when the source region 2 and the drain region 3 are formed in the step shown in FIG. 3B, the threshold control region 11 does not contact the source region 2 and the drain region 3.

Therefore, a MIS device having a miniaturized gate structure as shown in FIG. 1 can be easily realized without increasing the number of photolithography steps.

(Second Embodiment)-Structure of MIS Device-FIG. 4 shows a MISFET according to a second embodiment of the present invention.
It is sectional drawing of the MIS device which has a structure. As shown in the figure, the MIS device of the present embodiment is a Si substrate 1
And an element isolation oxide film 9 provided near the surface of the Si substrate 1 and surrounding the active region; a source region 2 and a drain region 3 containing high-concentration n-type impurities provided separately from each other in the active region. A gate insulating film 4 provided on a region located between the source region 2 and the drain region 3 in the Si substrate 1; a gate electrode 5 provided on the gate insulating film 4; And a source extension 6 containing a relatively high concentration of n-type impurities extending from the source region 2 to a region below the gate electrode 5 in the Si substrate 1. And a drain extension 7 containing a relatively high concentration of n-type impurities extending from the drain region 3 to a region below the gate electrode 5 in the Si substrate 1; Source extension 6 in the i substrate 1, and a two thresholds controlling pocket 12 containing p-type impurities respectively adjacent to the drain extension 7. The region located between the source extension 6 and the drain extension 7 and above the threshold control pocket 12 in the active region is a low-concentration channel region containing a low-concentration p-type impurity. .

Here, the junction depth of the source extension 6 and the drain extension 7 (depth to the pn junction) is the source region 2 and the drain region 3
Shallower than the junction depth. The threshold control pocket 12 is not in contact with the source region 2 or the drain region 3. That is, the threshold control pocket 12 is not in contact with the entire lower part of the source extension 6 and the drain extension 7.

With the above configuration, the following operational effects can be obtained in this embodiment.

First, the threshold control pocket 12 is not in contact with the entire lower portion of the source extension 6, and most of the lower portion of the source extension 6 has a low concentration of p-type in the Si substrate 1. It is in contact with a substrate region containing impurities (such as a p-well). Therefore, the p-type local channel region 110 is
In the MIS device of the present embodiment, the junction capacitance of the pn junction below the source extension 6 is reduced as compared with the conventional MIS device entirely contacting the lower portion of the MIS device (see FIG. 10).

Similarly, in the MIS device of the present embodiment, the junction capacitance at the pn junction below the drain extension 7 is reduced.

The threshold control pocket 12 is not in contact with the source region 2, and the source region 2 is a source region 6 of the same conductivity type or a substrate region in the Si substrate 1 containing a low concentration of p-type impurities. (Such as a p-well). Therefore, the conventional MIS device in which the p-type local channel region 110 is in contact with the source region 102 (FIG. 10)
Compared with the MIS device of the present embodiment, the junction capacitance of the pn junction around the source region 2 is reduced.

Similarly, in the MIS device of this embodiment, the junction capacitance at the pn junction around the drain region 3 is reduced. Therefore, the operation speed of the MIS device is improved.

Second, since there is almost no high-concentration p-type region below the source extension 6 and the drain extension 7, the junction leakage current between the source extension 6 and the drain extension 7 and the substrate region is also reduced. Become smaller.

Third, the threshold control pocket 12 containing a high concentration p-type impurity for suppressing the short channel effect is
Since the structure does not reach the surface of the i-substrate 1 and most of the carriers travel in the low-concentration channel region during operation, the effect that the carriers are scattered by impurities is suppressed. Therefore, the carrier mobility of the MIS device of the present embodiment is larger than that of the conventional MIS device having a local channel structure, and the current driving force is improved. Therefore, it is possible to realize a transistor having a high current drivability while ensuring the function of preventing short channel effects.

Further, unlike the first embodiment, in the present embodiment, the threshold control pocket 12 which is a threshold control area is divided into two right and left sides, and the entire area below the gate electrode 5 is formed. It doesn't exist all over,
The sub-threshold slope is the MIS of the first embodiment.
It is smaller than the sub-threshold slope of the device. Therefore, it can be said that the first embodiment is more advantageous in reducing power consumption and increasing the speed.

-Manufacturing Method- FIGS. 5A to 6B show n in the second embodiment.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a MIS device having a MISFET structure. Here, only the manufacturing process in the nMISFET formation region will be described, but the manufacturing process in the pMISFET formation region can be similarly performed by reversing the conductivity type of the impurity to be introduced.

First, in the step shown in FIG. 5A, a trench structure element isolation surrounding the active region is formed on the surface of the Si substrate 1 by a known technique using photolithography, dry etching, burying an oxide film, or the like. An oxide film 9 is formed. Further, after the formation of the element isolation insulating film 9 or before the formation of the element isolation insulating film 9, an n-type well is formed by implanting n-type impurity ions into the pMISFET formation region.
A p-well is formed by implanting p-type impurity ions into the FET formation region.

Subsequently, after sequentially depositing an oxide film and a conductor film on the surface of the active region, the conductor film and the oxide film are patterned to form a gate insulating film 4 and a gate electrode 5. Further, a relatively high concentration (medium concentration) of p-type impurity ions is implanted using the gate electrode 5 as a mask, so that a p-type serving as a pocket is formed in a region of the active region located on both sides of the gate electrode 5. The doped layer 12x is formed. As an example of a specific method, indium ion (I
The n ^+), the acceleration voltage is 50 keV, the dose of 1.0 ×
The implantation is performed under the condition of about 10 ¹⁴ cm ⁻² .

At this time, the depth of the peak position of the impurity concentration in the p-type doped layer 12x is about 50 nm. Then, the concentration of indium in the surface portion of the active region is extremely low. The maximum impurity concentration of indium in the p-type doped layer 12x is about 1.0 × 10 ¹⁹ cm ⁻³ . The p-type impurity to be implanted at this time is not limited to indium. In particular, by using a heavy element such as indium, the surface portion of the active region (channel region)
, A pocket as a threshold control region having a high peak concentration can be formed below the impurity concentration.

Next, in the step shown in FIG. 5B, n-type impurities are ion-implanted into the active region using the gate electrode 5 as a mask, thereby forming n-type doped layers 6x and 7x on the surface of the active region. (First conductivity type region) is selectively formed. At this time, ion implantation is performed to such an extent that a shallow region of the active region becomes amorphous. For example, when arsenic is implanted at an implantation energy of 4 keV and a high dose of about 8.0 × 10 ¹⁴ cm ⁻² , the n-type doped layers 6x and 7x are made amorphous. The depth of the amorphized regions of the n-type doped layers 6x and 7x is about 40 nm, and is formed to be slightly shallower than the depth of the peak concentration (about 50 nm) of the p-type doped layer 12x. At this time, the p-type doped layer 12x
Most of the regions are changed to n-type doped layers 6x and 7x containing a high concentration of n-type impurities. However, since the implantation energy at the time of ion implantation of the p-type impurity is larger than the implantation energy at the time of ion implantation of the n-type impurity, a part of the p-type doped layer 12x remains below the n-type doped layers 6x and 7x. ing.

Next, in the step shown in FIG. 6A, heat treatment for activating the impurities in the p-type doped layer 12x and the n-type doped layers 6x and 7x is performed, so that the source extension 6 and the drain extension 6 are formed. 7 and the threshold control pocket 12 are formed. At this time, the amorphous region of the active region is recrystallized, and crystal defects occur in the recrystallized region. Since this crystal defect causes accelerated diffusion of impurities, FIG.
In the state shown in (b), the p-type impurity (indium) in the region remaining under the n-type doped layers 6x and 7x in the p-type doped layer 12x is removed from the source extension 6 and the drain extension 7 in the source extension 6 and the drain extension 7. It is thought that it is attracted to crystal defects. As a result, a threshold control pocket 12 is formed adjacent only to a portion of the source extension 6 and the drain extension 7 located below the channel, and a low concentration p-type is formed above the threshold control pocket 12. It is a channel region containing impurities.

Thereafter, in the step shown in FIG. 6B, a silicon oxide film is deposited and the silicon oxide film is etched back by anisotropic etching to form a side wall 8 on the side surface of the gate electrode 5. I do. Thereafter, n-type impurity ions such as arsenic, phosphorus or antimony are implanted into the active region using the gate electrode 5 and the side walls 8 as a mask. As a result, the source
Outside the extension 6 and the drain extension 7, the n-type source region 2 and the n-type drain region 3 having a deeper junction depth than the source extension 6 and the drain extension 7 are formed.

According to the manufacturing method of this embodiment, FIG.
In the step shown in FIG. 2A, the p-type impurity at a medium concentration is ion-implanted with relatively large implantation energy, so that the impurity concentration at the surface portion (channel region) of the active region can be kept low. Since this ion implantation can be performed using the same mask as the ion implantation for forming the extensions 6 and 7, the photolithography process does not increase.

At this time, by using a heavy element such as indium, the threshold control pocket 12 having a high peak concentration is formed below the impurity concentration at the surface portion (channel region) of the active region while keeping the impurity concentration low. Can be formed.

Next, in the step shown in FIG. 5B, when the n-type impurity (arsenic) is ion-implanted, the n-type doped layer 6
The peak position of the impurity concentration in x, 7x is the p-type doped layer 1
By implanting ions so as to be shallower than the peak position of the impurity concentration in 2x, a part of the p-type doped layer 12x is left below the n-type doped layers 6x and 7x. Then, annealing for activating the impurities is performed in the step shown in FIG. At this time, a crystal defect occurs when the amorphous region is recrystallized, and it is considered that this crystal defect causes the accelerated diffusion of the impurity.
As a result, the high-concentration p-type doped layer existing below the source extension 6 and the drain extension 7 in the p-type doped layer 12x disappears and is separated from each other only in a portion located below the channel. A threshold control pocket 12 is formed. And FIG.
In the step shown in FIG. 2B, the source region 2 and the drain region 3
Is formed, the threshold control pocket 12 does not come into contact with the source region 2 and the drain region 3.

Therefore, a MIS device having a miniaturized gate structure as shown in FIG. 4 can be easily realized without increasing the number of photolithography steps.

In this embodiment, FIG.
After ion implantation of a p-type impurity (indium) of a medium concentration in the step shown in FIG.
Although the ion implantation of the type impurity (arsenic) is performed, the ion implantation of the p-type impurity may be performed after the ion implantation of the n-type impurity.

(Experimental Data) FIG. 7 is a diagram showing an impurity concentration profile in the depth direction in a MIS device when ions are implanted for a p-type threshold control region and an n-type extension according to the method of the present invention. It is. FIG.
FIG. 4 is a diagram showing a depth-wise impurity concentration profile in a MIS device after heat treatment of a p-type threshold control region and an n-type extension according to the method of the present invention. Hereinafter, FIG.
The fact that the structure of the MIS device of the present invention can be obtained by the manufacturing steps in the first and second embodiments will be described with reference to FIGS. The data shown in FIG. 7 and FIG.
This is data of a region where ions are implanted under conditions different from those of the first and second embodiments.
The relationship between the concentration peak positions of the n-type doped layer and the n-type doped layer does not change.

As shown in FIG. 7, at the time of ion implantation, indium (In) ions are implanted at a higher energy than arsenic (As) ions, so that the peak position of the In concentration is higher than the peak position of the As concentration. (Around 15 nm)
Is below. Therefore, FIG. 2 (b), FIG.
As shown in (b), the p-type doped layers 11x and 12x
It exists below the mold dope layer (extension) 6x, 7x.

On the other hand, as shown in FIG. 8, after annealing after the ion implantation, arsenic diffuses below the active region. Further, at the same time as In diffuses downward, In is attracted to lattice defects caused by recrystallization of an amorphous region formed by arsenic ion implantation, and FIG.
In this case, the peak of the In concentration near the depth of 15 nm disappears. In the region where the peak of the In concentration is present, the In concentration is significantly lower than the arsenic concentration. As a result, as shown in FIGS. 3A and 6A,
Below the extensions 6 and 7, the high density threshold control region 11 and the threshold control pocket 12 do not exist.

The reason why the above phenomena occur is not yet completely elucidated.
It is as follows. In a region of the n-type doped layer that has been made amorphous by implantation of arsenic ions, the crystal is recovered by the heat treatment, and lattice defects occur in this process. FIG. 9 shows a TEM photographic image of a cross section near the extension at this time. As shown in the figure,
There are many lattice defects near the lower part of the region that has been made amorphous by implantation of arsenic ions. It is considered that diffusion of impurities is promoted by the lattice defect, and in particular, indium is attracted to the lattice defect, so that a high-concentration p-type region does not exist below the extension.

[0077]

According to the present invention, since a high-concentration threshold control region is provided adjacent only to a part of the lower portion of the extension, the function of preventing short channel effects is high, and
An MIS semiconductor device having a large current driving force can be realized.

[Brief description of the drawings]

FIG. 1 shows a MISFET according to a first embodiment of the present invention.
It is sectional drawing of the MIS device which has a structure.

FIGS. 2A and 2B show n in the first embodiment; FIGS.
FIG. 10 is a cross-sectional view showing the first half of the manufacturing steps of the MIS device having the MISFET structure.

FIGS. 3A and 3B show n in the first embodiment; FIGS.
FIG. 10 is a cross-sectional view showing a latter half of the manufacturing process of the MIS device having the MISFET structure.

FIG. 4 shows a MISFET according to a second embodiment of the present invention.
It is sectional drawing of the MIS device which has a structure.

FIGS. 5A and 5B show n in the second embodiment; FIGS.
FIG. 10 is a cross-sectional view showing the first half of the manufacturing steps of the MIS device having the MISFET structure.

FIGS. 6A and 6B show n in the second embodiment; FIGS.
FIG. 10 is a cross-sectional view showing a latter half of the manufacturing process of the MIS device having the MISFET structure.

FIG. 7 is a diagram showing an impurity concentration profile in a depth direction in a MIS device when ion implantation for a p-type threshold control region and an n-type extension is performed according to the method of the present invention.

FIG. 8 is a diagram showing an impurity concentration profile in a depth direction in a MIS device after heat treatment of a p-type threshold control region and an n-type extension according to the method of the present invention.

FIG. 9 is a TEM photograph showing a state of occurrence of lattice defects after heat treatment of a p-type threshold control region and an n-type extension according to the method of the present invention.

FIG. 10 is a cross-sectional view of a conventional n-channel MIS device having a local channel structure.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Si substrate (p-type) 2 source region 3 drain region 4 gate insulating film 5 gate electrode 6 source extension 6 x n-type doped layer 7 drain extension 7 x n-type doped layer 8 sidewall 9 element isolation and oxide film 11 threshold Value control region 11x p-type doped layer 12 threshold value control pocket 12x p-type doped layer 15 low concentration channel region

Claims (10)

[Claims] A first conductive type source region formed in the semiconductor substrate; a first conductive type formed in the semiconductor substrate and separated by a certain distance from the source region; A drain region of a mold, a channel region formed on the surface portion on the main surface side of the semiconductor substrate, located between the source region and the drain region, and a channel region formed on the main surface of the semiconductor substrate, A gate insulating film covering a region, a gate electrode formed on the gate insulating film, and a source depth provided between the source region and the channel region in the semiconductor substrate, and a junction depth of the source region. A source extension of a first conductivity type, which is shallower than the source extension, and a junction depth provided between the drain region and the channel region in the semiconductor substrate; Shallow first conductivity type drain extension than the junction depth of the region, is formed below the channel region in the above semiconductor substrate, while in contact with part of the lower portion of the source extension and the drain extension,
An MIS semiconductor device comprising: a second conductivity type threshold control region provided separately from the source / drain region. 2. The MIS type semiconductor device according to claim 1, wherein a peak of an impurity concentration of said threshold control region is located at a depth substantially equal to a junction depth of said source extension and said drain extension. A MIS type semiconductor device characterized by the above-mentioned. 3. The MIS type semiconductor device according to claim 1, wherein a region having the largest number of crystal defects exists near a lower portion of said source extension and said drain extension. Semiconductor device. 4. A semiconductor substrate having a main surface, a first conductivity type source region formed in the semiconductor substrate, and a first conductivity type formed in the semiconductor substrate and separated from the source region by a certain distance. A drain region of a mold, a channel region formed on the surface portion on the main surface side of the semiconductor substrate, located between the source region and the drain region, and a channel region formed on the main surface of the semiconductor substrate, A gate insulating film covering a portion excluding an end portion of the region; a gate electrode formed on the gate insulating film; a gate electrode provided between the source region and the channel region in the semiconductor substrate; A source extension of a first conductivity type, which is shallower than a junction depth of the source region, and a junction provided between the drain region and the channel region in the semiconductor substrate; A first conductivity type drain extension shallower than a junction depth of the drain region, a portion formed below the channel region in the semiconductor substrate, and in contact with a part of a lower portion of the source extension; An MIS semiconductor device comprising a second conductivity type threshold control region divided into a portion in contact with a part of a lower portion of the drain extension and provided apart from the source / drain region. 5. The MIS type semiconductor device according to claim 4, wherein the peak of the impurity concentration of the threshold control region is located at a depth substantially equal to the junction depth of the source extension and the drain extension. A MIS type semiconductor device characterized by the above-mentioned. 6. The MIS type semiconductor device according to claim 4, wherein a region having the largest number of crystal defects exists near a lower portion of the source extension and the drain extension. Semiconductor device. 7. A step of implanting impurity ions of the second conductivity type into the active region of the semiconductor substrate to form a second conductivity type region having a concentration profile of low concentration at the surface portion and high concentration at the deep portion (a). (B) forming a gate insulating film and a gate electrode on the semiconductor substrate sequentially; and implanting impurity ions of the first conductivity type into the active region using the gate electrode as a mask. (C) forming a first conductivity type region having an amorphized region shallower than the depth of the second conductivity type region on both sides of the gate electrode in the semiconductor substrate; By activating the conductivity type region and recovering the amorphous region at the same time, the source extension region and the drain extension region, and the source extension region Forming a threshold control region in contact with a lower portion of each of the region and the drain extension region (d)
A method for manufacturing a MIS semiconductor device, comprising: 8. The method of manufacturing a MIS type semiconductor device according to claim 7, wherein in the step (c), the peak position of the first conductivity type impurity concentration in the first conductivity type region is the second conductivity type. A method for manufacturing a MIS type semiconductor device, comprising: forming the first conductivity type region above a peak position of a second conductivity type impurity concentration in the region. 9. A step (a) of sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate, and implanting second conductivity type impurity ions into an active region of the semiconductor substrate using the gate electrode as a mask. (B) forming a second conductivity type region having a concentration profile of low concentration at the surface portion and high concentration at the deep portion on both sides of the gate electrode; Impurity ions of the conductivity type are implanted into the active region to form a first conductivity type region having an amorphous region shallower than the depth of the second conductivity type region on both sides of the gate electrode in the semiconductor substrate. (C) activating the first and second conductivity type regions by heat treatment and recovering the amorphous region at the same time as the source extension region and the drain region. (D) forming a pair of threshold control regions which are in contact with a part of each lower part of the source extension region and the drain extension region and are separated from each other. A method for manufacturing a semiconductor device. 10. The method of manufacturing a MIS type semiconductor device according to claim 9, wherein in the step (c), the peak position of the first conductivity type impurity concentration in the first conductivity type region is the second conductivity type. A method for manufacturing a MIS type semiconductor device, comprising: forming the first conductivity type region above a peak position of a second conductivity type impurity concentration in the region.