JP2004363636A5 - - Google Patents

Description

Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

The present invention relates to a method of manufacturing a semiconductor substrate and a method of manufacturing a semiconductor device required to obtain a semiconductor device including a high-speed, low power consumption field-effect transistor, particularly a field-effect transistor having strained Ge or strained SiGe as a channel layer. About.

The hole and electron mobilities of Ge subjected to compressive strain in a plane parallel to the substrate can exceed the hole and electron mobilities of Si in both p and n channels by selecting an appropriate plane orientation. Are known.

FIG. 13 shows one of the prior art transistor structures using the strain Ge as a channel (first conventional example) (see Patent Document 1) . This structure is obtained by forming p-Si on an n-type Si substrate 61.
_0.5 Ge _0.5 buffer layer 62, i-Si _0.5 Ge _0.5 Ge spacer layer 63, i-
Ge channel layer 64, i-Si _0.5 Ge _0.5 Ge spacer layer 65, p-Si _0.5 G
e _0.5 layer _{66, i-Si 1-x} Ge x layer (x = 0.5 → 0) ( SiGe cap layer) 6
7. A Ti Schottky gate electrode 68 is laminated. The source / drain region 6
9 are formed at both ends immediately below the gate electrode 68.

This structure is a so-called modulation-doped FET (MODFET), i-Ge channel layer 6
P-Si _0.5 Ge _0.5 buffer layer 62, i-Si _{0
. Since} carriers are supplied from the ₅ Ge _0.5 Ge spacer layer 65 to the channel layer 64 , the hole mobility does not decrease due to scattering by the doped impurities. Therefore, high-speed operation utilizing the high mobility of holes of strain Ge is said to be possible. A structure similar to this structure is also disclosed in Non-Patent Document 1.

Further, as another conventional technique, a transistor using strained Si subjected to in-plane tensile strain as a channel is also known. It is known that the carrier mobility of strained Si also exceeds Si in both the p and n channels similarly to the above-described strain Ge, so that these transistors have a larger mobility at the same gate size than the transistor of the Si channel. Driving force is obtained. Among them, FIG. 14 shows a transistor structure which is considered to be most practical (second conventional example). This structure is a structure proposed and verified by a research group including the present inventors (see Non-Patent Document 2).

In this structure, a buried oxide film 72 and a SiGe buffer layer 7 are formed on a Si or SiGe layer 71.
3. The strained Si channel layer 74, the gate oxide film 75, and the gate electrode
Source / drain regions 77 are formed in the iGe buffer layer 73 and the strained Si channel layer 74.

In this structure, in addition to the high carrier mobility due to the strained Si channel 74, the presence of the buried oxide film 72 can reduce the parasitic capacitance and increase the driving force because miniaturization can be performed while keeping the impurity concentration low. It has merits. Therefore, when a CMOS logic circuit is configured with this structure, higher-speed operation with lower power consumption becomes possible.

As a method for manufacturing a semiconductor substrate having a high Ge composition SiGe layer on an oxide film, such as a SiGe buffer layer 73 on an oxide film as shown in FIG. 14, (1) a thin film SOI (Silicon)
on Insulator) (see Non-Patent Document 3),
2) A method in which an oxide film formed on a Si substrate and a laminated structure of SiGe epitaxially grown on the Si substrate are bonded to each other, and a part of the SiGe laminated structure is removed later (Patent Document 2)
, 3), and (3) a method of producing a SiGe crystal on an oxide film by oxygen ion implantation and annealing (SIMOX method) used in the process of producing the second conventional example.
JP-A-2-196436 E. Murakami et al., IEEE Transaction on Electron Devices, Vol. 41, p. 857 (1994), and YH Xie et al., Applied Physics Letters Vol. 63, p. 2263 (1994). T. Mizuno, S. Takagi, N. Sugiyama, J. Koga, T. Tezuka, K. Usuda, T. Hatakeyama, A. Kurobe, and A. Toriumi, IEDM Technical Digests p. 934 (1999) AR Powell et al., Appl. Phys. Lett. 64, 1856 (1994) Patent No. 3037934 Japanese Patent No. 2908787

First, a problem that arises when the first conventional example is put to practical use is that a source-drain junction leak is large. In the structure of the first conventional example, the thickness of the SiGe buffer layer 62 is a considerably large value of 500 nm, but in other similar conventional examples, the thickness is several hundred nm to about 1 μm or more. . This is the SiGe buffer layer 6
2 is a thickness necessary for sufficiently reducing the dislocation density and thereby reducing the dislocation density reaching the channel layer 64. At this time, the lower portion of the source / drain diffusion region 69 and the SiGe buffer layer 6
2 at the p ⁺ -n junction (for p-channel) or n ⁺ -p junction (for n-channel)
Is formed ) .

Here, since the Ge composition of the SiGe buffer layer 62 is as high as about 50 atm% or more, the value of the band gap is about 75 to 60% of the value of the band gap of Si. The reverse bias saturation current of the pn junction is represented by the sum of the diffusion current and the recombination current. Each component is proportional to the square of the intrinsic carrier density and the square of the intrinsic carrier density, respectively. The intrinsic carrier density increases as the band gap energy decreases. For example, the intrinsic carrier density of Ge is 1000 times or more larger than that of Si. Therefore, there arises a problem that the junction leak or the off current between the source / drain region 69 and the SiGe buffer layer 62 in the first conventional example is two to four orders of magnitude larger than that of Si. In consideration of the leakage current via the dislocation in the SiGe buffer layer 62, the off-state current is further increased. This causes a problem of a large increase in power consumption when a large-scale circuit is formed. If this leakage is to be reduced, SiGe having a low Ge composition should be used.
When the buffer layer 62 is used, the lattice constant difference between the buffer layer 62 and the Ge channel layer 64 increases,
Dislocations occur in the channel or the surface becomes uneven to release the strain. Therefore, in the first conventional example, since the thick SiGe buffer layer 62 having a Ge composition of 50 atm% or more must be used, the leakage between the source and the drain or between the drain and the substrate is smaller than that of the Si-based transistor. It is inevitable that it will be several orders of magnitude larger.

Next, problems of the second conventional example will be described. FIG. 3B shows a band structure near a channel according to the second conventional example. As can be seen from FIG. 3B, the strained Si channel layer 7
4 has a lower valence band energy than the valence band edge of the SiGe buffer layer 73. Therefore, when a negative bias is applied to the gate to form a hole channel, the strain is generated before the surface channel is formed. A buried channel is formed at the interface between the Si channel layer 74 and the SiGe buffer layer 73.

FIG. 15 shows the current (log (Id) −) of the transistor and the Si-MOSFET of the second conventional example.
3 shows a voltage (Vg) curve. Due to the presence of the aforementioned buried channel, as shown in FIG.
The characteristics near the threshold voltage deteriorate (the S factor increases). The influence of the buried channel becomes more remarkable as the thickness of the strained Si channel layer 74 becomes smaller. That is, the effect becomes larger as the size is reduced. Therefore, it is difficult to set the threshold voltage low when fabricating a fine MOSFET.

FIG. 16 shows (Vg (gate voltage) -Vth (threshold voltage))-current characteristics of the second conventional transistor and the Si-MOSFET. The mobility of this buried channel is SiG
The mobility is low due to alloy scattering in the e-buffer layer. Therefore, as shown in FIG. 16, in the second conventional example, the driving force is lower at a low gate voltage than the driving force of a normal surface channel Si-MOSFET. For the above reasons, it is difficult to reduce power consumption in the second conventional example.

SUMMARY OF THE INVENTION An object of the present invention is to provide a field-effect transistor that has a small leakage current between a source and a drain or between a drain and a substrate and that can reduce power consumption.

Another object of the present invention is to provide a semiconductor substrate on which the field effect transistor can be easily obtained.

Regarding the manufacturing method of the SiGe layer on the oxide film, first, in the method (1), since the underlying SOI is required, the thickness of the semiconductor layer on the oxide film is increased by that amount, and the FET is manufactured. In this case, it becomes difficult to shorten the channel. Further, when SiGe is epitaxially grown on the SOI and an annealing process is performed to relax the dislocation, dislocation occurs in the SOI layer.

In the method (2), a SiGe buffer layer having a thickness of several μm is grown on a Si substrate, and a SiGe thin film having a desired composition is formed thereon. In this case, inevitably a surface undulation called a cross hatch having a period of about 1 μm is generated. Furthermore, it is difficult to completely remove dislocations remaining in the buffer layer, and there is a problem that dislocations are generated at a density of about 10 ⁶ cm ⁻² near the surface. As the Ge composition increases, the dislocation density tends to increase.

In the case of (3), when the Ge composition is increased, Ge is combined with oxygen at the time of annealing to evaporate, so that a continuous buried oxide film is not formed or the surface is roughened.

The present invention suppresses an increase in the thickness of the laminated structure on the oxide film, generation of dislocations, or surface roughness even when the Ge composition is high (30 atm% or more) in manufacturing a SiGe layer on the oxide film. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that can perform the above-mentioned steps.

The first method of manufacturing a semiconductor substrate according to the present invention includes a step of forming a laminated structure in which an insulating film and a semiconductor layer containing Si and Ge are sequentially laminated on a supporting base; Forming a first semiconductor layer comprising a SiGe layer having a higher Ge composition than the semiconductor layer on the insulating film, and a Si oxide film located on the first semiconductor layer. ,
Removing the Si oxide film; and forming a G layer on the first semiconductor layer from the first semiconductor layer.
A method for manufacturing a semiconductor substrate, comprising performing a step of stacking a second semiconductor layer including a SiGe or Ge layer having a high e composition.

According to a second method of manufacturing a semiconductor substrate of the present invention, a method of manufacturing a semiconductor substrate comprising the steps of:
Forming a semiconductor layer containing Si and Ge on the layer or the SiGe layer, and oxidizing the semiconductor layer to provide a first layer having a SiGe layer having a higher Ge composition than the semiconductor layer on the insulating film. Forming a semiconductor layer and a Si oxide film located on the first semiconductor layer; removing the Si oxide film; and forming the first semiconductor layer on the first semiconductor layer. A method for manufacturing a semiconductor substrate, comprising performing a step of stacking a second semiconductor layer including a SiGe or Ge layer having a higher Ge composition.

The present invention also provides a step of sequentially laminating a gate insulating film and a gate electrode film on the semiconductor substrate obtained by the first method for manufacturing a semiconductor substrate;
Performing a process of forming a gate insulating film and a gate electrode and forming a source / drain region;
A method for manufacturing a semiconductor device, comprising forming a field effect transistor having a channel formed in the second semiconductor layer of the semiconductor substrate.

Further, the present invention provides a step of sequentially laminating a gate insulating film and a gate electrode film on the semiconductor substrate obtained by the second method for manufacturing a semiconductor substrate;
Performing a process of forming a gate insulating film and a gate electrode and forming a source / drain region;
A method for manufacturing a semiconductor device, comprising forming a field effect transistor having a channel formed in the second semiconductor layer of the semiconductor substrate.

According to the semiconductor device and the semiconductor substrate obtained by the present invention, it is possible to obtain a MISFET capable of operating at high speed with lower power consumption than the Si-MOSFET. In addition, these MISFE
By using T, an integrated circuit capable of operating at higher speed with lower power consumption than the conventional one can be obtained.

According to the method of manufacturing a semiconductor substrate of the present invention, a SiGe layer having a low Ge dislocation density and a high Ge composition with lattice relaxation is formed.

An embodiment of a field-effect transistor obtained by applying the method for manufacturing a semiconductor device of the present invention includes a support base, an insulating film formed on the support base, a source region formed on the insulating film, and a source region. A semiconductor layer in which a drain region is formed, a gate insulating film formed on the semiconductor layer, and a field-effect transistor including a gate electrode formed on the gate insulating film, wherein the semiconductor layer is Ge composition provided on the side in contact with the insulating film is 30 atm%
The semiconductor device includes the above-described SiGe region and a SiGe or Ge channel region provided on the surface opposite to the insulating film and having a higher Ge composition than the SiGe region.

SiGe having a Ge composition of 30 atm% or more is a compound represented by Si _1-x Ge _x (1> x ≧ 0.3) .

FIG. 1 is a schematic diagram illustrating an example of a field-effect transistor. An insulating film 2 is formed on a supporting base 1, and a semiconductor layer is formed on the insulating film 2. The insulating film 2 electrically insulates the support base 1 from the semiconductor layer, and includes, for example, a Si oxide film. The semiconductor layer includes a SiGe buffer layer 3 (first semiconductor layer) having a high Ge composition having a Ge composition of 30 atm% or more, and a channel layer 4 composed of a SiGe layer having a Ge composition higher than the first semiconductor layer or a Ge layer ( (A second semiconductor layer). The substrate 5 includes the support base 1
, An insulating film 2, a first semiconductor layer, and a second semiconductor layer. Source / drain regions 6 are formed on the substrate 5 and connected to a source electrode (not shown) and a drain electrode (not shown), respectively. Further, the gate insulating film 7 and the gate electrode 8 are stacked to form a field effect transistor.

That is, in the field effect transistor, the SiGe buffer layer 3 having a high Ge composition and the channel layer 4 made of a Ge layer or a SiGe layer are stacked on the insulating film 2. Thereby, the leak current between the source and the drain, which has conventionally been a problem, can be suppressed to a practical level. Further, an integrated circuit capable of low power consumption and high speed operation utilizing the high mobility of the Ge or SiGe channel can be obtained.

  This will be described in more detail below.

In the channel layer 4 formed on the SiGe buffer layer 3, strain is introduced into the crystal structure due to a difference in lattice constant between the SiGe buffer layer 3 and the channel layer 4. Thereby, the hole and electron mobilities in the channel layer 4 greatly exceed the hole and electron mobilities of Si, and the device can be operated at high speed. The strain may not be introduced in the channel layer 4. Even in such a case, the mobility of electrons and holes is sufficiently higher than that of Si. However, the mobility of electrons and holes is higher when strain is introduced.

FIG. 2 is an enlarged view of a pn junction of a source region or a drain region in the field effect transistor according to the first related art and the first embodiment. FIG. 2A is an enlarged view of a pn junction of a source region or a drain region of the field effect transistor according to the first conventional example shown in FIG. FIG. 2B is an enlarged view of a pn junction of a source region or a drain region in the substrate of the field-effect transistor according to the embodiment shown in FIG. In the field-effect transistor of the present invention shown in FIG. 2B, the source / drain regions 6 are formed in the SiGe buffer layer 3 and the channel layer 4 formed on the insulating film 2. The presence of the insulating film 2 completely suppresses a leak current to the supporting base. Further, the area of the pn junction surface is greatly reduced, and the channel layer 4 and the SiGe buffer layer 3 are formed by applying a gate voltage.
Are depleted, the leakage current between the source and the drain is significantly reduced as compared with the first conventional example.

On the other hand, in the substrate of the first conventional field effect transistor shown in FIG. 2A, the i-Ge channel layer 64 and the SiGe cap layer 67 are stacked on the thick (> 500 nm) buffer layer 62. I have. Further, a source or drain region 69 is formed. In FIG. 2A, since the insulating film 2 as in FIG. 2B does not exist, a leak to the supporting base occurs. In addition, because of the large area of the pn junction and the transition remaining in the buffer layer 62, the leak current between the source and the drain becomes significantly larger than that in the present embodiment.

FIG. 3A shows a band structure near the channel layer of the field-effect transistor according to the present embodiment. With the configuration according to the present invention, as can be seen from FIG. 3A, the energy of the valence band of the channel layer 4 is larger than the energy of the valence band edge of the SiGe buffer layer (Si _0.3 Ge _0.7 ) 3. Therefore, if a negative bias is applied to the gate electrode to form a hole channel, only the surface channel is formed. Therefore, the characteristic near the threshold voltage does not deteriorate due to the absence of the buried channel as in the second conventional example, and the threshold voltage can be set low. Further, the driving force at a low gate voltage can be increased. For the above reasons, low power consumption can be realized in the present invention.

In the conventional Si-MOSFET, an SOI substrate having a similar structure is used, but this is mainly intended to increase the speed by reducing the parasitic capacitance between the substrate and the wiring and the junction capacitance of the region. . The role of the insulating film 2 in the present embodiment is to suppress the off current for the SiGe or Ge channel layer, which is essential for practical use, whereas the conventional Si-MO
SFETs only provide additional functionality.

In the field effect transistor of the present embodiment, it is desirable that the dislocation density of the SiGe buffer layer 3 (first semiconductor layer) is 10 ⁶ cm ⁻² or less. The element or L
The yield of SI can be set to a practical level. The dislocation density is more preferably 10 ⁴
cm ⁻² or less.

Further, when the Ge composition distribution of the SiGe buffer layer 3 (first semiconductor layer) in the depth direction is substantially uniform, no strain is accumulated in the SiGe buffer layer 3 so that the transition hardly occurs. Therefore, in order to reduce the dislocation density, it is desirable that the Ge composition of the SiGe buffer layer 3 (first semiconductor layer) be substantially uniform in the depth direction distribution.

In the field-effect transistor of this embodiment, it is desirable that a Si cap layer is provided between the channel layer 4 (second semiconductor layer) and the gate insulating film 7. This prevents oxidation of the SiGe or Ge surface during the manufacturing process of the field effect transistor. Further, it is possible to prevent the interface with the gate insulating film 7 from being formed in SiGe or Ge, thereby preventing an increase in the interface state. Further, if the thickness of the Si cap layer is less than the critical thickness (minimum thickness at which dislocations occur due to lattice constant mismatch) with respect to the SiGe buffer layer 3, no dislocations occur. With these effects, the carrier mobility can be kept high.

The semiconductor substrate of the present embodiment is used for manufacturing the field-effect transistor according to the present embodiment, and is a semiconductor substrate having two layers of a high Ge composition corresponding to the SiGe buffer layer 3 and the channel layer 4. If a field-effect transistor is manufactured using the semiconductor substrate of the present embodiment, the leakage current between the source and the drain or between the drain and the substrate is small,
Further, a field-effect transistor capable of high-speed operation and low power consumption can be provided.

In the semiconductor substrate of the present embodiment, the dislocation density of the SiGe buffer layer 3 (first semiconductor layer) is desirably 10 ⁶ cm ⁻² or less. Thereby semiconductor devices or LSI
Can be set to a practical level. The dislocation density is more preferably 10 ⁴ cm
^-2 or less.

In the semiconductor substrate of the present embodiment, the Ge of the SiGe buffer layer 3 (first semiconductor layer)
It is preferred that the depth distribution of the composition be substantially uniform.

Further, for example, for the field-effect transistor according to the present embodiment, a semiconductor substrate on which a SiGe layer having a high Ge composition (30 atm% or more) is formed as a SiGe buffer layer is required. First and second used for manufacturing a semiconductor substrate having the high Ge composition SiGe layer
In the method of manufacturing a semiconductor substrate described above, a semiconductor comprising a low Ge composition Si and Ge layer directly on an insulating film formed on a supporting base or on a Si layer or a SiGe layer formed on the insulating film By forming a layer and performing an oxidation treatment, specifically, a heat treatment in an oxidizing atmosphere, a SiGe film having a high Ge composition in which Ge is concentrated is formed simultaneously with the formation of a Si oxide film.

That is, by oxidizing a semiconductor layer including a low Ge composition Si and a Ge layer, a low G composition is obtained.
Si atoms are selectively oxidized from the surface of the semiconductor layer including Si and Ge layers having an e composition to form a Si oxide film, and Ge atoms are discharged from the formed Si oxide film, and the inside of the semiconductor layer is removed. It is accumulated in a semiconductor layer containing Si and Ge. This is because the bond between the SiO ₂ SiO
This is because oxygen atoms are preferentially bonded to Si atoms because they are chemically more stable than Ge—O bonds of GeO ₂ or GeO. Therefore, Ge is concentrated and SiGe of high Ge composition is
A layer and a Si oxide film are formed.

The Si oxide film generated at this time may be removed as needed. Further, a step of forming a channel layer and the like is performed as necessary.

According to the first and second manufacturing methods of the present invention, the semiconductor layer containing Si and Ge is oxidized, specifically, heated in an oxidizing atmosphere, so that the semiconductor layer containing Ge and Si contains Ge. , And the Ge concentration in the generated SiGe layer becomes uniform. If this layer is used, for example, as a SiGe buffer layer in the field-effect transistor according to the present embodiment, Ge
No distortion occurs inside the SiGe buffer layer due to the non-uniform composition. As a result, the dislocation density can be suppressed to 10 ⁶ cm ⁻² or less after sufficient lattice relaxation.

This will be described with reference to FIGS. FIG. 4 is a view for explaining the Ge composition distribution during the oxidation of the semiconductor layer containing Si and Ge in the method for manufacturing a semiconductor substrate according to the present invention. Whether Ge atoms diffuse or Ge atoms are accumulated at the interface in the semiconductor layer _{(Si 1-x} Ge _x) containing Si and Ge, roughly speaking, the diffusion length of the Ge per unit time by oxidation SiGe
Can be considered to be determined by the magnitude relation of the thickness (consumption rate) consumed. If the diffusion length is larger than the consumption rate, Ge diffuses into the SiGe layer and the Ge composition becomes uniform in the depth direction, and if the reverse, the Ge accumulates at the interface (FIG. 4).

FIG. 5 is a diagram showing the relationship between the diffusion length of Ge atoms in Si and the thickness at which SiGe is consumed per unit time due to oxidation. FIG. 5A shows that the diffusion length is always higher than the consumption rate if the ambient gas is 100% O ₂ and the temperature is 950 ° C. or higher.

However, when looking at the consumption rate immediately after oxidation, the value is almost the same as the diffusion length even at 950 ° C. or higher, and Ge is accumulated to some extent at the interface immediately after oxidation. There is no problem if the film thickness of the accumulation region is sufficiently smaller than the critical film thickness. In order to reduce the risk of dislocation generation immediately after such oxidation, the consumption rate may be reduced without changing the temperature (that is, without changing the diffusion length). Therefore, it is desirable to use an oxygen gas diluted with an inert gas as the atmosphere gas. Since the consumption rate is almost proportional to the oxygen partial pressure, the use rate of oxygen gas diluted to 50% is almost halved, and a sufficiently large margin is obtained for the diffusion length (FIG. 5B). Therefore, it is desirable to use oxygen gas diluted to 50% or less.

Further, according to the first and second manufacturing methods of the present invention, the Si oxide film becomes viscous fluid and S
The interface between the iGe layer and the Si oxide film becomes slippery, and the increase in the lattice constant accompanying the increase in the Ge composition of the SiGe layer is not prevented. Due to these effects, Ge enrichment, thinning, and lattice relaxation can be simultaneously achieved without generating dislocations. Also, the surface roughness is reduced.

As a result, when a channel layer is further formed on the obtained SiGe layer, a channel layer having a lower dislocation density can be obtained as compared with the conventional method, so that the carrier mobility can be kept high, and It is possible to provide a field-effect transistor capable of suppressing a leak current.

(Example 1)
FIG. 6 shows a schematic diagram of the field effect transistor of the first embodiment. In this embodiment, a (001) Si substrate is used as the support substrate 11, a buried oxide film as the insulating film 12, an SiGe buffer layer 13 as the first semiconductor layer, and a strain as the second semiconductor layer on the support substrate. A gate insulating film 17 and a gate electrode 18 are sequentially laminated on a semiconductor substrate 16 on which a channel layer 14 made of Ge and a Si cap layer 15 are laminated. SiGe buffer layer 13 and channel layer 1
At both ends of the gate region in FIG. 4, a source region and a drain region 19 for obtaining ohmic contact with the source and drain electrodes, and a metal reaction layer 20 are formed.

In the field-effect transistor according to the present embodiment, the plane orientation of the Si substrate 11 used as the support base 11 is not limited to (001) but may be other plane orientations, for example, a (111) substrate.
A (110) substrate may be used.

In the field-effect transistor according to the present embodiment, it is desirable that the channel layer 14 has a thickness of 3 nm or more. The reason why a thickness of 3 nm or more is required is that most of the carriers are confined in the channel layer 14. That is, the width in the depth direction of the inversion layer channel formed immediately below the gate insulating film 17 is about 5 nm, and the thickness of the channel layer 14 needs to be at least 3 nm even in consideration of the thickness of the Si cap layer 15. Become.

Further, the thickness of the channel layer 14 has an upper limit depending on the critical thickness according to the Ge composition of the SiGe buffer layer 13. For example, when the Ge composition is 70 atm%, the upper limit of the thickness of the channel layer 14 is 5 nm.

In the field effect transistor according to the present invention, the thickness of the SiGe buffer layer 13 can be arbitrarily set in principle. However, when fabricating a field-effect transistor having a gate length of 100 nm or less, the channel layer 14 and the SiGe buffer layer 13 are required to suppress the short channel effect.
Is preferably 35 nm or less in the channel region.

In the field-effect transistor of this embodiment, the Ge composition of the SiGe buffer layer 13 is 30 atm.
% Or more. This is because if the Ge composition contained in the SiGe buffer layer 13 is less than 30 atm%, the strain of the channel layer 14 increases and a flat film having a thickness of 3 nm or more cannot be obtained.

More desirably, at least 60 atm% is desirable. This is because if the Ge composition of the SiGe buffer layer 13 is less than 60 atm%, dislocation may occur in the channel layer 4 if the channel layer 14 is stacked to 3 nm or more. This is because the Ge composition of the SiGe buffer layer 13 is 60 at.
This is because the critical thermodynamic film thickness of Ge with respect to m% is 3 nm.

A more desirable range of the Ge composition is 60 atm% or more and 80 atm% or less. This upper limit value of 80 atm% is a set value for enjoying the effect of increasing the hole mobility due to strain. That is, if the Ge composition is 80 atm% or less, the phonon scattering mobility of holes becomes twice or more the mobility for unstrained Ge due to the effect of strain applied to the channel layer 14.

In the field effect transistor of this embodiment, the channel layer 14 is a Ge layer, but may be a SiGe layer having a higher Ge composition than the SiGe buffer layer 13 instead of Ge. Since the carrier mobility increases as the Ge composition of the channel layer 14 increases, a channel layer made of a Ge layer is most desirable.

In the field-effect transistor according to the present embodiment, it is desirable that an extremely thin Si cap layer 15 is laminated between the channel layer 14 and the gate insulating film 17 in order to protect the surface of the channel layer 14. The Si cap layer 15 on the channel layer 14 prevents oxidation of the Ge surface in the transistor manufacturing process. Further, the interface with the gate insulating film 17 is
To prevent the formation of the inside, thereby preventing the interface level from increasing. The thickness of the Si cap layer 15 is desirably 2 nm or less so as not to cause dislocation. This is because the critical thermodynamic thickness of the Si cap layer is 2 nm when the Ge composition of the SiGe buffer layer 13 is 80 atm%.
Because it is.

Further, the thickness of the Si cap layer 15 is preferably as small as possible, but is preferably 0.5 nm or more in consideration of fluctuation of the film thickness.

A structure without the Si cap layer 15 is also possible. In this case, a Ge nitride film may be used as the gate insulating film 17 in addition to the materials described below. This Ge nitride film can be obtained not only by deposition by CVD, but also by directly nitriding the Ge surface with ammonia gas or nitrogen gas.

In the field-effect transistor according to the present embodiment, a stacked film of Zr silicate / ZrO ₂ as shown in FIG. 7 can be used as the gate insulating film 17. In FIG. 7, a ZrO ₂ layer 22 is laminated on a Zr silicate layer 21. Here, silicate is Zr in SiO ₂
, Hf, La and the like are metals in a solid solution.

The material of the gate insulating film 17 is not only a Si oxide film (SiO ₂ ) but also a Si nitride film (Si ₃ N ₄ ) , a Si oxynitride film (SiO _x N _y ) , Al ₂ O ₃ , and Ta ₂ O _5. , TiO ₂
, Ya ₂ O ₃ or other high dielectric gate insulating films can also be used.

The thickness of the source region and the drain region 19 must be suppressed to 35 nm or less when the gate length is 100 nm or less. At this time, the parasitic resistance due to the thin source / drain region increases as it is. In order to suppress this, the resistance of the source / drain region can be suppressed low by using a compound 20 (silicide, germanide) of Si and Ge and a metal (Co, Ti, Ni) up to the vicinity of the lower portion of the gate side wall.

As the gate electrode 18, p-type or n-type doped poly-Si or poly-Si
Ge can be used. It is also possible to use a metal such as W.

  Next, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIGS.

First, a UHV-CVD method or an MBV method is performed on an SOI substrate 34 (SOI film 33 having a thickness of 20 nm) in which a buried oxide film 32 and an SOI film 33 are formed on a Si layer 31 serving as a support base.
The E _0.9 or the LP-CVD method is used to form a Si _0.9 Ge _0.1 film 35 of 56 nm and a Si layer 36 of 5 nm.
The epitaxial growth is performed in nm. At this time, dislocation does not occur by making each film thickness less than the critical film thickness at the growth temperature [FIG. 8 (1)]. At this time, instead of the SOI substrate 34, a substrate in which an oxide film is formed on a Si substrate, or a substrate in which an oxide film and a SiGe layer are sequentially formed on a Si substrate may be used.

Next, the wafer is put into an oxidation furnace and heated to perform an oxidation treatment. As a result, Si _{0
. 9} Ge _0.1 layer SiGe layer containing more Ge than 35 _(Si 0.3 _{Ge 0.7} layer)
37 and a Si oxide film 38 are formed. Heating is performed using oxygen gas diluted to 50% with nitrogen.
Oxidation is performed at 000 ° C. for 16 hours until the generated SiGe layer 37 has a thickness of 8 nm. Alternatively, after oxidizing at 1000 ° C. and 50% oxygen for 3 hours, switching to 100% oxygen for another 8 hours 20
It oxidizes. Alternatively, after oxidizing with 1050 ° C. and 50% oxygen for 1 hour and 23 minutes, the temperature is raised to 1000
C. and oxidize with 100% oxygen for 8 hours and 20 minutes. As a result of the oxidation, the Ge composition of the SiGe layer 37 is concentrated to 70 atm% [FIG. 8 (2)].

Here, care must be taken that the oxidation temperature does not exceed the melting point of the SiGe layer 37.
As in this embodiment, the final oxidation temperature must be 1025 ° C. or less in order to obtain a SiGe layer 37 containing 70 at% Ge of Ge. In order to shorten the oxidation time, it is effective to set the temperature to a high value at first, and gradually or gradually decrease the temperature within a range not exceeding the melting point corresponding to the Ge composition in the SiGe layer 37. is there.

Next, after removing the Si oxide film 38 and cleaning the surface, the SiGe buffer layer 37 having a composition of Si _0.3 Ge _0.7 having a thickness of 5 nm is again formed by the UHV-CVD method, the MBE method, or the LP-CVD method. ', A Ge channel layer 39 of Ge having a thickness of 5 nm is sequentially formed.

Subsequently, an amorphous Si layer 40 as a Si cap layer is
nm. In order to deposit amorphous Si, the substrate temperature may be reduced to 300 ° C. or lower, and then the Si raw material (Si atom or silane gas or disilane gas) may be supplied [FIG.
(3)]. By depositing the Si layer 40 in an amorphous state on the Ge channel layer 39, the formation of surface irregularities and islands due to lattice mismatch can be prevented, and a flat surface can be obtained. This amorphous Si layer is crystallized in a later step. At this time, since the surface of the Si layer is covered with an oxide film, the surface flatness is maintained even when Si is crystallized. Therefore, when the field-effect transistor is formed, the carrier mobility can be kept high.

On the other hand, when Si is directly epitaxially grown on the Ge channel layer 39, surface irregularities and islands due to lattice mismatch are formed, which is not desirable.

Next, about 0.5 nm of Si is applied to the surface of the amorphous Si layer 40 with a mixed solution of hydrochloric acid and hydrogen peroxide.
After forming an oxide film (not shown), a ZrO ₂ film 41 is deposited as a gate insulating film by laser ablation or sputtering, and subsequently a poly-SiGe gate electrode 42 is deposited [
FIG. 8 (4)]. At this time, since the substrate temperature becomes 500 ° C. or higher, the amorphous Si layer 40 is crystallized by solid phase growth.

The source / drain regions 43 and the like are formed on the wafer thus obtained,
The transistor is processed in the same manner as the OSFET process [FIG. 8 (5)].

Here, another method for obtaining the structure having the SiGe layer 37 having a high Ge composition shown in FIG. First, graded composition Si _1-x Ge _x layer having a thickness of 1μm on the Si substrate (x = 0 → 0
. 1) A 1.5 μm thick Si _0.9 Ge _0.1 layer and a 20 nm thick Si layer were UHV-C
The layers are stacked by the VD method, the MBE method, or the LP-CVD method.

Next, oxygen ions are accelerated at an acceleration voltage of 160 keV and a dose of 4 × 10 ¹⁷ atoms / cm.
^{2 is} implanted and a thermal oxide film is formed on the surface at 900 ° C. to a thickness of 10 nm or more. S to implant oxygen ions
The reason why the Ge composition of the iGe layer is as low as 10 atm% is to obtain a continuous and uniform buried oxide film. When the Ge composition is 30 atm% or more, a continuous buried oxide film cannot be obtained by this method [Y. Ishikawa et al., Appl. Phys. Lett., 75, 983 (1999)].

Next, when annealing is performed at 1300 ° C. for 4 hours in an argon gas atmosphere containing a small amount (0.5%) of oxygen, a buried oxide film is formed on the substrate side from the oxide film-SiGe interface by 300 nm. Ge is excluded from this buried oxide film, and it becomes almost pure SiO ₂ . Next, the wafer is etched with a mixed solution of hydrofluoric acid and nitric acid until the SiGe layer becomes 56 nm.

Next, when the SiGe layer is oxidized to 8 nm in an oxygen atmosphere, the Ge composition becomes 70 atm.
%, And the structure of FIG. 8B is obtained.

(Example 2)
FIG. 9 shows a schematic view of the field-effect transistor of the second embodiment. In this embodiment,
In order to suppress an increase in the parasitic resistance caused by the thin film thickness of the source / drain regions, in the transistor shown in FIG. It is covered with.

(Example 3)
FIG. 10 is a schematic view of a field-effect transistor according to the third embodiment. In this embodiment, in order to suppress the parasitic resistance, in the transistor shown in FIG. 6 of the first embodiment, a Si _0.3 Ge _0.7 layer 51 is selectively deposited on the source / drain region 19, The thickness of the drain region is increased to 100 nm. In order to fabricate this structure, an SiO ₂ mask is temporarily deposited on the entire surface, only the upper surface of the source / drain region is exposed, and a SiGe layer may be deposited by a selective CVD method.

(Example 4)
FIG. 11 is a schematic view of a field-effect transistor according to the fourth embodiment. In the present embodiment, in the transistor shown in FIG. 6 of the first embodiment, the SiGe buffer layer 13 has a two-layer structure. On the first buffer layer 52 having a Ge composition of 55 atm% and a thickness of 5 nm formed by oxidation, a second buffer layer 53 having a Ge composition of 75 atm% and a thickness of 10 nm is laminated. According to the present embodiment, the strain applied to the Ge channel is increased by the presence of the second buffer layer.
Of the buffer layer alone. Therefore, the Ge composition of the first buffer layer can be reduced as compared with the first embodiment, so that the margin for controlling the film thickness during oxidation increases,
The yield is improved.

As a modification of this embodiment, a structure in which the Ge composition of the second buffer layer increases continuously or stepwise as approaching the surface is possible.

(Example 5)
FIG. 12 shows an example in which the field effect transistor shown in the first embodiment shown in FIG. 6 is applied to a CMOS inverter. The p-channel and n-channel MOSFETs are insulated by a trench reaching the buried oxide film. The substrate 11 is biased so as to function as a back gate for adjusting a threshold.

FIG. 1 is a schematic diagram illustrating an embodiment of a field-effect transistor. FIG. 4 is an enlarged view of a pn junction of a source region or a drain region in the field-effect transistor according to the first related art and the embodiment of the present invention. FIG. 7 is a diagram showing a band structure near a channel layer of a field-effect transistor according to an embodiment of the present invention and a second conventional technique. FIG. 4 is a diagram illustrating a Ge composition distribution during oxidation of a semiconductor layer containing Si and Ge in the method for manufacturing a semiconductor substrate according to the present invention. The figure which shows the relationship between the diffusion length of Ge atom in Si, and the thickness which SiGe is consumed per unit time by oxidation. FIG. 1 is a schematic diagram of a field-effect transistor according to a first embodiment. FIG. 3 is a schematic view illustrating an example of a gate insulating film. FIG. 4 is a process chart illustrating a method for manufacturing the field-effect transistor of the present embodiment. FIG. 4 is a schematic diagram of a field-effect transistor according to a second embodiment. FIG. 9 is a schematic diagram of a field-effect transistor according to a third embodiment. FIG. 9 is a schematic diagram of a field-effect transistor according to a fourth embodiment. FIG. 2 is a schematic diagram showing an example in which the field-effect transistor shown in the first embodiment is applied to a CMOS inverter. FIG. 4 is a schematic diagram showing a first conventional example of a field-effect transistor structure. FIG. 9 is a schematic diagram showing a second conventional field-effect transistor structure. FIG. 14 is a characteristic diagram showing a relationship between current (log (Id) -voltage (Vg)) of a transistor and a Si-MOSFET according to a second conventional example. FIG. 9 is a characteristic diagram showing a relationship between (Vg (gate voltage) -Vth (threshold voltage))-current of the transistor of the second conventional example and the Si-MOSFET.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... Support base 2 ... Insulating film 3 ... SiGe buffer layer (first semiconductor layer)
4 ... Channel layer (second semiconductor layer)
Reference numeral 5: substrate 6, source region, drain region 7, gate insulating film 8, gate electrode 11, support base 12, insulating film 13, first semiconductor layer (SiGe) Buffer layer)
14 second semiconductor layer (channel layer made of strained Ge)
15 ... Si cap layer 16 ... Semiconductor substrate 17 ... Gate insulating film 18 ... Gate electrode 19 ... Source region and drain region 20 ... Metal reaction layer 31 ... Si layer 32 embedded oxide film 33 SOI film 34 SOI substrate 35 Si _0.9 Ge _0.1 film 36 Si layer 37 SiGe layer of high Ge composition ( Si _0.3 Ge _0.7 layer )
37 '... SiGe buffer layer 38 ... Si oxide film 39 ... Ge channel layer 40 ... Amorphous Si layer 41 ... Gate insulating film 42 ... Gate electrode

Claims (13)

Forming a laminated structure in which an insulating film and a semiconductor layer containing Si and Ge are sequentially laminated on a supporting base;
A first semiconductor layer including a SiGe layer having a higher Ge composition than the semiconductor layer on the insulating film by performing an oxidation process on the semiconductor layer; and a Si oxide film positioned on the first semiconductor layer. And the step of generating
Removing the Si oxide film;
SiGe or Ge having a higher Ge composition than the first semiconductor layer is formed on the first semiconductor layer.
A method for manufacturing a semiconductor substrate, comprising performing a step of laminating a second semiconductor layer including a layer. 2. The method according to claim 1, wherein the oxidation is performed by using an oxygen gas diluted to 50% or less with an inert gas. 2. The method according to claim 1, further comprising: forming a Si layer having a thickness of 2 nm or less on the second semiconductor layer. 4. The method according to claim 3, further comprising the step of sequentially laminating a gate insulating film layer and a gate electrode layer on the Si layer. 2. The method according to claim 1, further comprising the step of sequentially laminating a gate insulating film layer and a gate electrode layer on the second semiconductor layer. Forming a semiconductor layer containing Si and Ge on a Si layer or a SiGe layer formed on a supporting base via an insulating film;
By performing an oxidation treatment on the semiconductor layer, a first semiconductor layer including a SiGe layer having a higher Ge composition than the semiconductor layer on the insulating film, and a Si oxide film located on the first semiconductor layer. Generating a
Removing the Si oxide film;
SiGe or Ge having a higher Ge composition than the first semiconductor layer is formed on the first semiconductor layer.
A method for manufacturing a semiconductor substrate, comprising performing a step of laminating a second semiconductor layer including a layer. 7. The method of manufacturing a semiconductor substrate according to claim 6, wherein the oxidation treatment is performed by using thermal oxidation using oxygen gas diluted to a concentration of 50% or less with an inert gas. 7. The method according to claim 6, wherein the semiconductor layer containing Si and Ge is formed by epitaxial growth. 7. The method according to claim 6, further comprising the step of forming a Si layer having a thickness of 2 nm or less on the second semiconductor layer. 10. The method according to claim 9, further comprising the step of sequentially laminating a gate insulating film layer and a gate electrode layer on the Si layer. 7. The method according to claim 6, further comprising the step of sequentially laminating a gate insulating film layer and a gate electrode layer on the second semiconductor layer. 4. A step of sequentially laminating a gate insulating film and a gate electrode film on a semiconductor substrate obtained by the method for manufacturing a semiconductor substrate according to claim 1; Performing a process of processing a gate insulating film and a gate electrode and forming a source / drain region to form a field-effect transistor having a channel formed in the second semiconductor layer of the semiconductor substrate. Device manufacturing method. A step of sequentially laminating a gate insulating film and a gate electrode film on a semiconductor substrate obtained by the method for manufacturing a semiconductor substrate according to claim 6, and forming the gate insulating film and the gate electrode film on the semiconductor substrate. Performing a process of processing a gate insulating film and a gate electrode and forming a source / drain region to form a field-effect transistor having a channel formed in the second semiconductor layer of the semiconductor substrate. Device manufacturing method.