JPH06204478A - Mos-type thin film transistor - Google Patents

Abstract

PURPOSE:To suppress the deterioration of the breakdown strength between the source area and the drain area of a polycrystalline silicon MOS-type thin film transistor due to the carrier generated by the electric field concentrating effects of a gate electrode to the drain area edge. CONSTITUTION:A polycrystal silicon MOS-type thin film transistor is permitted to have the laminated structure of a gate electrode 4, a gate oxide film 5, a polycrystal silicon thin film and a basic insulating film 1. LOPOS 11 is formed at the rear plane of the channel area 6 of a polycrystalline silicon thin film and a crystal condition deteriorating part 7 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type thin film transistor, and more particularly to a MOS type thin film transistor using a polycrystalline silicon thin film for source, drain and channel regions.

[0002]

2. Description of the Related Art Thin film SOI (Silicon On I)
A transistor is a transistor formed on a silicon thin film on an insulating film. The element region can be completely separated by etching, and the short-circuit effect due to the underlying insulating film can be suppressed and the junction capacitance between the source and drain regions can be reduced. ， It has great advantages such as mobility improvement by relaxing vertical electric field.

As a method for forming an SOI structure, SIMOX is used.
(Separation By Implanted O
xygen), which is attracting attention as a method for forming a fine MOS transistor. In this method, after implanting oxygen ions with high energy into a single crystal substrate,
This is a method of forming a SOI structure by reducing crystal defects in silicon by high-temperature heat treatment at about 00 ° C. and forming a buried oxide film inside silicon.

A polycrystalline silicon thin film transistor formed by depositing polycrystalline silicon on an insulating substrate is inferior in characteristics to a transistor whose channel region is single crystal silicon, but is relatively easy to form. Therefore, it is used as a load element of a high-speed static memory integrated circuit, or is used as a liquid crystal drive transistor arranged in each display unit called a pixel in a liquid crystal display element.

As an example of a thin film transistor, a cross-sectional view of a device structure of a general polycrystalline silicon thin film transistor is shown in FIG.

A polycrystalline silicon thin film is deposited on the underlying insulating film 1, doped with phosphorus at a high concentration by a diffusion method, and then patterned to form a polycrystalline silicon gate electrode 4. Next, the gate insulating film 5 is formed by the CVD method, and then an amorphous silicon thin film is deposited and the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film. This crystallization method includes a method of increasing the crystal grain size by a solid phase crystallization method (solid phase growth method) in which heat treatment is performed at a temperature of about 600 ° C. for several hours to crystallize, or a laser irradiation is performed instantaneously. There is a method of crystallizing an amorphous silicon thin film at a high temperature to improve the crystallinity of the polycrystalline silicon thin film. In addition, the polycrystalline silicon thin film is heat-treated at 1000 ° C. or higher, or laser-heated,
Attempts have also been made to improve crystallinity and transistor characteristics.

Thereafter, the polycrystalline silicon thin film is patterned into islands and separated. In the subsequent steps, a silicon oxide film is formed by a chemical deposition method as in a general MOS transistor, and then impurities are injected into the polycrystalline silicon thin film using a resist as a mask to form a source region 2, a drain region 3, and a channel region. 6 is formed, the resist and the silicon oxide film are removed, an interlayer insulating film 9 is deposited, and the interlayer insulating film 9 is deposited in a nitrogen atmosphere.
The implanted impurities are activated by heat treatment at about 00 ° C. to reduce the resistance of the source region 2 and the drain region 3, and at the same time flatten the interlayer insulating film 9. Next, a contact hole is formed,
The aluminum film is sputtered, the aluminum film is patterned to form the aluminum electrode 10, and hydrogen alloying is performed at 450 ° C. in a hydrogen atmosphere. Through the above steps, the basic structure of the polycrystalline silicon thin film transistor is formed. After forming the transistor, the substrate temperature is set to 35
The silicon dangling bonds existing in the crystal grain boundaries of the polycrystalline silicon thin film composed of the source region 2, the drain region 3 and the channel region 6 and the crystal defects are treated by hydrogen plasma treatment at about 0 ° C. and hydrogen pressure of 1 Torr. There is also a method of improving the transistor characteristics by reducing the trap level density by using a hydrogenation method of bonding hydrogen.

[0008]

The thin film transistor using the polycrystalline silicon thin film shown in FIG.
Unlike the S transistor, the potential of the polycrystalline silicon thin film (channel region) between the source region and the drain region becomes a floating state. For this reason, carriers generated by impact ionization caused by electric field concentration at the end of the drain region are accumulated in the polycrystalline silicon thin film, and the potential of the channel region rises. As a result, the PN junction on the source region side is forward biased, the drain current increases, the infect ionization rate increases, and the potential of the channel region also increases. The positive feedback as described above occurs, the drain current sharply increases as the drain voltage increases, and the breakdown voltage between the source region and the drain region decreases. This phenomenon is called a parasitic bipolar effect and limits the breakdown voltage of the thin film SOI transistor.

[0009] As a method for improving this problem, Japanese Patent Laid-Open No. Hei 3
In Japanese Patent Laid-Open No. 171673, an impurity diffusion region for isolation between elements is provided, and the region is connected to a fixed potential so that carriers generated by infect ionization flow into the impurity diffusion region for element isolation and disappear. It is possible to reduce the minority carrier concentration in the channel region and prevent the breakdown voltage between the source region and the drain region from decreasing due to the parasitic bipolar effect.

However, when the element isolation region is in wide contact with the channel region, it becomes a parasitic capacitance of the element and the operating speed is lowered, so that the advantages of the SOI structure cannot be fully utilized. Further, when the channel width is wide, there is a problem that the number of minority carriers that do not flow into the element isolation region increases and the breakdown voltage decreases.

In consideration of the above problems, the present invention minimizes the deterioration of the basic characteristics of a polycrystalline silicon thin film transistor, and reduces the minority carrier concentration generated by impact ionization, thereby reducing the breakdown voltage between the source region and the drain region. We propose a structure that maximizes the effect of improvement.

[0012]

In order to solve the above-mentioned problems of the prior art, the MOS type thin film transistor of the present invention has a method such as thermal oxidation on at least a part of the channel region formed in the polycrystalline silicon thin film. There is a portion where the crystalline state is deteriorated.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1A, which is a plan view of a MOS type thin film transistor, and FIG. 1B, which is a sectional view taken along line AA of FIG. 1A, a first embodiment of the present invention will be described. Is formed as follows.

First, polycrystalline silicon is deposited to a thickness of about 100 nm on the base insulating film 1 to reduce the resistance by the phosphorus diffusion method, and then patterned to form the gate electrode 4. A 100 nm gate oxide film 5 is deposited on the gate electrode 4 by a chemical deposition method to form a polycrystalline silicon thin film having a film thickness of 150 nm. This polycrystalline silicon thin film is obtained by crystallizing an amorphous silicon thin film by heat treatment in a nitrogen atmosphere at 600 ° C. for 20 hours. When etching the polycrystalline silicon thin film for device isolation, the regions where the source region, the drain region, and the channel region are formed are left. After forming a silicon oxide film on this by a chemical deposition method, arsenic is implanted with a resist as a mask at an acceleration energy of 30 keV and an implantation amount of 5E15 cm ⁻² to form a source region 2 and a drain region 3. After removing the resist, the entire surface of the oxide film is etched, and the surface of the polycrystalline silicon thin film including the channel region 6 is wet-oxidized at about 950 ° C. to form a thermal oxide film 8 of 100 nm. As a result, about 50 nm of the polycrystalline silicon thin film portion is consumed by the thermal oxidation, and the thickness of the polycrystalline silicon thin film is 1
It becomes about 00 nm. Further, the crystallinity of the interface portion in contact with the thermal oxide film 8 is significantly deteriorated by the thermal oxidation, and the crystalline state deteriorated portion 7 is formed. (The polycrystalline silicon thin film has a non-uniform plane orientation. When thermal oxidation treatment is performed on this polycrystalline silicon thin film interface, the oxidation state of the interface becomes uneven because the oxidation rate varies depending on the plane orientation. The crystallinity deteriorates. A portion in such a state is referred to as a crystal state deterioration portion.) After forming the thermal oxide film 8, the interlayer insulating film 9 is formed to 400 n.
m, and the interlayer insulating film 9 is flattened at 850 ° C. for 3
A heat treatment for 0 minutes is performed in a nitrogen atmosphere. After forming the contact hole 14 in the source region 2, the drain region 3, and the gate electrode 4, aluminum film sputtering,
Aluminum electrode 1 by the process of etching aluminum film
0 is formed and connected, and hydrogen alloying is performed to complete a thin film transistor. After that, the substrate temperature is 350 ° C and the hydrogen pressure is 1
Hydrogenation is performed in hydrogen plasma of Torr to reduce the trap level density of polycrystalline silicon.

Referring to FIG. 5, which is a graph showing current-voltage characteristics of a thin film transistor, the following is true for an N-type transistor having a gate length of 9 μm and a gate width of 2 μm. In the conventional thin film transistor, the drain voltage is 15
The drain current sharply increases above V, and the breakdown voltage between the source region and the drain region decreases due to the parasitic bipolar effect. It can be seen that in the transistor of the first embodiment, the drain current does not suddenly increase up to the drain voltage of 18 V, the parasitic bipolar effect can be reduced, and the breakdown voltage between the source region and the drain region is improved. In the conventional example, holes generated by impact ionization at the edge of the drain region are accumulated in the channel region near the edge of the source region, whereas in the present example, holes flowing into the channel region are thermally oxidized. It is considered that a large amount of recombination is caused at the portion where the crystalline state is deteriorated at, so that the parasitic bipolar effect is suppressed and the breakdown voltage between the source region and the drain region is improved. Also, as is clear from FIG. 5, there is almost no difference in the on-current even when the two are compared. This is because, also in this embodiment, the crystal state of the interface between the gate oxide film on which the inversion layer is formed and the polycrystalline silicon is kept as good as in the conventional case. From the above results, it is understood that the breakdown voltage between the source region and the drain region can be improved without deteriorating the basic characteristics of the transistor such as on-current.

Referring to FIG. 2, which is a cross-sectional view of a MOS type thin film transistor, a second embodiment of the present invention is formed as follows.

First, up to the gate electrode 4 is formed on the base insulating film 1 by the same method as in the first embodiment.
A gate oxide film 5 having a thickness of about 100 nm is formed on the gate electrode 4 by a chemical deposition method, and a polycrystalline silicon thin film having a thickness of about 150 nm is formed by the same method as that of the first embodiment. This polycrystalline silicon thin film is etched to isolate the elements to form a region where a source region, a drain region, and a channel region are formed. After forming a silicon oxide film with a film thickness of about 30 nm on this by a chemical deposition method, the source region 2 and the drain region 3 are formed by ion implantation of arsenic using a resist as a mask, as in the first embodiment. . After removing the resist and the silicon oxide film, wet oxidation at 900 ° C. is performed to form a thermal oxide film of 15 nm, a silicon nitride film is grown to 100 nm, and the silicon nitride film in the channel region 6 is removed using the resist as a mask. Then, the resist is removed. Then 980 ° C
Wet oxidation of LOPOS oxidation (local oxi
Dation poly-silicon) is performed to form LOPOS 11 having a film thickness of about 220 nm in the central portion, and the silicon nitride film is removed. As a result, LOPOS
The crystal state deterioration portion 7 due to oxidation is formed. Next, an interlayer insulating film 9 is deposited to a thickness of about 450 nm, and heat treatment at 850 ° C. for 30 minutes is performed in a nitrogen atmosphere to flatten the interlayer insulating film 9. Further, contact holes are formed in the source region 2, the drain region 3, and the gate electrode 4, the aluminum electrode 10 is connected, and hydrogen alloying is performed to complete the thin film transistor. After that, hydrogenation is performed by the same method as in the first embodiment to reduce the trap level density of polycrystalline silicon.

From the comparison of the current-voltage characteristics shown in FIG.
It can be seen that in the second embodiment, the breakdown voltage between the source region and the drain region is improved by 3 V or more as compared with the case of the first embodiment. This is because in addition to the increase in the recombination rate of holes due to the deterioration of the crystalline state, the polycrystalline silicon is consumed by the LOPOS formation, and the thickness of the channel region portion of the polycrystalline silicon thin film is 40 nm, which is extremely thin. Therefore, holes formed by impact ionization at the edge of the drain region are less likely to flow toward the edge of the source region, holes are not accumulated near the edge of the source region, and holes are accumulated at the lower part of the drain region. This is because the structure is such that the bipolar effect is extremely unlikely to occur.

The crystal state of the interface between the gate oxide film and the polycrystalline silicon in this embodiment is maintained in a good state, as in the first embodiment. Therefore, the basic characteristics of the transistor such as on-current are not deteriorated.

Referring to FIG. 3, which is a cross-sectional view of a MOS type thin film transistor, a third embodiment of the present invention is formed as follows.

First, even a polycrystalline silicon thin film in which elements are separated is formed by the same method as in the second embodiment.
After forming a 30 nm silicon oxide film on this by a chemical deposition method, an acceleration energy of 150 k is used to form the source region 2 and the drain region 3 using the resist as a mask.
Arsenic is implanted with eV and an implantation dose of 2E15 cm ^-2 . Also L
In order to form the low-concentration N-type region 12 of the DD structure, another resist is used as a mask and phosphorus is used at an acceleration energy of 20 ke
V, and the implantation amount is 1E13 cm ^-2 . Furthermore, LOP
The thickness of the central part is about 220 nm, and the LO is
The POS 11 is formed. As a result, a crystal state deterioration part similar to that of the second embodiment is formed. Next, the interlayer insulating film 9, the contact hole, and the aluminum electrode 10 are formed and hydrogen alloying is performed to complete the thin film transistor. Then, hydrogen is applied in the same manner as in the first embodiment to reduce the trap level density of polycrystalline silicon.

As shown in FIG. 5, it can be seen that in the third embodiment, the withstand thickness between the source region and the drain region is further improved by 1V as compared with the second embodiment. This is because the recombination rate of holes increases with the deterioration of the crystalline state, the parasitic bipolar effect is reduced by the LOPOS formation described in the second embodiment, and the electric field concentration at the drain end is alleviated by the LDD structure. Impact ionization is reduced,
This is because the generation of holes is suppressed.

Referring to FIG. 4A, which is a plan view of the MOS type thin film transistor, and FIG. 4B, which is a sectional view taken along line BB of FIG. 4A, a fourth embodiment of the present invention will be described. Is formed as follows.

First, the element-isolated polycrystalline silicon thin film is formed by the same method as in the second embodiment. A 30 nm silicon oxide film is formed on this by a chemical deposition method, and then arsenic is implanted to form the source region 2 and the drain region 3 using the resist as a mask.
Further, in order to form the extraction electrode region 13, boron is accelerated with an acceleration energy of 20 ke using another resist as a mask.
V, and the implantation amount is 1E15 cm ^-2 . Further, the LOPOS 11 having a film thickness of the central portion of about 220 nm is formed.
As a result, as in the second embodiment, the crystalline state deterioration portion 7
Is formed. Next, the interlayer insulating film 9 and the contact hole 1
4, and aluminum electrodes 10 are formed and hydrogen alloying is performed to complete the thin film transistor. After that, hydrogen is applied to reduce the trap level density of polycrystalline silicon.

As shown in FIG. 5, the fourth embodiment is as follows.
It can be seen that the withstand voltage between the source region and the drain region is further improved by 2 V as compared with the second embodiment. This is because the recombination rate of holes increases with the deterioration of the crystalline state.
In addition to the reduction of the parasitic bipolar effect due to the formation, holes are removed by the extraction electrode through the lower part of the drain region, so that the drain junction breakdown voltage due to the holes accumulated in the lower part of the drain region generated in the second embodiment is reduced. This is because the decrease could be improved.

[0027]

As described above, in the MOS type thin film transistor of the present invention, a portion of the polycrystalline silicon thin film formed by thermal oxidation has a deteriorated crystal state in the S channel region near the end of the source region. The channel region formed in the polycrystalline silicon thin film in the portion where the film thickness is smaller than that of the source / drain region by suppressing the increase of the concentration of the minority carriers or by thermal oxidation such as LOPOS oxidation suppresses the minority carriers. Suppressing the influence on the source side PN junction region, and further, that the electrode connected to the region near the drain region and having a different conductivity type from the drain region reduces the minority carriers in the polycrystalline silicon thin film. This has the effect of improving the breakdown voltage between the source region and the drain region.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a sectional view of a third embodiment of the present invention.

FIG. 4 is a plan view and a sectional view of a fourth embodiment of the present invention.

FIG. 5 is a diagram for explaining effects of the first, second, third and fourth embodiments, and is a graph showing drain voltage-drain current characteristics of the thin film transistor.

FIG. 6 is a cross-sectional view of a conventional thin film transistor.

[Explanation of symbols]

 1 Base Insulating Film 2 Source Region 3 Drain Region 4 Gate Electrode 5 Gate Oxide Film 6 Channel Region 7 Crystal State Degradation Area 8 Thermal Oxide Film 9 Interlayer Insulating Film 10 Aluminum Electrode 11 LOPOS 12 Low Concentration N-type Region 13 P-type for Extraction Electrode Region 14 Contact hole 15 Lead electrode

Claims (4)

[Claims] 1. A laminated structure of a gate electrode, a gate insulating film made of a silicon oxide film, a polycrystalline silicon thin film in which a source region, a drain region and a channel region are formed, and an insulating film laminated structure. A MOS type thin film transistor characterized in that at least a part of the channel region of a silicon thin film has a portion whose crystal state is deteriorated. 2. A structure in which the film thickness of the channel region is smaller than the film thickness of the source region and the drain region by selective oxidation of the polycrystalline silicon thin film. MOS type thin film transistor. 3. The MOS type thin film transistor according to claim 1, further comprising an electrode connected to a portion having a conductivity type different from that of the drain region near the drain region. 4. The drain region is an offset structure,
The MOS type thin film transistor according to claim 1, 2 or 3 having an LDD structure.