JPH06232405A - Thin film transistor - Google Patents

Abstract

PURPOSE:To increase a breakdown strength between the source and the drain of a thin film transistor. CONSTITUTION:This thin film transistor is provided with a source region 2 made of a polycrystalline silicon film and provided on a silicon oxide film 1 and a channel lead-out electrode 9 having the opposite conductivity type to that of the source and provided in contact with a channel region 4 adjacent to the source region 2, thereby being able to reduce the hole concentration of the channel region and increase a breakdown strength between the source and the drain thereof.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to thin film transistors.

[0002]

2. Description of the Related Art Thin film SOI (Silicon On I)
Transistor) is a transistor formed on a silicon thin film on an insulating film. The element region can be completely separated by etching. In addition, the short channel effect is suppressed by the underlying insulating film, and the source / drain junction capacitance is reduced. , It has major advantages such as mobility improvement by relaxing the vertical electric field.

SIMO is used as a method for forming an SOI structure.
X (Separation By Implanted
Oxygen) has attracted attention as a means for forming a fine MOS transistor. This method involves implanting oxygen ions with high energy into a single crystal substrate,
This is a method of forming a SOI structure by reducing crystal defects in the silicon layer by high temperature heat treatment at about 1300 ° C. and forming a buried oxide film inside the silicon layer.

Further, a polycrystalline silicon thin film transistor formed by depositing a polycrystalline silicon film on an insulating substrate is inferior in characteristics to a transistor in which a channel region is a single crystal silicon layer, but is relatively formed. Since it is easy, it is applied to a load element of SRAM, a liquid crystal drive of a liquid crystal display, a peripheral drive circuit, and the like.

FIG. 7 is a sectional view showing an example of a conventional thin film transistor.

As shown in FIG. 7, an amorphous silicon film is deposited on the silicon oxide film 1 provided on an insulating substrate or a silicon substrate and is crystallized to form a polycrystalline silicon film, which is then SOI. The structure. The crystallization is performed by a method of increasing the crystal grain size by a solid phase crystallization method in which heat treatment is performed at a temperature of about 600 ° C. for several hours to crystallize, or an amorphous silicon film is instantaneously heated to a high temperature by the laser irradiation and crystallized
There is a method of improving the crystallinity of the polycrystalline silicon film. Further, the crystallinity of the polycrystalline silicon film is improved by heat treatment at 1000 ° C. or higher or heat treatment by laser irradiation,
Attempts have been made to improve transistor characteristics.

Next, the polycrystalline silicon film is patterned into an island shape to separate elements. Subsequent steps are the same as those for a general MOS transistor, the gate insulating film 5 is formed by a chemical deposition method or thermal oxidation, a polycrystalline silicon film is deposited on the entire surface, and a high concentration of phosphorus or the like is formed by a diffusion method. And then patterned to form a polycrystalline silicon gate 6
To form. Impurities are ion-implanted by self-alignment or using the photoresist film as a mask to form the source region 2 and the drain region 3. After that, the interlayer insulating film 7 is deposited,
Heat treatment is performed in a nitrogen gas atmosphere at about 900 ° C. to activate the implanted impurities to reduce the resistance of the source / drain regions 2 and 3, and at the same time flatten the interlayer insulating film 7. Next, a contact hole 15 is formed, an aluminum film is deposited by sputtering, and patterning is performed to form an aluminum electrode 8,
Hydrogen alloying is performed in a hydrogen atmosphere at about 450 ° C. Through the above steps, the basic structure of the polycrystalline silicon thin film transistor is formed.

After the transistor is formed, the substrate temperature is 3
The trap order density is treated by hydrogenation at about 50 ° C. in a hydrogen plasma at a hydrogen pressure of 1 Torr to bond hydrogen to the dangling bonds of silicon present in the crystal grain boundaries and crystal defects of the polycrystalline silicon film. There is also a method of improving the transistor characteristics by reducing

[0009]

In this conventional thin film transistor, as shown in the drain voltage-drain current characteristics of FIG. 8, when a certain drain voltage is exceeded, the drain current sharply increases, the source-drain breakdown voltage decreases, and It can be seen that, when hydrogenation is applied, the on-current increases but the breakdown voltage decreases. This phenomenon is due to the following reasons.

When the drain voltage increases and the electric field near the drain exceeds a certain value, impact ionization occurs near the drain. In the N-channel transistor formed on the silicon substrate, the generated holes become the substrate current, but in the N-channel SOI transistor, the substrate potential is not fixed, and therefore some of the holes are lost by recombination in the channel region. The remaining holes are accumulated in the channel region and the potential of the channel region rises. As a result, the source side PN junction is forward biased, the drain current increases, the impact ionization rate increases, and the potential of the channel region further rises. The positive feedback as described above occurs, the drain current rapidly increases as the drain voltage rises, and the source-drain breakdown voltage decreases. This phenomenon is called a parasitic bipolar operation and limits the breakdown voltage of the thin film SOI transistor.

One attempt to increase the breakdown voltage between the source and drain
As one method, there is a method in which the drain has an LDD structure to relax the electric field at the drain end and suppress impact ionization.

Further, as described in the prior art, in order to improve the transistor characteristics, in the polycrystalline silicon thin film transistor, a method such as laser irradiation or hydrogenation is used.
An attempt to reduce the trap level of a polycrystalline silicon film
Further, in the SIMOX method, an attempt has been made to reduce crystal defects inside the silicon thin film by high temperature heat treatment at 1300 ° C. or higher. However, these methods for improving the crystallinity of the silicon thin film improve the basic transistor characteristics, but reduce the recombination rate of the minority carriers accumulated in the channel region, so that the minority carriers of the channel region The concentration is increased and the parasitic bipolar transistor is likely to become conductive. In other words, the improvement of the crystallinity of the silicon thin film is
There is a problem that the breakdown voltage between the source and drain is reduced.

In Japanese Patent Laid-Open Publication No. 3-171673, in order to improve the breakdown voltage, an impurity diffusion region for element isolation is provided around the element region and the region is connected to a fixed potential, so that holes generated by impact ionization are eliminated. It has been reported that the hole concentration in the channel region can be reduced by flowing into the element isolation impurity diffusion region and disappearing, and the reduction of the source-drain breakdown voltage due to the parasitic bipolar effect can be prevented. However, when the element isolation region is in wide contact with the channel region, it becomes a parasitic capacitance of the element, and the advantages of the SOI structure cannot be fully exerted such that the operating speed is reduced. Further, when the channel width is wide, there are many holes that do not flow into the element isolation region, and there is a problem that the breakdown voltage is lowered.

An object of the present invention is to provide a thin film transistor which can minimize the deterioration of the basic characteristics of the SOI thin film transistor and maximize the effect of improving the withstand voltage between the source and the drain by reducing the hole concentration.

[0015]

A thin film transistor according to the present invention is a thin film transistor having an insulating substrate or a polycrystalline silicon film provided on an insulating film as an active layer and is in contact with a source region and a channel region adjacent to the source region. An extraction electrode having a conductivity type opposite to that of the provided source region is provided.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'showing a first embodiment of the present invention.

As shown in FIGS. 1A and 1B, a polycrystalline silicon thin film having a thickness of 100 nm is formed on a silicon oxide film 1 provided on an insulating substrate or a silicon substrate.
This polycrystalline silicon film is formed by depositing an amorphous silicon film,
It was crystallized by heat treatment for 20 hours in a nitrogen gas atmosphere at 600 ° C. Next, this polycrystalline silicon thin film is selectively etched for element isolation, and a region including a source region, a drain region, a channel region, and a lead electrode from the channel region is patterned and formed.
Next, after depositing a gate oxide film 5 to a thickness of 100 nm on the surface including the patterned polycrystalline silicon thin film,
A polycrystalline silicon film is deposited thereon with a thickness of 400 nm to diffuse phosphorus to reduce the resistance of the polycrystalline silicon film, and then the polycrystalline silicon film is patterned to form a gate electrode 6. At the same time, after removing the gate oxide film 5 immediately below the gate electrode 6 by plasma etching,
A silicon oxide film is deposited to a thickness of 30 nm, the photoresist film patterned and applied on the silicon oxide film and the gate electrode 6 are used as masks for arsenic ions with an acceleration energy of 70 keV and a dose of 5 × 10 ¹⁵ cm ^-2. Then, the source region 2 and the drain region 3 are formed by ion implantation. Next, using the photoresist film provided on the source region 2 and the drain region 3 as a mask, boron is ion-implanted at an acceleration energy of 30 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² to form a channel extraction electrode 9. Next, an interlayer insulating film 17 is deposited on the entire surface and heat-treated for 30 minutes in a nitrogen gas atmosphere at 900 ° C. to activate the implanted impurities. Next, in each of the source region 2, the drain region 3, the gate electrode 6, and the interlayer insulating film 7 on the channel extraction electrode 9,
After forming the contact hole 15, an aluminum film is deposited by sputtering and patterned to form an aluminum electrode 8, and hydrogen alloying is performed to complete a thin film transistor. After that, the substrate temperature is 350 ° C. and the RF power is 400
Hydrogenation is performed in hydrogen plasma with W and hydrogen pressure of 1 Torr to reduce the trap level density of the polycrystalline silicon film.

FIGS. 2 (a) and 2 (b) are characteristic diagrams showing a comparison between the drain voltage-drain current characteristic and the gate voltage-drain current characteristic of the thin film transistor of the first embodiment of the present invention and the conventional thin film transistor. . The measured transistor is an N-type with a gate length of 8 μm and a gate width of 2 μm, the potential of the extraction electrode is 0 V, and the gate voltage is 10 V.
And

As shown in FIG. 2A, in the thin film transistor of the conventional example, when the drain voltage is -15 V or more, the drain current sharply increases and the breakdown voltage due to the parasitic bipolar is lowered. It can be seen that in the transistor, a drastic increase in drain current is not seen up to a drain voltage of 22 V, the parasitic bipolar effect can be reduced, and the source-drain breakdown voltage is improved. This is because in the conventional example, holes generated by impact ionization are accumulated in the channel region at the drain end, whereas in the embodiment of the present invention, the holes in the channel region have P-type conductivity. It is considered that the concentration of holes in the channel can be reduced because it flows out from the extraction electrode, and the parasitic bipolar effect can be reduced. When the effect was investigated by changing the position of the extraction electrode, when the position of the extraction electrode was in the vicinity of the source region, there was almost no effect on the on-current and the effect of improving the breakdown voltage was greatest, but the extraction electrode However, the influences such as a decrease in both the on-current and the withstand voltage became larger as the voltage approached the drain side. This is considered to be because in the case of the thin film SOI transistor, holes generated by impact ionization are accumulated near the source.

From the above results, the source-drain breakdown voltage can be improved without affecting various characteristics such as the on-current of the thin film transistor by providing the P-type electrode for drawing holes in the channel region near the source. You can see that you can.

Further, as shown in FIG. 2B, the threshold voltage is increased by about 0.5 V by making the extraction electrode the same potential as the source electrode. This indicates that in the conventional thin film transistor, holes are accumulated in the channel region and the channel potential rises.

FIG. 3 is a plan view showing a second embodiment of the present invention. When an independent potential is not applied to the extraction electrode in the first embodiment, as shown in FIG.
Alternatively, the P-type region 13 may be formed in contact with both sides of the above, and both regions may be connected by the aluminum electrode 8.

4 (a) and 4 (b) are a plan view and a sectional view taken along line BB 'of the third embodiment of the present invention.

As shown in FIGS. 4A and 4B, an amorphous silicon film in which boron is introduced at 1 × 10 ²⁰ cm ^-2 is formed on the silicon oxide film 1 provided on an insulating substrate or a silicon substrate. It is deposited to a thickness of 100 nm, crystallized by heat treatment at 900 ° C., and patterned to form a channel extraction electrode 9 having a P conductivity type. Then, a polycrystalline silicon film is formed thereon by the same method as that of the first embodiment and is patterned to separate the element formation region. Next, a gate oxide film 5 is deposited on the surface including the element formation region, a gate electrode 6 is formed on the gate oxide film 5, and the gate oxide film 5 other than immediately below the gate electrode 6 is etched. Then, using the gate electrode 6 as a mask, arsenic was ion-implanted at an acceleration energy of 70 keV and a dose of 5 × 10 ¹⁵ cm ⁻² to form a source region 2 and a drain region 3. Next, an interlayer insulating film 7 was deposited and heat-treated in a nitrogen gas atmosphere at 850 ° C. to activate the impurities implanted in the source and drain regions, form an aluminum electrode 8 and perform hydrogen alloying. After that, hydrogenation was performed as in the first example.

According to this embodiment, the parasitic bipolar effect can be reduced and the withstand voltage between the source and the drain can be improved almost similarly to the first embodiment. Further, in the method of the first embodiment,
Since the extraction electrode is only in contact with the side surface of the channel region, when the gate width is large, the holes are not sufficiently extracted from the source end to the extraction electrode, and the effect of reducing the parasitic bipolar becomes small. However, in this embodiment, since the channel extraction electrode 9 is connected to all the regions of the channel, there is an effect that the parasitic bipolar can be reduced regardless of the gate width.

5 (a) and 5 (b) are sectional views showing the order of steps for explaining the manufacturing method of the fourth embodiment of the present invention.

First, as shown in FIG. 5A, a polycrystalline silicon film having a thickness of 250 nm is formed on the underlying silicon oxide film 1, and the polycrystalline silicon film is patterned for element isolation. , A gate oxide film 5 and a gate electrode 6 are formed. Next, after removing the gate oxide film 5 immediately below the gate electrode 6, a silicon oxide film is newly deposited to a thickness of 30 nm, and the acceleration energy of boron is 80 keV and the dose amount is used only in the source region forming portion with the photoresist film as a mask. Two
Ions are implanted at × 10 ¹⁴ cm ^-2 to form the P-type layer 13 under the source region forming portion. Next, after removing the photoresist film, phosphorus is ion-implanted at an acceleration energy of 40 keV and a dose amount of 1 × 10 ¹³ cm ⁻² to form a low concentration N-type region 1.
1 is formed. Next, a film thickness of 200 is formed on the side surface of the gate electrode 6.
nm side wall film 10 is formed, and arsenic is used as a mask for accelerating energy of 50 keV and a dose of 5 × 10 ¹⁵ cm ^-2.
And ion implantation is performed to form P on the N type drain region 3 and the lower layer.
An N type source region 2 having a mold region 13 is formed.

Next, as shown in FIG. 5B, the silicon oxide film is removed, a titanium film is deposited on the entire surface by sputtering, and a rapid thermal treatment at about 700 ° C. is performed in nitrogen gas for about 20 seconds. The source region 2, the drain region 3,
The surface of the gate electrode 6 made of a polycrystalline silicon film is silicidized to form a silicide layer 14a reaching the P-type region 13 under the source region, a silicide layer 14b on the drain region 3 and a silicide layer 14c on the gate electrode 6, respectively. Form each. Next, the unreacted titanium film is removed.
By this silicidation process, the resistance of the source region and the drain region can be reduced, and the potential of the P-type region 13 can be made equal to that of the source region. After that, the interlayer insulating film 7 is formed, the heat treatment is performed at 750 ° C. to activate the impurities, and the aluminum electrode 8 is formed. Then, similarly to the first embodiment,
It was hydrogenated by hydrogen alloying.

According to this embodiment, the withstand voltage between the source and the drain is improved from -15V to -25V in the thin film transistor having the same size as that of the first embodiment. This is LDD
It is considered that this is because the electric field near the drain edge can be relaxed by the structure, and the P-type layer below the source region can reduce the hole concentration in the channel region.

FIG. 6 is a sectional view showing a fifth embodiment of the present invention.

As shown in FIG. 6, a polycrystalline silicon film is deposited to a thickness of 100 nm on the underlying silicon oxide film 1, phosphorus is diffused to reduce the resistance, and then patterned to form the gate electrode 6. Form. A gate oxide film 5 is deposited on the surface including the gate electrode 6, and a polycrystalline silicon film is deposited to 100 nm.
And the device forming region is separated by patterning. Next, after depositing a silicon oxide film with a thickness of 30 nm, arsenic is used as acceleration energy 30 with the photoresist film selectively formed on the silicon oxide film as a mask.
Ion implantation is performed with keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form a source region 2, a drain region 3 and a channel region 4. Next, a part of the channel region 4 and the source region 2
Then, BF ₂ is ion-implanted into a part of the source region 2 at an acceleration energy of 20 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² using the photoresist film as a mask to form a P-type region 13 in the upper layer of the source region 2. Next, an interlayer insulating film 7 is deposited on the entire surface, and 600
The impurities were activated by performing heat treatment for 20 hours in a nitrogen gas atmosphere at 0 ° C. Next, an aluminum electrode 8 connected to each of the source region 2, the P-type region 13, the drain region 3 and the gate electrode 6 through a contact hole provided in the interlayer insulating film 7 is formed, and then hydrogen alloying is performed, It was hydrogenated as in the first example.

This embodiment has the advantage that the parasitic bipolar can be reduced as in the first, second and third embodiments and the process can be simplified as compared with the third and fourth embodiments.

[0034]

As described above, according to the present invention, the source,
An electrode having a conductivity type different from that of the drain region is connected to the channel region near the source region, and an electrode having a conductivity type different from that of the source and drain regions is located between the source region and the source region. Connected to the top, bottom, side surfaces of the region extending over the channel region or at a place including two or more of them, or the conductivity type of the source and drain regions in the upper or lower layer region extending over the source region to the channel region. Having a layer of a conductivity type different from that has an effect that the breakdown voltage between the source and the drain can be improved.

[Brief description of drawings]

FIG. 1 is a plan view and A- showing a first embodiment of the present invention.
A'line sectional drawing.

FIG. 2 is a diagram showing drain voltage-drain current characteristics and gate voltage-drain current characteristics of the first embodiment of the present invention and a conventional example.

FIG. 3 is a plan view showing a second embodiment of the present invention.

FIG. 4 is a plan view and B- showing a third embodiment of the present invention.
B'line sectional drawing.

5A to 5C are cross-sectional views showing the manufacturing process of the fourth embodiment of the present invention in the order of steps for explaining the manufacturing method.

FIG. 6 is a sectional view showing a fifth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing an example of a conventional thin film transistor.

FIG. 8 is a diagram showing drain voltage-drain current characteristics of a conventional thin film transistor.

[Explanation of symbols]

 1 Silicon Oxide Film 2 Source Region 3 Drain Region 4 Channel Region 5 Gate Oxide Film 6 Gate Electrode 7 Interlayer Insulating Film 8 Aluminum Electrode 9 Channel Extraction Electrode 10 Sidewall Film 11 Low Concentration N-type Region 13 P-type Region 14a, 14b, 14c Silicide Layer 15 Contact hole

Claims (3)

[Claims] 1. In a thin film transistor having an insulating substrate or a polycrystalline silicon film provided on an insulating film as an active layer, a conductivity type opposite to that of the source region provided in contact with a source region and a channel region adjacent to the source region is provided. A thin film transistor comprising the extraction electrode having the above. 2. The extraction electrode is formed in contact with any one of an upper portion, a lower portion and a side surface portion of a source region and a channel region adjacent to the source region, or a region including at least two portions thereof. Thin film transistor. 3. The drain region is an offset structure or LD
The thin film transistor according to claim 1, which has a D structure.