JPH06275830A - Accumulation-type polycrystalline silicon thin-film transistor - Google Patents

Abstract

PURPOSE:To achieve a high breakdown voltage and a high mutual conductance simultaneously by forming with a high-resistance Poly-Si layer provided between a gate region and a source region and between the gate region and a drain region and silicon layer which is doped at a lower concentration than the source and drain regions. CONSTITUTION:Polycrystalline silicon 2 is deposited on an amorphous insulation substrate 1, the film is formed in island shape, and then a gate insulation film 3 is formed. The polycrystalline silicon is deposited, phosphor is diffused to it, and then a gate electrode 4 is formed. The gate insulation film 3 on the source and drain regions is eliminated. Phosphourus is implanted at the eliminated region and a source region 5 and a drain region 6 are formed. The gate insulation film except that positioned under the gate electrode is eliminated, phosphorus is implanted. and then a high-resistance region 7 and a low- concentration region 8 are formed between the source and gate regions and between the drain and gate regions. Silicon oxide film or silicon nitride film is deposited, thus forming an interlayer insulation film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon thin film transistor (hereinafter referred to as "Poly-SiTFT") having both high breakdown voltage and high transconductance.

[0002]

2. Description of the Related Art A Poly-Si TFT manufactured by using a semiconductor layer made of polycrystalline silicon formed on an insulating substrate.
Has a higher mobility than an amorphous silicon thin film transistor.

Therefore, since the driving capability is increased, the driving I
C. So-called integrated driver is possible, and because of high mobility, miniaturization is possible and high density can be realized, so research and development have been conventionally conducted.

First, the accumulation type Poly-SiT
The FT will be described.

In the Poly-Si TFT, when the polycrystal silicon of the semiconductor layer is n-type, when a positive voltage is applied to the gate electrode, electrons are induced in the channel and accumulated in the channel to be in the accumulation state. A current flows between the TFT and the drain region, and the TFT is turned on. Further, when a negative voltage is applied to the gate electrode, holes of minority carriers are induced in the channel and the state is inverted, so that no current flows between the source region and the drain region, and the TFT is turned off.

On the other hand, in the case where the semiconductor layer is p-type, when a negative voltage is applied to the gate electrode, holes are induced in the channel, and the holes are accumulated to be in the accumulation state, so that the source region and the drain region are separated from each other. A current flows between them and the TFT is turned on. Further, when a positive voltage is applied to the gate electrode, minority carrier electrons are induced in the channel, the channel is inverted, and the TFT is turned off.

That is, accumulation type Poly-SiT
The FT operates by forming a storage layer in the channel when the TFT is on and forming an inversion layer when the TFT is off.

The conventional Poly-Si TFT will be described below.

FIG. 6 shows a sectional view of a conventional Poly-Si TFT.

As shown in the figure, a polycrystalline silicon film 2 is formed by a CVD method on an amorphous insulating substrate 1 made of quartz, glass or the like and then etched into an island pattern,
A gate insulating film 3 made of a SiO ₂ film is formed by a thermal oxidation method. Next, the gate electrode 4 made of polycrystalline silicon is formed by the CVD method.

After that, the gate insulating film 3 other than the region of the gate electrode 4 is etched by using the gate electrode 4 as a mask, the polycrystalline silicon film 2 is doped with an impurity element, and the high concentration source region 5 and drain region 6 are formed. To form.

Although not shown in the figure, an interlayer insulating film 9 is laminated on the entire surface after the above step, as shown in FIG. 4 showing an embodiment of the present invention, which will be described later, and a source region 5 and a drain region 6 are formed. A contact hole 10 is formed on top, a source electrode 12 and a drain electrode 13 which are respectively in contact therewith are formed, and a display electrode 11 is further provided here, whereby a display device can be obtained.

However, in such a conventional accumulation type Poly-Si TFT, in the case of one n-type semiconductor layer TFT, a negative gate voltage is applied to the gate electrode to turn off the Poly-Si TFT. Then, the p-channel layer is formed with a depth of 100 Å or less.

On the other hand, in the case of the other p-type semiconductor TFT, a positive gate voltage is applied to the gate electrode and the Poly-S
When the iTFT is turned off, the depth of the n-channel layer is 1
It is formed below 00Å.

Therefore, in any type of semiconductor layer, the electric field due to the gate voltage and the drain voltage concentrates at the boundary between the source region or the drain region and the gate region, that is, the drain junction portion, so that the trap is generated. The carrier will move through.

Then, a large leak current depending on the gate voltage and the drain voltage will flow (Reference: JGF
ossum et.al, IEEE Trans.Electron Devices, volED-32, p
(See 1878, 1985).

Therefore, between the source region and the gate region,
As a high breakdown voltage Poly-SiTFT having a high breakdown voltage between the drain region and the gate region, a Poly-SiT having a region composed of one layer with the same impurity concentration as the gate region.
FT has been proposed.

FIG. 7 shows a cross-sectional view of a conventional Poly-Si TFT having a region composed of one layer with the same impurity concentration as the gate region.

As shown in the figure, a polycrystalline silicon film 2 is formed by a CVD method on an amorphous insulating substrate 1 made of quartz, glass or the like, and then etched into an island pattern,
A gate insulating film 3 made of a SiO ₂ film is formed by a thermal oxidation method. Next, the gate electrode 4 made of polycrystalline silicon is formed by the CVD method.

After that step, self-alignment is performed to remove the gate insulating film by etching so as to leave the gate insulating film wider than the gate electrode, and the exposed polycrystalline silicon film 2 is doped with an impurity element to form a high concentration source. The region 5 and the drain region 6 are formed, and the high resistance region 7 consisting of one layer is formed between the source region and the gate region and between the drain region and the gate region.

Here, although not shown, an interlayer insulating film 9 is laminated on the entire surface after the above process, contact holes 10 are formed on the source region 5 and the drain region 6, and the source electrodes contacting the respective regions are formed. 12 and the drain electrode 13 are formed. Further, if the display electrode 11 is provided here, a display device can be obtained.

By the way, even the high breakdown voltage Poly-Si TFT having the high resistance region composed of one layer shown in FIG. 7 has a drawback that the transconductance is significantly lowered.

It is considered that this is because the high resistance region consisting of one layer has a very high resistance, and the region acts as a parasitic resistance added in series to the channel to lower the mutual conductance of the Poly-Si TFT. .

In order to reduce the resistance of the region, it is necessary to reduce the size of the region to 1 μm or less, but it is difficult to fabricate it, and the impurities in the source and drain regions are diffused by the activation process to have a high resistance. It had the drawback of being out of control.

Further, as shown in FIG. 8, the impurity concentration of the high resistance region formed of the above-mentioned one layer is set lower than the impurity concentration of the source and drain regions and higher than that of the gate region to increase the mutual conductance. TFTs having the so-called low concentration region between the source region and the gate region and between the drain region and the gate region are also manufactured.

However, the high transconductance TFT shown in the figure has a drawback that the breakdown voltage is lowered because the resistance in the low concentration region is lower than that in the gate region.

In order to solve this drawback, the size of the low-concentration region should be increased to 5 μm or more. However, because of this, the mutual conductance is lowered and the TFT is reduced.
Further, the disadvantage that the area occupied by the occupies becomes large occurs.

[0028]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and the Poly-Si TFT has a high withstand voltage characteristic in an off state and a high transconductance characteristic in an on state. Poly-SiTF
It provides T.

[0029]

In the accumulation type polycrystalline silicon thin film transistor of the present invention, the region between the gate region and the source region or the drain region is
The upper layer has the same impurity concentration as that of the gate region, and the lower layer has an impurity concentration lower than that of the source and drain regions and higher than that of the gate region.

In the accumulation type polycrystalline silicon thin film transistor, the upper layer has a thickness of more than 100 Å from the surface of the polycrystalline silicon.

Furthermore, in a liquid crystal display device provided with an accumulation type polycrystalline silicon thin film transistor,
A region between the gate region and the source region or the drain region has the same impurity concentration as that of the gate region, an impurity concentration lower than that of the source region and the drain region, and a higher impurity concentration than that of the gate region. The upper layer has a thickness of more than 100Å from the surface of the polycrystalline silicon.

[0032]

According to the present invention, a high resistance polycrystalline silicon layer having a thickness from the surface thereof of more than 100Å is formed in the regions between the source region and the gate region and between the drain region and the gate region. As a result, the leak current when the TFT is in the off state can be reduced, and a high breakdown voltage Poly-Si TFT can be realized. Furthermore, between the source region and the gate region,
The lower region of the high-resistance polycrystalline silicon layer in the region between the drain region and the gate region is a low-concentration doped polycrystalline silicon layer having a lower impurity concentration than the source and drain regions. Since the resistance between the region and the region between the drain region and the gate region is low, the on-current increases when the TFT is in the on state, and the high transconductance of the Poly-Si TFT can be realized.

[0033]

EXAMPLE A Poly-Si TFT of the present invention will be described.

Here, an embodiment in the case of a TFT in which the semiconductor layer is n-type polycrystalline silicon will be described with reference to the drawings.

FIG. 1 shows a sectional view of the Poly-Si TFT of the present invention. FIG. 2 is a plan view when the Poly-Si TFT of the present invention is applied to a display device, and FIGS. 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (b) show AA of FIG. The sectional view of each manufacturing process of the Poly-Si TFT of the present invention is shown along the line ".

According to these figures, the Poly-SiT of the present invention
A method of manufacturing the FT will be described. As shown in FIG. 3A, 1500 Å of polycrystalline silicon 2 is deposited by CVD (Chemical Vapor Deposition) on the entire surface of a cleaned amorphous insulating substrate 1, for example, a quartz substrate, and the film is subjected to a photolithography process. Then, the gate insulating film 3 is formed by thermal oxidation so as to cover the polycrystalline silicon film. The gate insulating film 3 may be a silicon oxide film or a silicon nitride film formed by a CVD method or a sputtering method.

Next, as shown in FIG. 3B, 1500 Å of polycrystalline silicon is deposited again by the CVD method, and phosphorus (P) is diffused into the polycrystalline silicon. Then, the gate electrode 4 is formed by a photolithography process.

Then, as shown in FIG. 3C, the gate insulating film 3 on the source and drain regions formed in the next step.
Are removed by photolithography.

Ion implantation (acceleration voltage: 30 keV or less, dose amount: 1 × 10) is applied to the region where the gate insulating film is removed.
^The source region 5 and the drain region 6 are formed by implanting phosphorus (P) with ¹⁵ dose / cm ² ).

After that step, by self-alignment, the gate insulating film other than that located under the gate electrode is removed by etching, and the ion implantation conditions are changed in the above-mentioned ion implantation (accelerating voltage: 60 to 100 keV, dose amount). 1 × 10 ¹³ dose / cm ² ) was used to implant phosphorus (P), and as shown in FIG. 3D, a high resistance region was formed between the source region and the gate region and between the drain region and the gate region. 7 and a low-concentration region 8 (hatched portion) are formed.

Then, in order to compensate the dangling bonds existing in the Poly-Si film with hydrogen, hydrogenation is performed by hydrogen discharge, and then, as shown in FIG. 4A, a silicon oxide film or a silicon nitride film is formed by a CVD method. The thickness of the film is 4000Å
An interlayer insulating film 9 is deposited to form a contact hole 10 in the interlayer insulating film 9 by a photolithography process.

Here, as shown in FIG. 4B, the Poly-S
When the iTFT is used as a liquid crystal display element, an ITO (Indium Tin Oxide) film is formed by a sputtering method and is formed by a photolithography process before forming the contact hole 10 to form the display electrode 11. .

Then, aluminum is formed as a wiring material by a sputtering method and is molded through a photolithography process to form a source electrode 12 and a drain electrode 13 to complete a thin film transistor.

The embodiment described above is a case of a TFT provided with n-type polycrystalline silicon. However, even in the case of a TFT provided with n-type polycrystalline silicon, phosphorus (P (3) is replaced with boron (B), it can be manufactured similarly to the above-mentioned TFT provided with n-type polycrystalline silicon.

Here, FIG. 5 shows a cross-sectional view when the Poly-Si TFT manufactured by the manufacturing method of the present invention is applied to a liquid crystal display device.

As shown in the figure, the active matrix liquid crystal display device to which the present invention is applied is the above-described Poly-
Po with the alignment film 14 formed on the SiTFT and the display electrode
The liquid crystal layer 15 is sandwiched between the ly-SiTFT substrate and the counter substrate 17 having the common electrode 16 for the counter substrate and the alignment film 14 on the amorphous insulating substrate such as glass.

As in the above embodiment, the Poly-Si of the present invention is used.
A TFT has two layers, a high resistance region as an upper layer and a low concentration region as a lower layer, between the source region and the gate region and between the drain region and the gate region.
When the FT is in the off state, it is possible to realize an off current equivalent to that of the conventional structure TFT which is a high-resistance Poly-Si TFT, and in the on state, an on current or mobility equivalent to that of the conventional structure TFT having one low-concentration layer. It was realized. As a result, in the Poly-Si TFT of the present invention, the on / off ratio of the TFT could be greatly improved by one digit or more as compared with the conventional structure TFT.

[0048]

As described above, according to the present invention, the high resistance Poly-Si layer provided between the gate region and the source region and between the gate electrode and the drain region, and the source region and the drain region are provided. By forming a double layer including a silicon layer doped at a lower concentration than that, an off current is reduced and a high breakdown voltage is achieved, and at the same time, an on current is increased and a high transconductance can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a Poly-Si TFT of the present invention.

FIG. 2 is a plan view showing an embodiment of a Poly-Si TFT of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a Poly-Si TFT of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a Poly-Si TFT of the present invention.

FIG. 5 is a cross-sectional view showing an embodiment of a liquid crystal display device using a Poly-Si TFT of the present invention.

FIG. 6 is a sectional view showing a conventional Poly-Si TFT.

FIG. 7 is a cross-sectional view showing a conventional Poly-Si TFT.

FIG. 8 is a cross-sectional view showing a conventional Poly-Si TFT.

[Explanation of symbols]

 1 Amorphous Insulating Substrate 2 Polycrystalline Silicon Film 3 Gate Insulating Film 4 Gate Electrode 5 Source Region 6 Drain Region 7 High Resistance Region 8 Low Concentration Region 9 Interlayer Insulating Film 10 Contact Hole 11 Display Electrode 12 Source Electrode 13 Drain Electrode 14 Alignment film 15 Liquid crystal layer 16 Common electrode for counter substrate 17 Counter substrate

Claims (3)

[Claims] 1. In an accumulation type polycrystalline silicon thin film transistor, a region between a gate region and a source region or a drain region is lower than an upper layer having the same impurity concentration as that of the gate region and the source region and the drain region. A polycrystalline silicon thin film transistor comprising two layers, a lower layer having an impurity concentration and an impurity concentration higher than that of the gate region. 2. The polycrystalline silicon thin film transistor according to claim 1, wherein the upper layer has a thickness greater than 100 Å from the surface of the polycrystalline silicon. 3. A liquid crystal display device comprising an accumulation type polycrystalline silicon thin film transistor, wherein a region between a gate region and a source region or a drain region has an upper layer having the same impurity concentration as that of the gate region,
It has two layers, a lower layer having a lower impurity concentration than the source region and the drain region and a higher impurity concentration than the gate region, and the upper layer has a thickness greater than 100Å from the surface of the polycrystalline silicon. Characteristic liquid crystal display device.