JPS59151465A - Vertical type metal oxide semiconductor field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce feedback capacitance between a gate and a drain by partially burying an insulator to a section immediately under approximately the central section of a gate oxide film and lengthening an opposite distance between a gate electrode film and a drain region. CONSTITUTION:An N<-> layer (c) functioning as a drain is formed on an N<+> type Si substrate (a), and P type well regions (d) serving as channel regions are formed to the layer (c) and N<+> type well regions (e) functioning as source regions in the regions (d). A gate oxide film (g) is applied and formed between the regions (d) and (d), and a gate electrode film (i) is formed on the upper surface of the film (g). In a vertical type MOSFET formed in this manner, an insulator (h) is buried to a section immediately under approximately the central section of the film (g) shaped between the adjacent regions (d) and (d) in the surface of the base body (a). Consequently, an opposite distance between a film (i) and the region (c) positioned at the upper and lower sections of the insulator (h) while hlding the insulator is brought to a separate state. Accordingly, feedback capacitance between a gate and the drain is reduced, and the speed of switching can be increased.

Description

[Detailed Description of the Invention] This invention has a small feedback capacitance between the gate and drain.
The present invention also relates to a vertical MO8FET that can be manufactured with high yield.

In recent years, power MO8FETs have been developed due to the desire to simplify and integrate drive circuits and lower the power supply voltage of the circuits.
Among them, there is a movement to apply vertical MO8FETs, which have low oscillation resistance and are suitable for power switching, to switches.

FIG. 1 shows the general structure of a conventional vertical MO8FET, and this vertical MO8FET has conventionally been manufactured through the following manufacturing process.

(a) A low-resistance drain substrate 1 made of a silicon wafer having high-concentration N-type (N+) properties is
) layer is epitaxially grown to form a high resistance drain region 2.

(b) A gate insulating film 3 is formed on the surface of this high-resistance drain region 20 by thermal oxidation, and a polysilicon film constituting the gate electrode 5 is further formed on its upper surface.

(c) After selectively removing this polysilicon by photolithography, using the polysilicon as a mask, inject into the well region for channel formation into the opened source window by a double diffusion method. A source region 7 and a well contact region 8 which are concentrically diffused from the center toward the outer periphery are sequentially formed.

(iv) After completing the above double diffusion process, a source electrode 10 is formed on the upper surface of the gate electrode 5 through an insulating film 9 by evaporation, and a low resistance drain substrate 10 is formed on the upper surface of the gate electrode 5.
A drain electrode 11 is formed on the back surface of the substrate to complete the final product shown in FIG.

According to the vertical MO8FET to which the above method is applied, in order to form the well region 6 and source region 7 constituting the channel forming region by the double diffusion method, a large number of transistors can be simultaneously manufactured on a silicon wafer. In this case, the characteristics of each transistor can be made uniform, which significantly improves the yield and leads to miniaturization. After performing ion implantation from the window, 2
In order to form the well region and source region by m-diffusion, it is necessary to previously cover the entire region sandwiched between adjacent source windows with a polysilicon film.

For this reason, the geometry of the final product is such that in addition to the top surface of the channel region, which is originally required as a gate electrode, a polysilicon film remains up to the top surface of the drain region, and due to its structure, the gate electrode and train electrode are covered with a thin gate insulating film. As a result, the drain-gate capacitance becomes large, and this capacitance acts as a feedback circuit from the output to the input, so there is a problem that it becomes an obstacle to increasing the switching speed. Ta.

This invention was made by focusing on these conventional problems, and its purpose is to create a vertical MO8FET with a small feedback capacitance between the gate and drain and which can be manufactured with high yield. It is about providing.

In order to achieve the above object, the present invention locally embeds an insulator directly under the approximate center of a gate oxide film covering adjacent channel forming well regions on a semiconductor substrate surface, thereby forming a gate electrode. The facing distance between the film and the drain region is set apart.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIG. 2 and the subsequent drawings.

FIG. 2 is a cross-sectional view of an element showing the structure of an embodiment of a vertical MO8FET according to the present invention.

In the figure, a is an N0 type silicon wafer constituting the substrate, b is an aluminum evaporation layer that is coated on the back side of the substrate a and functions as a drain electrode, C is formed on the substrate a by epitaxial growth, d is a P-type well region that functions as a channel forming region, e is an N÷-type well region that functions as a tooth region, and f is a contact region for leading the P-well d to the outside. The P÷ type small T/L region 9g which functions as a gate oxide film is formed to cover between adjacent P well regions d and 6 for channel formation, and h is buried directly under the center of the gate oxide film g. i is the gate oxide film 9
A gate electrode film made of polysilicon that covers the upper surface, j is an insulating film that covers the upper surface of the gate electrode film i, and conduction is established between the N+ well "region e, which becomes the source region, and the P ten-type small well region f. , an aluminum electrode layer.

As described above, in the vertical MO8FET 5- according to the present invention, a predetermined portion approximately at the center of the gate oxide film Q formed between adjacent well regions d for channel formation on the surface of the semiconductor substrate e is formed. An insulating material is embedded directly under the region, and therefore, the facing distance between the gate electrode film i and the drain region C, which sandwich and cover the insulating material I), is the same as that of the conventional method shown in FIG. It will be in a separated state compared to the example.

Therefore, the feedback capacitance between the gate and drain is reduced, and switching speed can be increased.

Next, FIG. 3 shows the manufacturing process of a vertical MO8FET to which the present invention is applied.

Hereinafter, this manufacturing method will be explained in order according to each step (A) to (H).

(A) Consists of a high-concentration N-type (N+) silicon single crystal plate with a donor impurity concentration No of about 1 x 10" cm-3. On the low resistance drain substrate 20, No.
Low concentration N type, (N -
) A silicon single crystal is epitaxially grown to form a - high resistance drain region 21;

6-(B) Cover the surface of the high-resistance drain region 21 with a resist 22 other than the planned formation position of the channel-forming well region, and then dry-etch the surface of the window opening formed in the resist 22. Approximately 1μm
Etching is performed to form the recess 21a, and after step 2, the resist 2
Remove 2.

(C) A silicon oxide film 23 containing arsenic with a molar concentration ratio of about 3 ml is deposited to a thickness of about 1 μm over the entire surface by CVD, and then the silicon oxide film 23 is removed except for the recesses 21a by photolithography. In this case, the periphery of the silicon oxide film 23 filled in the four portions 2Ia is gently raised from the surface.

(D) Silicon oxide for gate on the surface by thermal oxidation method 1!
124 to a thickness of about 1000, and a CV on the top surface.
A polysilicon layer constituting the gate electrode 25 is formed by method D.

At this time, the N-type impurity made of arsenic in the silicon oxide film 23 contained in the recess 21a is diffused by the thermal oxidation, and the silicon oxide It! An N-type high concentration region (N+) 23a is formed at the periphery of 23 and the culm surface of the high-resistance drain region 21, as shown by a broken line.

(E) After selectively removing the well region formation position covered by polysilicon by photolithography, boron ions (B+) are implanted by ion implantation using the remaining portion of the gate electrode 25 as a mask material. do.

The implantation energy of this ion is approximately 60 keV.

The implantation amount is approximately 4×10'3 am-2.

Then, if heat treated at about 1100℃ for about 24 hours, 4~
P-type well region 2 for channel formation with a depth of about 6 μm
6 is formed.

(F) Next, using the resist 27 as a mask,
Boron (B+) is implanted by ion implantation through a window formed in the center of the upper surface of 6.

The implantation energy of this ion is approximately 50 keV.

The implantation amount is about 5.times.10.sup.15 am@-2, and by removing the resist 27 after completing this operation, a precursor of a P-type well contact region is completed in the center of the well region 26.

(G) The P-type well contact region precursor is covered with a resist 28, and phosphorus ions (P+) are implanted using the resist 28 as a mask. The implantation energy of this ion is approximately 10.0keV and the implantation amount is approximately 5X1.
015am-2, and phosphorus ions also enter polysilicon.

After this operation is completed, the resist 28 is removed and the phosphorus ions (
A source region precursor consisting of P+) is completed.

(H) By CVD method, an insulating film 29 made of phosphorus glass with a phosphorus molar concentration ratio of about 3% is formed to a thickness of about 7,000 mm to cover the surface, and is heat-treated in nitrogen at about 1,050°C. , the boron (' B + ), phosphorus ions (
P+) diffuses into the P-type well contact region 3, respectively.
0 and N÷ type source regions 31 are completed.

(1) Next, after opening windows on the surfaces of the source region 31 and well contact region 30, and opening windows on the gate contact portion (not shown), aluminum is vacuum-deposited on the surface to a thickness of about 1.5 μm. After deposition, a source electrode 32° and a gate lead electrode (not shown) are formed by etching. Next, aluminum with a thickness of about 1 .mu.m is deposited on the back surface of the low resistance drain substrate 20 by vacuum evaporation and alloyed at about 450.degree. C. to form a drain electrode 33, thereby completing the final product.

In the vertical MO8FET manufactured through the above steps, as is clear from the structure shown in FIG. 3(1), most of the Since the structure is such that the thick silicon film 23 is interposed in the region, the drain-gate capacitance is significantly reduced, and the switching speed is increased.
Since the conventional double diffusion method can be applied as is to the manufacturing process, the advantage of this method is that there is no decrease in yield when the device is integrated at high density, and it can be manufactured at low cost. .

10- Also, in the embodiment, the high resistance drain region 2
N-type impurities such as arsenic are contained in the thick silicon oxide film 23 embedded in the silicon oxide film 23, and then a silicon oxide film 24 is formed on the surface of the high-resistance drain region 21: in the process, oxidation of I! 23 and high resistance drain region 2
Since a high concentration N type (N+) region is formed at the boundary with 1, the iI current flows through this N type (N+) region, and the specific resistance caused by the high resistance drain region can be reduced.

In the above embodiment, a P-type well region is formed on an N-type substrate, but in contrast to the above, a P-channel vertical well region is formed on a P-type substrate. Of course, it can also be applied to type MO8FET.

As described in detail in the embodiments above, the vertical MO8FET according to the present invention has a structure in which local insulation is provided directly under the substantially central part of the gate oxide film that covers between adjacent channel forming well regions on the semiconductor substrate surface. Since the gate electrode film and the drain region are separated from each other by embedding the material, the feedback capacitance between the gate and the drain can be significantly reduced. It has excellent features such as being able to be manufactured in exactly the same way in a single process with the addition of an insulator depositing step.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the general structure of a conventional vertical MO8FET, FIG. 2 is an element cross-sectional view showing an embodiment of the vertical MO8FET according to the present invention, and FIGS. 3(A) to (1) are FIG. 3 is a cross-sectional view of an element showing each step of an embodiment of the present invention. 20.21... Semiconductor substrate 21a...... Concavity 23... Insulating film 24... Insulating layer 25・・・・・・・・・・・・Electrode film 26・・・・・・・・・Well region for channel formation 31・・・・・・・・・Source region procedure correction document (Method) June 3, 1980 2, Title of invention: Vertical MO8FET3, Person making the amendment □ Relationship to the case Address of patent applicant Address: 2 Takaracho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Name
(399) Nissan Motor Co., Ltd. Representative Shun Nunohara 4, Agent 101 Address 1-15-16-6 Uchikanda, Chiyoda-ku, Tokyo
, Subject of amendment Drawing 7, Contents of amendment (1) We would like you to add the drawing number "Figure 3" so that it is not placed on the attached drawing. 1-320-

Claims (1)

[Claims] (1) A vertical MO8FE in which a well region for channel formation is formed by the two-φ diffusion method using the gate electrode film as a mask, and a source region is formed within the well region.
In T: A vertical MO8F characterized in that an insulator is locally buried directly under the approximate center of the gate oxide film covering between adjacent channel forming well regions on the semiconductor substrate surface.
E.T.