JPS59182570A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain three-dimensional structure suitable for a NAND gate circuit by each forming two gate electrodes to upper and lower sections through a gate insulating film while holding a channel region in a semiconductor substrate and surrounding the electrodes by an insulating film thicker than the gate insulating film when preparing an MIS transistor. CONSTITUTION:An SiO2 film 11 is formed on the surface of a P type Si substrate 1, and As ions, etc. are implanted through the film 11 to shape an N<+> type Si gate electrode 2. A P type polycrystalline Si film 4 as a channel region is deposited on the whole surface including a gate insulating film 3 consisting of the film 11 positioned on the electrode 2 while selecting the quantity of an impurity so as to obtain a desired threshold value, a gate insulating film 5 corresponding to the electrode 2 is formed on the film 4, and a gate electrode 6 composed of N<+> type polycrystalline Si is deposited. N<+> type source region 7 and drain region 8 are formed to the film 4 through an ion implantation while being positioned on both sides of the electrode 6, and the electrode 6 is surrounded by a thick insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION (a+) Technical Field of the Invention The present invention relates to semiconductor devices, and particularly to a three-dimensional logic element in which a plurality of Mis transistors are stacked three-dimensionally.

fb) Prior Art and Problems As is well known, semiconductor integrated circuits (ICs) are becoming increasingly highly integrated, and this is because as the degree of integration increases, significant performance improvements such as faster operation can be expected.

By the way, in logic circuits, for example, an enhancement/depression type NAND gate circuit as shown in FIG. 1 is commonly used, and almost all of such gate circuits are composed of M'IS) transistors. That is, in the same figure, 1. ．． 12 is an input gate element, and L is a load MIS element.

Of course, a logic IC consisting of such MIS) transistors,
1"j+6 integration is progressing, but there is a limit to integration with the current IC structure that is formed two-dimensionally (two-dimensionally) on a semiconductor substrate.

Therefore, a three-dimensional (three-dimensional) structure is a concern, and it goes without saying that this will lead to even higher integration and higher performance.

[C) Object of the Invention From this viewpoint, the present invention proposes a three-dimensional structure of the above-mentioned NAND circuit.

(dl)Structure of the InventionThe object of the invention is to provide a semiconductor device having a double-gate electrode type M1st-run transistor structure in which two gate electrodes are provided on a substrate with a channel region sandwiched therebetween, and two gate electrodes are provided below each with a gate insulating film interposed therebetween. This is achieved in a timely manner.

In addition, this can be achieved by a semiconductor device in which the above substrate is a semiconductor substrate, and an insulating film thicker than that of Kate & Color KAll Moxibustion is provided around a gate electrode provided in the semiconductor substrate.

(Ql　Embodiments of the invention Examples will be described in detail below with reference to two drawings.

FIG. 2 is a sectional view of an embodiment according to the present invention, and this example is the input element 1 shown in FIG. 1 above. , I2 are laminated. As shown in the figure, N+ on the P type silicon substrate l.
type silicon gate electrode) to form silicon dioxide (
S i O2) H'A 3 parts 1 - P-type channel region 4 is installed on the insulation crotch, and SiO is further placed on it.
□An N'' type silicon gate electrode 6 is provided through a gate insulation film consisting of a film 5, and thus the gate electrode 2, the 5i02 film 3, and the channel region 4 form one input element 11.
is formed, and 1' input elements I2 are formed by the gate electrode 6, the SiO□ film 5, and the channel region 4, and a source region @7 and a drain region 8 are provided in common on both sides. ing. Note that 9 is a cover insulating film made of a 5i02 film, and 10 is a lead-out electrode.

In this way, since the two input elements are three-dimensionally formed, the degree of integration is significantly improved.

In addition, such a structure can be easily formed by using a single crystal thin film forming method such as a lateral epitaxial growth method.

3 to 6 show schematic cross-sectional views of the order of the forming steps. First, as shown in FIG. 3, the surface of a P-type silicon substrate 1 is thermally oxidized to form a 5i02 film 11, and then windows are selectively opened and arsenic ions are implanted to form a film with a thickness of 0.5 to 1 μm. N of
A + type silicon gate electrode 1 and electrode 2 are formed, and a 5i02 film 3 (gate insulating film) having a thickness of 400 nm is further formed thereon. At this time, a method may be used in which ions are implanted into the gate electrode 2 after the 5i02 film 3 is formed. Here, 5iO21EIIL with a thick film thickness is formed in advance, but this is important because MO' formed in the subsequent steps
This is extremely effective in reducing the parasitic capacitance of the S transisk and increasing the operating speed.

Next, as shown in FIG. 4, a polycrystalline silicon film with a thickness of 4,000 yen was deposited by chemical vapor deposition (CVD), and a cap layer 12 (an antireflection film) was coated on top of the polycrystalline silicon film. The polycrystalline silicon film is melted and scanned by laser irradiation to form a silicon crystal film 4. This is the lateral epitaxial growth method described above. Next, after removing the cap layer 7, as shown in FIG.
1016 boron ions are implanted to form a P-type silicon crystal film 4 and a threshold value is determined.

Next, as shown in FIG. 6, a film W2O is formed by CVD method.
Three 5i02 films 5 (gate insulating films) and polycrystalline silicon films 6 are deposited, and then the 5i02 films 5 and polycrystalline silicon films 6 are patterned simultaneously. Next, highly concentrated phosphorus ions are implanted over the entire surface to make the polycrystalline silicon film 6 N.
After forming a + type silicon gate electrode and simultaneously forming an N+ type source region 7 and drain region 8, a thickness t+'
After depositing the l5i02 film 9 and forming a window thereon to form the electrode 10, the structure is completed as shown in FIG. In this case, the gate electrode 6 may be crystallized or remain polycrystalline.

Next, FIG. 7 shows another embodiment of the present invention, in which a similar MIS transistor is formed on a monochromatic line substrate 13, and the method of formation is almost the same as that described above. Furthermore, the gate electrode may be made of metal such as molybdenum.

Next, FIG. 8 shows a sectional view of an embodiment according to the present invention in which the number of input gate elements is further increased.

In the figure, 14 is a channel region, 15 is an insulating film, 16 is a gate electrode, and two channel regions, four gate thread-colored border films, and three gates are formed. , the source region 17 and the train region 18 are common.The logic symbols in this example are as shown in FIG.
If the Q-shaped structure of the embodiment shown in FIG. 8 is formed, more input gate elements can be stacked.

The method of forming the embodiment shown in FIG. 8 is approximately the same as that of the above example.
It is necessary to add a step of applying and bakunnin the iC, )1 center 19 after defining the gate electrode ( )16.

Next, FIG. 10 shows another example according to the present invention in which a melon layer is formed on an insulating base (20), and a tungsten electrode 21 is used as the gel electrode.In addition to tungsten, Molybuan or a silicide thereof may also be used.The formation method is also the same as above.

ffl Effects of the Invention As is clear from the above explanation, according to the present invention, the IC can be more highly integrated and its performance can be significantly improved.

[Brief explanation of the drawing]

1 is a circuit diagram of a NAND type gate 1, FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. Figures 8 and 10
The figure shows another embodiment of the present invention made of ``-11 conductor; 1°
The cross-sectional view, FIG. 9, is a logical symbol of the embodiment of FIG. In the figure, 1 is a P-type semiconductor substrate, 2. G, '6 is the gate electrode, 3, 5.15 is the gate electrode (1 rin 'i + 14 is the 1-2t area, 7.17 is the hearth area, 8.18
is the drain territory J or 9. ．． 11.19 is ':, silicon oxide (SiC2) 117.10 is a lead-out electrode, 12 is a key 2/bulk layer (antireflection film), 13.20 is an insulating base (anti-reflection film),
21 indicates a tungsten electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 6 Figure 9 Figure 10 F1

Claims (2)

[Claims] (1) A semiconductor device characterized by having a dual-gate electrode type MIS transistor structure in which two gate electrodes are provided on the upper and lower sides of a substrate with a channel region sandwiched therebetween, with gate insulating films interposed therebetween. (2) The semiconductor device according to claim 1, wherein the substrate is a semiconductor substrate, and an insulating film thicker than a gate insulating film is provided around a gate electrode provided in the semiconductor substrate.