JPS61281558A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a MOS semiconductor device, threshold voltage thereof can be changed by simple operation, by burying a conductive pattern into an insulating layer while being insulated from other semiconductor elements and wirings. CONSTITUTION:P-type silicon 21 is thermally oxidized and treated, an oxide film 22 is formed, phosphorus is doped to a polycrystalline silicon film deposited on the whole surface, and the phosphorus-doped polycrystalline silicon film is patterned through a photoetching method to shape a polycrystalline silicon pattern (a floating electrode) 23 on the oxide film 22. An SiO2 film 24 is deposited on the oxide film 22, and the floating electrode 23 is buried into an insulating layer consisting of the oxide film 22 and the SiO2 film 24. When the concentration and thickness of regions between source and drain regions in a semiconductor layer are selected so that a depletion layer generated when voltage is applied to a gate electrode reaches up to the surface of the insulating layer at that time, the threshold voltage of a semiconductor device is represented by the function of the quantity of carriers injected to a floating conductive pattern. Accordingly, threshold voltage can be changed by simple operation.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a MOS semiconductor device, and is used to improve MOS semiconductor devices such as multivalued logic circuits and EPROMs having MOS transistors with different threshold voltages on the same chip. Involved.

[Technical background of the invention]

Conventionally, a multi-value logic circuit having MOS transistors having different threshold voltages has a structure shown in FIG. 3. 1 in FIG. 3 is, for example, a p-type silicon substrate, and a field oxide film 2 for isolating transistors is provided on the surface of this substrate 1. This field oxidation
Four MOS transistors Trt and Tr2 having different threshold voltages are formed in the island-shaped substrate region separated by I2.

These transistors Trt and Tr2 have gates on the surface of the substrate 1 including n+ type source and drain regions 3.4 provided electrically isolated from each other on the surface of the substrate 1, and a channel region between these regions 3.4. A gate electrode 6 is provided through an oxide film 5. and,
Channel region 711 of each transistor Trl, Te3
By changing the amount of ion implantation of impurities (usually p-type impurities) into the transistors Tr1 and Tr72,
The threshold voltages of Te3 are mutually changed.

On the other hand, an EPROM having a structure shown in FIG. 4 is conventionally known. Reference numeral 11 in FIG. 4 is, for example, a p-type silicon substrate, and a field oxide film 12 for isolating transistors is provided on the surface of this substrate 11. In the island-shaped substrate region separated by the field oxide film 12, n+ type source and drain regions 13 and 14 electrically isolated from each other are provided. A substrate 1 including a channel region between these source and train regions 13 and 14.
A floating gate 16 made of polycrystalline silicon is provided on one surface with a gate oxide film 15 interposed therebetween. An oxide film 17 formed by thermal oxidation of the gate 16 is provided around the floating gate 16. A control gate 18 made of polycrystalline silicon is provided on the oxide film 17 on the upper surface of the floating gate 16. EPRO with such configuration
In M, a high voltage is applied to the control gate 18 and the drain region 14, and hot electrons generated near the drain region 14 are transferred to the floating gate 16 through the gate oxide film 15.
The threshold voltage of the transistor is changed by injecting it into the transistor.

[Problems with background technology]

However, in the multivalued logic circuit shown in FIG. 3 described above, when transistors with different threshold voltages are manufactured by ion implantation, it is necessary to perform photolithography and ion implantation for the number of transistors with different threshold voltages. , there are many steps, which leads to a decrease in productivity. In addition, when controlling the threshold voltage using ion implantation, the threshold voltage cannot be checked until after each transistor has been fabricated, so if the thickness of the gate oxide film deviates from the set value, the threshold voltage will change. A problem occurs when the circuit does not operate.

On the other hand, in the EPROM shown in FIG. 4, when hot electrons generated in the channel region are injected into the floating gate 16 through the gate oxide film 15, the number of interface units between the silicon substrate 11 and the gate oxide film 15 increases. There is a problem that transistor characteristics deteriorate.

[Purpose of the invention]

The present invention aims to provide a MOS type semiconductor device in which the threshold voltage can be changed by a simple operation without changing the impurity concentration of the channel region.

[Summary of the invention]

The present invention provides a semiconductor layer provided on an insulating layer, a source and a drain region of one conductivity type provided on the semiconductor layer so as to be electrically separated from each other so as to reach the surface of the insulating layer, and these source and drain regions. In a MOS type semiconductor device including a gate electrode provided on the surface of a semiconductor layer including a channel region between train regions via a gate oxide film, a conductive pattern is insulated in the insulating layer from other semiconductor elements and wiring. It is characterized by the fact that it can be embedded. According to the present invention, since the floating conductive pattern is embedded in the insulating layer, a high voltage is applied to the gate electrode and the drain region, and hot electrons are injected into the conductive pattern by a high electric field near the drain region. The back gate effect of the conductive pattern makes it possible to change the threshold voltage of the semiconductor layer region between the source and train regions. In this case, if the concentration and thickness of the region between the source and drain regions of the semiconductor layer are selected so that the depletion layer generated when a voltage is applied to the gate electrode reaches the surface of the insulating layer, the threshold voltage of the semiconductor device can be It can be a function of the amount of carriers injected into the floating conductive pattern. Therefore, it is possible to obtain a MOS type semiconductor device in which the threshold voltage can be changed by a simple operation without changing the impurity concentration of the channel region as described above.

[Embodiments of the invention]

Hereinafter, an example applied to a MOSIC using SOI will be described in detail, together with the manufacturing method shown in FIGS. 1(a) to 1(C).

First, for example, p-type silicon 21 was thermally oxidized to form an oxide film 22 having a thickness of, for example, 1 μm.

Subsequently, a polycrystalline silicon film with a thickness of, for example, 4,000 wafers is deposited on the entire surface, and the polycrystalline silicon film is doped with phosphorus.The phosphorus-doped polycrystalline silicon film is then patterned by photolithography to form a polycrystalline silicon film on the oxide film 22. A crystalline silicon pattern (floating electrode) 23 was formed (as shown in FIG. 1(a)).
.

Next, a film with a thickness of 5,000 mm with a flat surface is deposited on the oxide film 22 including the floating electrode 23 by bias sputtering.
An i02 film 24 was deposited. As a result, the floating electrode 23 is embedded in the insulating layer with the thickness of the oxide film 22 and the SiO2 film 24. Note that the thickness 4 of the SiO2 film 24 on the floating electrode 23 is, for example, 1000. In this process, C
An SiO2 film having a flat surface may be formed by depositing a SiO2 film by a VD method, applying a resist film over the entire surface, and etching back the resist film and the SiO2 film. Next, after depositing a silicon film on the entire surface, laser annealing or electron beam annealing is performed to form the SiO2 film 24.
An upper crystalline silicon layer 25 was formed on the upper layer 24 (as shown in FIG.
I x 10"!'/cm3 or less. Such a thickness of 6000 people, boron concentration of 1 x 1016/cm3
By forming the following single-crystal silicon layer 25, when a voltage is applied to the subsequent gate electrode, the depletion layer sufficiently reaches the surface of the S+02 film 24 constituting the insulating layer from the single-crystal silicon layer 25.

Next, a field oxide film 26 is formed on the single crystal silicon layer 25 by a selective oxidation method or the like, and then a thermal oxidation treatment is performed to reduce the surface thickness of the island-like regions of the single crystal silicon layer separated by the field oxide film 26. 500 people grew thermal oxide films.

Subsequently, a polycrystalline silicon film with a thickness of 4,000 wafers is deposited on the entire surface and doped with phosphorus, and then the phosphorus-doped polycrystalline silicon film is patterned by photolithography to form a gate electrode 27. Gate oxide film 2 is formed by selectively etching away the thermal oxide film as a mask.
8 was formed. Subsequently, using the gate electrode 27 and the field oxide film 26 as a mask, an n-type impurity, for example, phosphorus, is ion-implanted and activated to reach the island-like region of the single crystal silicon layer 25 to the surface 4 of the SiO2 film 24. Drain regions 29 and 30 were formed. Thereafter, a bias electrode 31 was formed on the back surface of the substrate 21 to manufacture an n-channel MOSIC (FIG. 2(C)).

According to the present invention, when a voltage higher than the voltage normally used is applied to the gate electrode 27 and drain region 30 of a transistor whose threshold voltage is to be changed, oxidation w
Carriers are injected into the floating electrode 23 embedded in the insulating layer made of A22 and 5i02 films 24, and the floating electrode 2
The threshold value of the transistor can be changed by the back gate effect of No. 3.

At this time, in the single crystal silicon layer region between the source and drain regions 29 and 30, the depletion layer generated when a voltage is applied to the gate electrode 27 forms the film surface 4 of the 5if2 film 24, which constitutes the insulating layer in which the floating electrode 23 is buried. The threshold voltage of the relevant transistor can be a function of the amount of carriers injected into the floating electrode 23, since the concentration and thickness are chosen to reach it. In addition, when it is desired to inject holes into the floating electrode 2♀ in the carrier injection, no bias voltage is applied to the electrode 31 which is exclusively on the substrate 21, and when it is desired to inject electrons, a positive bias voltage is applied to the electrode. Apply. Through such operations, the threshold voltage of the transistor can be changed either in the positive direction or in the positive direction.

Specifically, all transistors in the integrated circuit are initially set to a normally off state, and the threshold voltage of a given transistor is changed in the manner described above to set the normally off state.
EPR by turning on or changing the condition.

Can be used as OM. In this application to FFEPROM, hot electrons are positively floating through the gate oxide film on the substrate, as in conventional EPROM.
Because carriers are injected into a floating electrode buried in an insulating layer that is not related to transistor operation, instead of flowing into and out of the transistor, the interface between the substrate and the gate oxide film increases as in conventional transistors. can prevent deterioration of characteristics.

In addition, the threshold voltages of the plurality of transistors are selected in the manner described above. Alternatively, by changing it, a multivalued logic circuit can be easily realized.

In the above embodiment, the insulating layer is an oxide film formed on the surface of the semiconductor substrate and a Si deposited by bias sputtering.
Although the structure is made of an O2 film, it is not limited thereto. For example, it may be composed of an insulating substrate such as glass and a SiO2 film for covering and embedding the conductive pattern (floating electrode).

In the above embodiment, the conductive pattern is formed from phosphorus-doped polycrystalline silicon, but the present invention is not limited thereto. For example, it may be formed of a high melting point metal such as tungsten, molybdenum, or titanium, or a high melting point metal silicide such as tungsten silicide, molybdenum silicide, or titanium silicide.

In the above embodiment, the step of embedding the conductive pattern (floating electrode) in the insulating layer was performed by forming the floating electrode 23 on the oxide film 22 and depositing the 5102 film 24 by bias sputtering. but not limited to.

For example, first, a phosphorus-doped polycrystalline silicon film 32 is deposited on the oxide film 22 of the p-type silicon substrate 21, and an oxidation-resistant silicon nitride pattern 33 is deposited on the polycrystalline silicon film 32.
(as shown in FIG. 2(a)). Next, a thermal oxidation process is performed using the silicon nitride pattern 33 as a mask to oxidize the exposed polycrystalline silicon film, and after removing the silicon nitride pattern 33, the surface layer of the remaining polycrystalline silicon film is oxidized to oxidize the exposed polycrystalline silicon film. Substrate 2 as shown in figure (b)
A polycrystalline silicon pattern (floating electrode) 23' may be formed, which is buried with the oxide film 22 and the thermal oxide film 34 on the oxide film 1.

In the above embodiment, single crystal silicon is used as a means of selecting the concentration and thickness of the region between the source and drain regions of the semiconductor layer so that the depletion layer generated when a voltage is applied to the gate electrode reaches the surface of the insulating layer. Although this was carried out at the time of layer formation, the present invention is not limited thereto. For example, the above object may be achieved by forming a single crystal silicon layer, forming a field oxide film, and then implanting impurity ions into each island region to adjust the concentration.

〔Effect of the invention〕

As described in detail above, according to the present invention, the threshold voltage can be changed with a simple operation without changing the impurity concentration etc. of the channel region.
A MOS type semiconductor device applicable to P'R' OM and the like can be provided.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are cross-sectional views showing the manufacturing process for obtaining an n-channel O8 IC in an embodiment of the present invention,
2(a) and 2(b) are cross-sectional views showing the process of forming a conductive pattern according to another embodiment of the present invention, FIG. 3 is a cross-sectional view showing a conventional multivalued logic circuit, and FIG. 4 is a conventional FIG. 21...p-type silicon substrate, 22... oxide film, 23
．． 23'...polycrystalline silicon pattern (floating electrode),
24...5i02HIA, 25... Single crystal silicon layer, 26... Field oxide film, 27... Gate electrode, 28... Gate oxide film, 29... Source region,
30...Drain region, 33...Silicon nitride pattern, 34...Thermal oxidation jI.

Claims (2)

[Claims] (1) a semiconductor layer provided on an insulating layer; a source and drain region of one conductivity type provided in this semiconductor layer and electrically separated from each other so as to reach the surface of the insulating layer;
In these MOS type semiconductor devices equipped with a gate electrode provided through a gate oxide film on the surface of the semiconductor layer including the channel region between the source and drain regions, a conductive pattern is formed in the insulating layer to connect other semiconductor elements or A MOS type semiconductor device characterized by being buried and insulated from wiring. (2) The impurity concentration and thickness of the semiconductor layer region between the source and drain regions are adjusted so that at least a portion of the depletion layer formed in the semiconductor layer region reaches the surface of the insulating layer by applying a bias to the gate electrode. A MOS type semiconductor device according to claim 1, characterized in that the MOS type semiconductor device is selected as follows.