JPH09321307A - Semiconductor device - Google Patents
Semiconductor deviceInfo
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- JPH09321307A JPH09321307A JP13503796A JP13503796A JPH09321307A JP H09321307 A JPH09321307 A JP H09321307A JP 13503796 A JP13503796 A JP 13503796A JP 13503796 A JP13503796 A JP 13503796A JP H09321307 A JPH09321307 A JP H09321307A
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- layer
- sige
- strain
- semiconductor layer
- channel
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- Junction Field-Effect Transistors (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＯＳＦＥＴやＨ
ＥＭＴ等のようにチャネルが誘起されるチャネル半導体
層を有する半導体素子を備えた半導体装置に関する。TECHNICAL FIELD The present invention relates to a MOSFET and an H
The present invention relates to a semiconductor device including a semiconductor element having a channel semiconductor layer in which a channel is induced, such as EMT.
【０００２】[0002]
【従来の技術】コンピュ−タ−や通信機器の重要部分に
は、多数のトランジスタや抵抗等を電気回路を達成する
ようにむすびつけ、１チップ上に集積化して形成した大
規模集積回路（ＬＳＩ）が多用されている。このため、
機器全体の性能は、ＬＳＩ単体の性能と大きく結び付い
ている。2. Description of the Related Art An important part of a computer or a communication device is a large-scale integrated circuit (LSI) formed by integrating a large number of transistors, resistors, and the like so as to achieve an electric circuit. Is often used. For this reason,
The performance of the entire device is greatly linked to the performance of the LSI alone.
【０００３】ＬＳＩ単体の性能向上、例えば、Ｓｉ系Ｍ
ＯＳデバイス等で構成されるＬＳＩ単体の性能向上にお
いては、高速かつ低消費電力を特徴とするＭＯＳＦＥＴ
の改良が不可欠である。このため、例えば、電子移動度
等の電気的特性の向上を目的とした研究開発が精力的に
行なわれている。[0003] Performance improvement of a single LSI, for example, Si-based M
In order to improve the performance of an LSI composed of OS devices, etc., MOSFETs featuring high speed and low power consumption
Improvement of is essential. For this reason, for example, research and development have been vigorously carried out for the purpose of improving electrical characteristics such as electron mobility.
【０００４】しかし、チャネルが誘起されるチャネル半
導体層の構造についての検討は、その緒についたばかり
である。電子移動度を高めるための技術の１つとして、
チャネル半導体層に歪みをかける技術が知られている。
チャネル半導体層に歪みをかけると、そのバンド構造が
変化し、その結果、縮退が解けて電子散乱が抑制される
ので、電子移動度を高めることが可能となる。However, the study on the structure of the channel semiconductor layer in which the channel is induced has just begun. As one of the technologies to increase electron mobility,
A technique of applying strain to a channel semiconductor layer is known.
When strain is applied to the channel semiconductor layer, its band structure changes, and as a result, degeneracy is released and electron scattering is suppressed, so that electron mobility can be increased.
【０００５】具体的には、シリコン基板上にシリコンよ
りも格子定数の大きな材料からなる混晶層、例えば、Ｇ
ｅ濃度２０％のＳｉＧｅ混晶層（以下、単にＳｉＧｅ層
という）を形成し、このＳｉＧｅ層上にチャネル半導体
層としてのシリコン層を形成すると、格子定数の違いに
より、歪みのかかったシリコン層（以下、歪みチャネル
層という）が形成される。このような歪みチャネル層を
用いると、無歪みチャネル層を用いた場合の約１．７６
倍と大幅な電子移動度の向上を達成できることが報告さ
れている（J.Welser,J.L.Hoyt,S.Takagi, and J.F.Gibb
ons,IEDM 94-373 ）。Specifically, a mixed crystal layer made of a material having a lattice constant larger than that of silicon, such as G, is formed on a silicon substrate.
When a SiGe mixed crystal layer having an e concentration of 20% (hereinafter simply referred to as a SiGe layer) is formed and a silicon layer as a channel semiconductor layer is formed on this SiGe layer, a strained silicon layer ( Hereinafter, a strained channel layer) is formed. When such a strained channel layer is used, it is about 1.76 when a non-strained channel layer is used.
It has been reported that a double increase in electron mobility can be achieved (J.Welser, JLHoyt, S.Takagi, and JFGibb.
ons, IEDM 94-373).
【０００６】他方、電子移動度の向上のために、ＭＯＳ
ＦＥＴの短チャネル化を進めると、浮遊容量の影響が大
きくなるため、期待通りに電子移動度を向上することは
困難になる。On the other hand, in order to improve electron mobility, MOS
If the channel length of the FET is shortened, the influence of the stray capacitance increases, and it is difficult to improve the electron mobility as expected.
【０００７】そこで、ＳＯＩ（Silicon On Insulator）
基板にＭＯＳＦＥＴを作成することが検討されている。
ＳＯＩ基板の形成方法としては、張り合わせ基板等の幾
つかの方法が提案されているが、ＳＯＩ基板の酸化層と
その上のシリコン層の各々の膜厚を最適な寸法に形成で
きる方法として、シリコン基板に酸素イオンを注入した
後、このシリコン基板に高温熱処理を施して該基板内部
に埋め込み酸化層を形成するという、通称ＳＩＭＯＸ
（Separation by Implanted Oxygen）と呼ばれる方法が
広く用いられている。Therefore, SOI (Silicon On Insulator)
Fabrication of MOSFETs on a substrate is under consideration.
As a method for forming an SOI substrate, several methods such as a bonded substrate have been proposed. As a method for forming the oxide layer of the SOI substrate and the silicon layer on the oxide layer to have optimum film thicknesses, a silicon substrate is used. After implanting oxygen ions into the substrate, the silicon substrate is subjected to high temperature heat treatment to form a buried oxide layer inside the substrate, which is commonly known as SIMOX.
A method called (Separation by Implanted Oxygen) is widely used.
【０００８】図３に、ＳＯＩ基板に作成したＭＯＳＦＥ
Ｔの断面構造を示す。図中、５１はシリコン基板、５２
は酸化層、５３はシリコン層を示しており、これらはＳ
ＯＩ基板を構成している。FIG. 3 shows a MOSFE formed on an SOI substrate.
A sectional structure of T is shown. In the figure, 51 is a silicon substrate, 52
Is an oxide layer and 53 is a silicon layer. These are S
It constitutes an OI substrate.
【０００９】シリコン層５３上にはＳｉＧｅ混晶層（以
下、単にＳｉＧｅ層という）５４が形成され、このＳｉ
Ｇｅ層５４上には歪みシリコン層５５が形成されてい
る。これらシリコン層５３、ＳｉＧｅ層５４および歪み
シリコン層５５には酸化層５２に達する素子分離絶縁膜
５６が形成されている。A SiGe mixed crystal layer (hereinafter simply referred to as SiGe layer) 54 is formed on the silicon layer 53.
A strained silicon layer 55 is formed on the Ge layer 54. An element isolation insulating film 56 reaching the oxide layer 52 is formed on the silicon layer 53, the SiGe layer 54, and the strained silicon layer 55.
【００１０】歪みシリコン層５５上にはゲート酸化膜５
７、ゲート電極５８が順次形成されている。また、この
ゲート電極５８をマスクに用いたイオン注入により、歪
みシリコン層５５およびＳｉＧｅ層５４には、ｎ型ソー
ス領域５９およびｎ型ドレイン領域６０が自己整合に形
成されている。A gate oxide film 5 is formed on the strained silicon layer 55.
7 and a gate electrode 58 are sequentially formed. Further, an n-type source region 59 and an n-type drain region 60 are formed in the strained silicon layer 55 and the SiGe layer 54 in a self-aligned manner by ion implantation using the gate electrode 58 as a mask.
【００１１】そして、全面にはゲート電極５８を覆うよ
うに層間絶縁膜６１が形成され、この層間絶縁膜６１に
開口されたコンタクトホールを介してソース電極６２、
ドレイン電極６３がそれぞれｎ型ソース領域５９、ｎ型
ドレイン領域６０に接続している。An interlayer insulating film 61 is formed on the entire surface so as to cover the gate electrode 58, and a source electrode 62 is formed through a contact hole opened in the interlayer insulating film 61.
The drain electrode 63 is connected to the n-type source region 59 and the n-type drain region 60, respectively.
【００１２】上述したようなチャネル半導体層に歪みシ
リコン層５５を用い、基板にＳＯＩ基板を用いたＭＯＳ
ＦＥＴを実現できれば、０．１μｍルール以下の微細化
に対しても有効な素子特性が得られるようになる。すな
わち、短チャンネル効果を抑えながら電子移動度の向上
が図れるようになる。A MOS in which the strained silicon layer 55 is used as the channel semiconductor layer and the SOI substrate is used as the substrate as described above.
If an FET can be realized, effective element characteristics can be obtained even with miniaturization of 0.1 μm rule or less. That is, the electron mobility can be improved while suppressing the short channel effect.
【００１３】しかしながら、このようなＭＯＳＦＥＴの
実現に際しては以下のような問題がある。十分な歪みを
有する歪みシリコン層５５を得るには、厚いＳｉＧｅ混
晶バッファ層（以下、単にＳｉＧｅバッファ層という）
を形成し、その上に高Ｇｅ濃度のＳｉＧｅ層５４を形成
する必要がある。例えば、シリコン層５３に対して格子
定数が％オーダで異なる厚さ１００ｎｍ程度のＳｉＧｅ
バッファ層を形成する。However, there are the following problems in realizing such a MOSFET. To obtain the strained silicon layer 55 having a sufficient strain, a thick SiGe mixed crystal buffer layer (hereinafter, simply referred to as SiGe buffer layer)
Must be formed, and the SiGe layer 54 having a high Ge concentration must be formed thereon. For example, SiGe having a thickness of about 100 nm, which has a lattice constant different from that of the silicon layer 53 by%
A buffer layer is formed.
【００１４】しかし、下地のシリコン層５３との格子不
整合によりＳｉＧｅバッファ層内にミスフィット転位や
貫通転位が発生し、これら転位がＳｉＧｅ層５４内に引
き継がれ、さらにこれら転位がＳｉＧｅ層５４上に形成
する歪みシリコン層５５に引き継がれ、素子特性が劣化
するという問題が生じる。However, due to the lattice mismatch with the underlying silicon layer 53, misfit dislocations and threading dislocations are generated in the SiGe buffer layer, and these dislocations are taken over in the SiGe layer 54, and these dislocations are further formed on the SiGe layer 54. Then, the strained silicon layer 55 formed in the above step takes over, resulting in a problem that the device characteristics are deteriorated.
【００１５】仮にＳｉＧｅバッファ層の結晶成長が問題
なく行なわれ、ＳｉＧｅバッファ層内にミスフィット転
位や貫通転位が発生しなくても、後工程における高熱の
熱処理中で緩和が生じて、結果的に転位が生じる可能性
もある。Even if crystal growth of the SiGe buffer layer is carried out without any problem and misfit dislocations or threading dislocations do not occur in the SiGe buffer layer, relaxation occurs during high-temperature heat treatment in the subsequent step, and as a result, Dislocations may also occur.
【００１６】したがって、十分な歪みを有する歪みシリ
コン層５５を得るには、ＳｉＧｅ層５４がシリコン層５
３から受ける歪みを解放した、つまり、ＳｉＧｅ層５４
が緩和した状態で、ＳｉＧｅ層５４上にシリコンを成長
させて歪みシリコン層５５を形成することが望まれる。Therefore, in order to obtain the strained silicon layer 55 having a sufficient strain, the SiGe layer 54 should be replaced with the silicon layer 5.
3 is released, that is, the SiGe layer 54 is released.
Is relaxed, it is desired to grow silicon on the SiGe layer 54 to form the strained silicon layer 55.
【００１７】これを実現するためには、ＳｉＧｅバッフ
ァ層として、シリコン層５３から遠ざかるに従って徐々
にＧｅ濃度が高くなる厚い傾斜組成ＳｉＧｅ層を作成
し、この傾斜組成ＳｉＧｅ層上にＳｉＧｅ層５４、歪み
シリコン層５５を順次形成することが必要となる。In order to realize this, as the SiGe buffer layer, a thick graded composition SiGe layer in which the Ge concentration gradually increases as the distance from the silicon layer 53 is increased, and the SiGe layer 54 and the strain are formed on the graded composition SiGe layer. It is necessary to sequentially form the silicon layer 55.
【００１８】この厚い傾斜組成ＳｉＧｅ層では、貫通転
位、ミスフィット転位等の転位が該層中に閉じ込められ
る。また、ＳｉＧｅ層５４を形成する傾斜組成ＳｉＧｅ
層の表面は十分に緩和している。したがって、表面に転
位がなく、かつ歪みシリコン層５５からの歪みが解放さ
れたＳｉＧｅ層５４が得られ、これにより転位がなく十
分な歪みを有する歪みシリコン層５５を形成できるよう
になる。しかしながら、このＳｉＧｅバッファ層の厚み
は、およそ１μｍ程度となる。In this thick graded composition SiGe layer, dislocations such as threading dislocations and misfit dislocations are confined in the layer. Further, a graded composition SiGe forming the SiGe layer 54 is used.
The surface of the layer is fully relaxed. Therefore, the SiGe layer 54 having no dislocation on the surface and the strain released from the strained silicon layer 55 is obtained, and thus the strained silicon layer 55 having no dislocation and having sufficient strain can be formed. However, the thickness of this SiGe buffer layer is about 1 μm.
【００１９】一方、浮遊容量の低減などのＳＯＩ基板の
効果を得るためには、ＳＯＩ基板のＳＯＩ層の厚み（シ
リコン層５３の膜厚とＳｉＧｅ層５４の膜厚と歪みシリ
コン層５５の膜厚の合計）は０．１μｍ程度以下である
必要がある。On the other hand, in order to obtain the effect of the SOI substrate such as the reduction of the stray capacitance, the thickness of the SOI layer of the SOI substrate (the thickness of the silicon layer 53, the thickness of the SiGe layer 54 and the thickness of the strained silicon layer 55). Must be about 0.1 μm or less.
【００２０】したがって、上述したような厚いＳｉＧｅ
バッファ層（傾斜組成ＳｉＧｅ層）を形成した後に、歪
みシリコン層を形成したのでは、ＳＯＩ基板の効果を享
受できないという問題が生じる。Therefore, the thick SiGe as described above
If the strained silicon layer is formed after forming the buffer layer (graded composition SiGe layer), the effect of the SOI substrate cannot be obtained.
【００２１】さらに、上述した厚いＳｉＧｅバッファ層
（傾斜組成ＳｉＧｅ層）を形成するには、結晶成長時間
がかかるという問題がある。また、表面ラフネスが増加
し、その上に形成する歪みシリコン層５５の膜質が低下
するという問題もある。Further, there is a problem that it takes a crystal growth time to form the thick SiGe buffer layer (gradient composition SiGe layer) described above. There is also a problem that the surface roughness increases and the film quality of the strained silicon layer 55 formed thereon deteriorates.
【００２２】[0022]
【発明が解決しようとする課題】上述の如く、チャネル
半導体層に歪みシリコン層を用い、基板にＳＯＩ基板を
用いたＭＯＳＦＥＴを実現できれば、０．１μｍルール
以下の微細化に対しても、短チャンネル効果を抑えなが
ら電子移動度の向上が図れるとともに、ドレイン電流も
大きく取れるようになる。As described above, if a MOSFET in which a strained silicon layer is used as a channel semiconductor layer and an SOI substrate is used as a substrate can be realized, a short channel can be obtained even with a miniaturization of 0.1 μm rule or less. The electron mobility can be improved while suppressing the effect, and a large drain current can be obtained.
【００２３】転位がなく十分な歪みを有する歪みシリコ
ン層の形成方法として、ＳｉＧｅバッファ層としての厚
い傾斜組成ＳｉＧｅ層上にＳｉＧｅ層を形成し、このＳ
ｉＧｅ層上にシリコンを成長させて歪みシリコン層を形
成する方法が知られている。As a method of forming a strained silicon layer having no dislocation and having a sufficient strain, a SiGe layer is formed on a thick gradient composition SiGe layer as a SiGe buffer layer, and this S
A method of growing silicon on an iGe layer to form a strained silicon layer is known.
【００２４】しかし、厚い傾斜組成ＳｉＧｅ層を形成す
ることにより、歪みシリコン層とＳＯＩ構造を構成する
酸化層との間が大きくなり、ＳＯＩ構造の効果が得られ
なくなるという問題があった。However, by forming a thick gradient composition SiGe layer, the distance between the strained silicon layer and the oxide layer constituting the SOI structure becomes large, and there is a problem that the effect of the SOI structure cannot be obtained.
【００２５】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、ＳＯＩ構造による効果
を失わずに、高品質で十分な歪みを有するチャネル半導
体層を形成できる構造を有する半導体装置を提供するこ
とにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a structure capable of forming a channel semiconductor layer having high quality and sufficient strain without losing the effect of the SOI structure. It is to provide a semiconductor device having the same.
【００２６】[0026]
［概要］上記目的を達成するために、本発明に係る半導
体装置（請求項１）は、チャネルが誘起されるチャネル
半導体層と、格子定数が前記チャネル半導体層のそれと
異なり、前記チャネル半導体層に歪みを印加する歪み印
加半導体層と、この歪み印加半導体層内に形成された絶
縁層とを備えていることを特徴とする。[Outline] In order to achieve the above object, a semiconductor device according to the present invention (claim 1) has a channel semiconductor layer in which a channel is induced and a lattice constant different from that of the channel semiconductor layer. It is characterized in that it is provided with a strain applying semiconductor layer for applying strain and an insulating layer formed in the strain applying semiconductor layer.
【００２７】また、本発明に係る他の半導体装置（請求
項２）は、上記半導体装置（請求項１）において、前記
チャネル半導体層がシリコン層、前記歪み印加半導体層
がシリコンゲルマニウム層であることを特徴とする。Another semiconductor device according to the present invention (claim 2) is that in the semiconductor device (claim 1), the channel semiconductor layer is a silicon layer and the strain applying semiconductor layer is a silicon germanium layer. Is characterized by.
【００２８】この場合、上記絶縁層はＳＩＭＯＸ法によ
り形成することが好ましい。また、本発明に係る他の半
導体装置（請求項３）は、上記半導体装置（請求項１）
において、前記チャネル半導体層が、ＭＯＳＦＥＴのチ
ャネルが誘起される半導体層であることを特徴とする。In this case, the insulating layer is preferably formed by SIMOX method. Another semiconductor device according to the present invention (claim 3) is the above semiconductor device (claim 1).
In the above, the channel semiconductor layer is a semiconductor layer in which a channel of a MOSFET is induced.
【００２９】［作用］本発明の如きの構造によれば、例
えば、以下のような形成方法により、ＳＯＩ構造による
効果を失わずに、十分な歪みを有するチャネル半導体層
を形成できるようになる。[Operation] According to the structure of the present invention, the channel semiconductor layer having a sufficient strain can be formed by the following forming method without losing the effect of the SOI structure.
【００３０】すなわち、まず、後工程で形成するチャネ
ル半導体層に十分な歪みを与えることができる歪み印加
半導体層を形成する。これは例えば歪み印加半導体層が
ＳｉＧｅ層の場合であればＧｅ濃度を高くすれば良い。That is, first, a strain applying semiconductor layer capable of giving a sufficient strain to a channel semiconductor layer formed in a later step is formed. For example, if the strain applying semiconductor layer is a SiGe layer, the Ge concentration may be increased.
【００３１】次に歪み印加半導体層内に絶縁層を形成す
る。これは例えば酸素イオンを歪み印加半導体層内に注
入した後、アニール処理を行なって形成する。この結
果、歪み印加半導体層は絶縁層により上下二つに分離さ
れ、上部歪み印加半導体層／絶縁層／下部歪み印加半導
体層が構造できる。Next, an insulating layer is formed in the strain applying semiconductor layer. This is formed, for example, by implanting oxygen ions into the strain-applied semiconductor layer and then performing annealing treatment. As a result, the strain applying semiconductor layer is divided into upper and lower parts by the insulating layer, and an upper strain applying semiconductor layer / an insulating layer / a lower strain applying semiconductor layer can be structured.
【００３２】このとき、絶縁層、上部歪み印加半導体層
および後工程で形成するチャネル半導体層からなるＳＯ
Ｉ構造と同じ効果を享受できるように、絶縁層を形成す
る位置の深さを選ぶ。すなわち、ＳＯＩ構造による効果
を享受できる程度の薄い上部歪み印加層が得られるよう
に、歪み印加半導体層内に絶縁層を形成する。At this time, SO composed of an insulating layer, an upper strain applying semiconductor layer and a channel semiconductor layer formed in a later step.
The depth of the position where the insulating layer is formed is selected so that the same effect as the I structure can be obtained. That is, an insulating layer is formed in the strain-applied semiconductor layer so that an upper strain-applied layer that is thin enough to obtain the effect of the SOI structure can be obtained.
【００３３】さらに、上記アニール処理により、歪み印
加半導体層の形成時や絶縁層の形成時に、歪み印加半導
体層内に発生した転位等の欠陥が減少する。これによ
り、従来の厚い歪み印加半導体層と同程度数以下の欠陥
を有する高品質な薄い歪み印加半導体層が得られる。Further, the annealing treatment reduces defects such as dislocations generated in the strain-applied semiconductor layer during formation of the strain-applied semiconductor layer or formation of the insulating layer. As a result, a high-quality thin strain-applied semiconductor layer having defects equal to or less than those of the conventional thick strain-applied semiconductor layer can be obtained.
【００３４】最後に、高品質な薄い歪み印加半導体層
（上部歪み印加半導体層）上にチャネル半導体層を形成
する。ここで、上部歪み印加半導体層は、上述したよう
に、高品質でチャネル半導体層に十分な歪みを与えるこ
とができるように形成されているので、高品質で十分な
歪みを有するチャネル半導体層が形成されることにな
る。しかも、チャネル半導体層に歪みを印加する上部歪
み印加層は薄いので、ＳＯＩ構造と同等の効果は得られ
る。したがって、ＳＯＩ構造と同等の効果を失わずに、
高品質で十分な歪みを有するチャネル半導体層を形成で
きることになる。Finally, a channel semiconductor layer is formed on the high quality thin strain applied semiconductor layer (upper strain applied semiconductor layer). Here, since the upper strain application semiconductor layer is formed so as to be able to give sufficient strain to the channel semiconductor layer with high quality, as described above, a channel semiconductor layer with high quality and sufficient strain can be formed. Will be formed. Moreover, since the upper strain applying layer for applying strain to the channel semiconductor layer is thin, the same effect as the SOI structure can be obtained. Therefore, without losing the same effect as the SOI structure,
This makes it possible to form a channel semiconductor layer having high quality and sufficient strain.
【００３５】[0035]
【発明の実施の形態】以下、図面を参照しながら本発明
の実施の形態（以下、実施形態という）を説明する。 （第１の実施形態）先ず、本発明の基本的な考えについ
て説明する。図１に、本発明をＳｉ系ＭＯＳＦＥＴに適
用した場合のプロセスフローを従来法のそれと比較して
示す。この例では歪み印加半導体層としてＳｉＧｅ層を
用いている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) First, the basic idea of the present invention will be described. FIG. 1 shows a process flow when the present invention is applied to a Si-based MOSFET in comparison with that of a conventional method. In this example, a SiGe layer is used as the strain applying semiconductor layer.
【００３６】従来法では、まず、シリコン基板に酸素イ
オンを注入し、このシリコン基板にアニール処理を施し
てシリコン基板内に酸化層を形成することにより、つま
り、ＳＩＭＯＸ法によりＳＯＩ基板を形成する。In the conventional method, first, oxygen ions are implanted into a silicon substrate and the silicon substrate is annealed to form an oxide layer in the silicon substrate, that is, an SOI substrate is formed by the SIMOX method.
【００３７】次にＳｉＧｅバッファ層としてＳＯＩ基板
から離れるに従って結晶中のＧｅ濃度を徐々に高くなる
傾斜組成ＳｉＧｅ層をＳＯＩ基板上に形成する。次にＳ
ｉＧｅバッファ層上にＳｉＧｅを成長させて所望のＧｅ
濃度を有するＳｉＧｅ層を形成する。Next, a graded composition SiGe layer is formed as a SiGe buffer layer on the SOI substrate such that the Ge concentration in the crystal gradually increases as the distance from the SOI substrate increases. Then S
SiGe is grown on the iGe buffer layer to obtain the desired Ge.
A SiGe layer having a concentration is formed.
【００３８】最後に、ＳｉＧｅ層上にシリコンを成長さ
せて歪みシリコン層を形成した後、この歪みシリコン層
をチャネル半導体層とするＭＯＳＦＥＴを形成する。こ
れに対し、本発明では、まず、シリコン基板上にＳｉＧ
ｅを成長させて歪み印加半導体層としてのＳｉＧｅ層を
形成する。このとき、ＳｉＧｅ層のＧｅ濃度は、後工程
で形成する歪みシリコン層の歪みの大きさが十分に大き
くなるように選ぶ。Finally, after growing silicon on the SiGe layer to form a strained silicon layer, a MOSFET having the strained silicon layer as a channel semiconductor layer is formed. On the other hand, in the present invention, first, SiG is formed on the silicon substrate.
e is grown to form a SiGe layer as a strain application semiconductor layer. At this time, the Ge concentration of the SiGe layer is selected so that the magnitude of strain of the strained silicon layer formed in a later step becomes sufficiently large.
【００３９】次にＳｉＧｅ層に酸素イオンを注入した
後、このＳｉＧｅ層にアニール処理を施すことにより、
ＳｉＧｅ層内に埋め込み絶縁層を形成する。この結果、
ＳｉＧｅ層は埋め込み絶縁層により上下二つに分離され
る。以下、分離された上側のＳｉＧｅ層を上部ＳｉＧｅ
層、下側のＳｉＧｅ層を下部ＳｉＧｅ層という。Next, after implanting oxygen ions into the SiGe layer, the SiGe layer is annealed to obtain
A buried insulating layer is formed in the SiGe layer. As a result,
The SiGe layer is separated into upper and lower parts by the buried insulating layer. Hereinafter, the separated upper SiGe layer is referred to as the upper SiGe layer.
Layer, the lower SiGe layer is referred to as the lower SiGe layer.
【００４０】この工程時に、上部ＳｉＧｅ層の膜厚が薄
くなるように、埋め込み絶縁層をＳｉＧｅ層の浅い位置
に形成する。これにより、埋め込み絶縁層と次の工程で
形成する歪みシリコン層との間を短くできるので、埋め
込み絶縁層、上部ＳｉＧｅ層および歪みシリコン層によ
り構成されるＳＯＩ構造と同等の浮遊容量低減等の効果
を享受できるようになる。At this step, the buried insulating layer is formed at a shallow position of the SiGe layer so that the film thickness of the upper SiGe layer becomes thin. As a result, the distance between the buried insulating layer and the strained silicon layer formed in the next step can be shortened, so that an effect similar to that of the SOI structure formed by the buried insulating layer, the upper SiGe layer, and the strained silicon layer can be reduced. Will be able to enjoy.
【００４１】さらに、ＳｉＧｅ層に酸素イオンを注入し
た後のアニール処理により、ＳｉＧｅ層の形成時および
酸素イオン注入時に生じた転位等の欠陥を修復できるの
で、ＳｉＧｅバッファ層を形成しなくても、高品質な上
部ＳｉＧｅ層、下側ＳｉＧｅ層が得られる。Further, by performing an annealing treatment after implanting oxygen ions into the SiGe layer, defects such as dislocations generated at the time of forming the SiGe layer and at the time of implanting oxygen ions can be repaired. Therefore, even if the SiGe buffer layer is not formed. A high quality upper SiGe layer and a lower quality SiGe layer are obtained.
【００４２】したがって、従来よりも少ない工程数（１
工程短縮）で、ＳＯＩ構造と同等の効果を失わずに、高
品質で大きな歪みを有する歪みシリコン層を形成できる
高品質で薄い上部ＳｉＧｅ層（歪み印加半導体層）が得
られることになる。Therefore, the number of steps (1
By shortening the process, it is possible to obtain a high-quality thin upper SiGe layer (strain-applied semiconductor layer) capable of forming a high-quality strained silicon layer having a large strain without losing the same effect as the SOI structure.
【００４３】最後に、上部ＳｉＧｅ層上にシリコンを成
長させて歪みシリコン層を形成した後、この歪みシリコ
ン層をチャネル半導体層とするＭＯＳＦＥＴを形成す
る。なお、上部ＳｉＧｅ層上に新たなＳｉＧｅ層を形成
し、このＳｉＧｅ層上に歪みシリコン層を形成した後、
この歪みシリコン層にＭＯＳＦＥＴを形成しても良い。
この場合、より高品質なＳｉＧｅ層が得られるので、さ
らに素子特性の優れたＭＯＳＦＥＴを形成できるように
なる。Finally, after growing silicon on the upper SiGe layer to form a strained silicon layer, a MOSFET having the strained silicon layer as a channel semiconductor layer is formed. After forming a new SiGe layer on the upper SiGe layer and forming a strained silicon layer on this SiGe layer,
A MOSFET may be formed on this strained silicon layer.
In this case, since a higher quality SiGe layer is obtained, it becomes possible to form a MOSFET having more excellent device characteristics.
【００４４】次に本発明の具体的な実施形態について説
明する。図２は、本発明の一実施形態に係るｎ型ＭＯＳ
ＦＥＴの素子構造を示す断面図である。これを製造工程
に従い説明すると、まず、例えば、ＲＣＡ法等の洗浄法
を用いて自然酸化膜等が除去された清浄なシリコン基板
１を準備する。Next, specific embodiments of the present invention will be described. FIG. 2 shows an n-type MOS according to an embodiment of the present invention.
It is sectional drawing which shows the element structure of FET. This will be described according to the manufacturing process. First, for example, a clean silicon substrate 1 from which a natural oxide film and the like have been removed by using a cleaning method such as the RCA method is prepared.
【００４５】次にシリコン基板１上に厚さ１μｍ程度の
ＳｉＧｅ層２を形成する。ＳｉＧｅ層２のＧｅ濃度は、
後工程で形成する歪みシリコン層４の歪みが十分に大き
くなるように高くする。Next, a SiGe layer 2 having a thickness of about 1 μm is formed on the silicon substrate 1. The Ge concentration of the SiGe layer 2 is
The strain is increased so that the strain of the strained silicon layer 4 formed in the subsequent step becomes sufficiently large.
【００４６】ここで、Ｇｅ濃度を急激に増加させながら
ＳｉＧｅ層２を形成すると、シリコン基板１とＳｉＧｅ
層２の格子定数の違いにより生じる格子不整合によっ
て、ＳｉＧｅ層２中に無用の貫通転位、あるいはミスフ
ィット転位を含む欠陥を誘起することになるので、Ｇｅ
濃度はＳｉＧｅ層２の中で徐々に増加させ、表面で所望
濃度となるようにすることが好ましい。Here, when the SiGe layer 2 is formed while the Ge concentration is rapidly increased, the silicon substrate 1 and the SiGe layer are formed.
Due to the lattice mismatch caused by the difference in the lattice constant of the layer 2, defects that include unnecessary threading dislocations or misfit dislocations are induced in the SiGe layer 2, so Ge
It is preferable that the concentration is gradually increased in the SiGe layer 2 so that the surface has a desired concentration.
【００４７】膜厚１μｍという値は、ＳｉＧｅ層２のデ
バイス側に近い部分のＧｅ組成比を０．３と設計すると
きに用いる典型的な値である。Ｇｅ組成比は大きい方が
良く、０．２を大きく下回る場合には、ＳｉＧｅ層２上
に形成するＭＯＳＦＥＴの移動度の顕著な向上は期待で
きない。また、０．５を大きく越える場合には、ＳｉＧ
ｅ層２の表面凹凸（表面ラフネス）の増加や、膜質の低
下等の問題が生じる可能性がある。これらの点を考慮し
てＧｅ組成比を設定すれば、本発明の効果はより顕著に
発揮されるようになる。The value of 1 μm is a typical value used when designing the Ge composition ratio of the portion of the SiGe layer 2 close to the device side to be 0.3. The larger the Ge composition ratio, the better. If it is much lower than 0.2, the mobility of the MOSFET formed on the SiGe layer 2 cannot be significantly improved. If it exceeds 0.5, SiG
There is a possibility that problems such as an increase in surface irregularities (surface roughness) of the e-layer 2 and deterioration of film quality may occur. If the Ge composition ratio is set in consideration of these points, the effect of the present invention becomes more prominent.
【００４８】ＳｉＧｅ層２の具体的な成膜方法は以下の
通りである。すなわち、原料としてＳｉＨ4 およびＧｅ
Ｈ4 を用い、成長温度を５００℃に設定し、成長圧力を
１０-3Ｐａに設定して、真空容器中でＣＶＤ法により形
成する。The specific film forming method of the SiGe layer 2 is as follows. That is, SiH 4 and Ge are used as raw materials.
Using H 4 , the growth temperature is set to 500 ° C., the growth pressure is set to 10 −3 Pa, and the film is formed by the CVD method in a vacuum container.
【００４９】ＳｉＧｅを成長させるには、このようなＣ
ＶＤ法や、ＭＢＥ（Molecular BeamEpitaxy）法等のエ
ピタキシャル成長法が広く用いられるが、Ｇｅ組成比の
制御が可能な結晶成長方法であれば、他の成膜法を用い
ても良い。To grow SiGe, such C
Although an epitaxial growth method such as a VD method and an MBE (Molecular Beam Epitaxy) method is widely used, another film formation method may be used as long as it is a crystal growth method capable of controlling the Ge composition ratio.
【００５０】例えば、ＬＰＥ（Liquid Phase Epitaxy）
法等の液相成長法や、ポリＳｉＧｅ層あるいはアモルフ
ァスＳｉＧｅ層の加熱による固相成長法でもＳｉＧｅ層
２を形成できる。For example, LPE (Liquid Phase Epitaxy)
The SiGe layer 2 can also be formed by a liquid phase growth method such as a method or a solid phase growth method by heating a poly SiGe layer or an amorphous SiGe layer.
【００５１】また、ここでは、真空下（成長圧力１０-3
Ｐａ）でのＣＶＤ法の場合について説明したが、数百Ｔ
ｏｒｒの成長圧力による減圧あるいは常圧、加圧下でも
成長が可能である。Further, here, under vacuum (growth pressure 10 −3
Although the case of the CVD method in Pa) was explained, several hundred T
The growth can be performed under reduced pressure by the growth pressure of orr or under normal pressure or pressure.
【００５２】Ｓｉ原料としてはＳｉＨ4 、Ｓｉ2 Ｈ6 、
Ｓｉ2 Ｈ4 Ｃｌ2 等、Ｇｅ原料としてはＧｅＨ4 、Ｇｅ
Ｆ4 、Ｇｅ2 Ｈ8 等が適している。これら原料のガスは
キャリアガスを用いて真空容器内に導入しても良い。キ
ャリアガスとしては、例えば、水素ガス、窒素ガス、ヘ
リウムガスまたはアルゴン等の不活性ガス等があげられ
る。As the Si raw material, SiH 4 , Si 2 H 6 ,
Si 2 H 4 Cl 2, etc., GeH 4 , Ge as a Ge raw material
F 4 , Ge 2 H 8 and the like are suitable. These raw material gases may be introduced into the vacuum container using a carrier gas. Examples of the carrier gas include hydrogen gas, nitrogen gas, helium gas, inert gas such as argon, and the like.
【００５３】また、原料を予めプラズマ、光等により分
解して、成長に必要なエネルギーを有する成長に寄与す
る種を生成し、これを結晶成長に利用しても良い。ま
た、ＳｉＧｅ層２を形成する際に、Ｂ、Ａｓ、Ｐ等の不
純物源となるＢ2 Ｈ6 、ＡｓＨ3 、ＰＨ3 等を原料と同
時に真空容器内に導入して、ＳｉＧｅ層２が所定の導電
型になるようにしても良いし、あるいはＳｉＧｅ層２を
形成した後にＢ、Ａｓ、Ｐ等を拡散によりＳｉＧｅ層２
内に導入して、ＳｉＧｅ層２が所定の導電型になるよう
にしても良い。また、Ｂ、Ａｓ、Ｐ以外にＧａ、Ｓｂ、
Ｓｎ、Ａｌ、Ｎ等を用いても良い。Alternatively, the raw material may be decomposed in advance by plasma, light or the like to generate seeds having energy necessary for growth and contributing to growth, and the seeds may be used for crystal growth. Further, when the SiGe layer 2 is formed, B 2 H 6 , AsH 3 , PH 3 and the like, which are impurity sources of B, As, P, etc., are introduced into the vacuum container at the same time as the raw materials so that the SiGe layer 2 is formed to a predetermined size. Of the conductivity type, or after the SiGe layer 2 is formed, B, As, P, etc. are diffused to form the SiGe layer 2.
The SiGe layer 2 may be introduced into the inside so that the SiGe layer 2 has a predetermined conductivity type. In addition to B, As, P, Ga, Sb,
Sn, Al, N or the like may be used.
【００５４】次にドーズ量５×１０17ｃｍ-2の条件で酸
素イオンをＳｉＧｅ層２の上から注入した後、１３００
℃のアニール処理を施して、良好な埋め込み絶縁層３を
ＳｉＧｅ層２内に形成する。Next, oxygen ions were implanted from above the SiGe layer 2 under the condition of a dose amount of 5 × 10 17 cm -2 , and then 1300.
A good buried insulating layer 3 is formed in the SiGe layer 2 by annealing at a temperature of ℃.
【００５５】ＳｉＧｅ層２は埋め込み絶縁層３により上
下二つに分離される。以下、分離された上側のＳｉＧｅ
層２を上部ＳｉＧｅ層２、下側のＳｉＧｅ層２を下部Ｓ
ｉＧｅ層２という。The SiGe layer 2 is separated into upper and lower parts by the buried insulating layer 3. Below, the separated upper SiGe
The layer 2 is the upper SiGe layer 2, and the lower SiGe layer 2 is the lower S
It is called iGe layer 2.
【００５６】この工程時に、上部ＳｉＧｅ層２の膜厚が
薄くなるように、埋め込み絶縁層３をＳｉＧｅ層２の浅
い位置に形成する。また、上記アニール処理でＳｉＧｅ
層２内の転位等の欠陥が修復され、高品質なＳｉＧｅ層
２が形成される。At this step, the buried insulating layer 3 is formed at a shallow position of the SiGe layer 2 so that the film thickness of the upper SiGe layer 2 becomes thin. In addition, the above annealing treatment causes SiGe
Defects such as dislocations in the layer 2 are repaired and a high quality SiGe layer 2 is formed.
【００５７】したがって、埋め込み絶縁層３上には、歪
み印加半導体層として、高品質で薄い上部ＳｉＧｅ層２
が形成されることになる。次に成長温度を５００℃に設
定してＣＶＤ法により上部ＳｉＧｅ層２上にシリコンを
成長させて厚さ３０ｎｍの歪みシリコン層４を形成す
る。この歪みシリコン層４の歪みは引っ張り歪みであ
る。Therefore, on the buried insulating layer 3, a high quality and thin upper SiGe layer 2 is formed as a strain applying semiconductor layer.
Is formed. Next, the growth temperature is set to 500 ° C. and silicon is grown on the upper SiGe layer 2 by the CVD method to form the strained silicon layer 4 having a thickness of 30 nm. The strain of the strained silicon layer 4 is tensile strain.
【００５８】上部ＳｉＧｅ層２のＧｅ濃度は高いので、
歪みシリコン層４は、電子移動度の向上を図るのに十分
な大きさの引っ張り歪みを有したものとなる。さらに、
上部ＳｉＧｅ層２内の転位等の欠陥は低減されているの
で、高品質な歪みシリコン層４が形成される。Since the Ge concentration of the upper SiGe layer 2 is high,
The strained silicon layer 4 has a tensile strain that is large enough to improve the electron mobility. further,
Since defects such as dislocations in the upper SiGe layer 2 are reduced, a high quality strained silicon layer 4 is formed.
【００５９】さらまた、本実施形態では、埋め込み絶縁
層３、上部ＳｉＧｅ層２および歪みシリコン層４により
ＳＯＩ構造（SiGe On Insulator 構造）が形成されてい
るが、上部ＳｉＧｅ層２の膜厚は薄いので、上記ＳＯＩ
構造による浮遊容量低減等の効果は十分に発揮される。Furthermore, in this embodiment, the SOI structure (SiGe On Insulator structure) is formed by the buried insulating layer 3, the upper SiGe layer 2 and the strained silicon layer 4, but the upper SiGe layer 2 is thin. So the above SOI
The effect of reducing the stray capacitance due to the structure is sufficiently exhibited.
【００６０】したがって、本実施形態によれば、上記Ｓ
ＯＩ構造の利点およびチャネル層として歪みシリコン層
を用いた利点を有するＭＯＳＦＥＴを実現できるように
なる。Therefore, according to this embodiment, the above S
It becomes possible to realize a MOSFET having the advantages of the OI structure and the advantages of using the strained silicon layer as the channel layer.
【００６１】また、ＭＯＳＦＥＴの短チャネル効果の抑
制または駆動電流の向上、あるいはこれらを同時に効果
的に図るためには、歪みシリコン層４の膜厚は２０ｎｍ
以下であることが望ましい。Further, in order to suppress the short channel effect of the MOSFET, improve the driving current, or effectively achieve these simultaneously, the thickness of the strained silicon layer 4 is 20 nm.
It is desirable that:
【００６２】次にトレンチ分離法により素子分離絶縁膜
５を形成する。なお、トレンチ分離法の代わりにＬＯＣ
ＯＳ分離法等の他の素子分離法を用いても良い。この素
子分離絶縁膜５により、ｎ型ＭＯＳＦＥＴの形成予定領
域と、これに隣り合う別のデバイス、例えば、ｐ型ＭＯ
ＳＦＥＴの形成予定領域とが分離される。Next, the element isolation insulating film 5 is formed by the trench isolation method. LOC is used instead of the trench isolation method.
Other element isolation methods such as the OS isolation method may be used. By this element isolation insulating film 5, a region in which an n-type MOSFET is to be formed and another device adjacent thereto are formed, for example, a p-type MO.
The SFET formation planned region is separated.
【００６３】次に歪みシリコン層４の表面を熱酸化して
できるだけ薄いゲート酸化膜６を形成する。ゲート酸化
膜６の膜厚は１０ｎｍ程度以下であることが望ましい。
次にしきい値電圧調整用の不純物イオンをゲート酸化膜
６を介してチャネル領域に注入し、ｎ型チャネル領域を
形成する。Next, the surface of the strained silicon layer 4 is thermally oxidized to form the gate oxide film 6 as thin as possible. The film thickness of the gate oxide film 6 is preferably about 10 nm or less.
Next, impurity ions for adjusting the threshold voltage are implanted into the channel region through the gate oxide film 6 to form an n-type channel region.
【００６４】次にゲート酸化膜６上にゲート電極７とな
る多結晶シリコン膜を減圧ＣＶＤ法により形成した後、
上記多結晶シリコン膜を反応性イオンエッチング（ＲＩ
Ｅ）等の異方性エッチングによりパターニングして、ゲ
ート電極７を形成する。このとき、ゲート酸化膜６も同
様にパターニングし、ゲート電極７下以外のゲート酸化
膜６を除去する。Next, after forming a polycrystalline silicon film to be the gate electrode 7 on the gate oxide film 6 by the low pressure CVD method,
Reactive ion etching (RI
The gate electrode 7 is formed by patterning by anisotropic etching such as E). At this time, the gate oxide film 6 is similarly patterned to remove the gate oxide film 6 except under the gate electrode 7.
【００６５】次にゲート電極７をマスクにして、ｎ型Ｍ
ＯＳＦＥＴ形成領域にリンイオン等のｎ型不純物イオン
を選択的に注入した後、８００℃程度のアニール処理を
施して、ｎ型ソース領域８、ｎ型ドレイン領域９を自己
整合的に形成する。Next, using the gate electrode 7 as a mask, an n-type M
After selectively implanting n-type impurity ions such as phosphorus ions into the OSFET formation region, annealing is performed at about 800 ° C. to form the n-type source region 8 and the n-type drain region 9 in a self-aligned manner.
【００６６】次に全面にシリコン酸化膜またはシリコン
窒化膜などの層間絶縁膜１０をＣＶＤ法により形成した
後、この層間絶縁膜１０にゲート領域、ソース領域、ド
レイン領域に対するコンタクトホールを開口する。Next, after an interlayer insulating film 10 such as a silicon oxide film or a silicon nitride film is formed on the entire surface by the CVD method, contact holes for the gate region, the source region and the drain region are opened in this interlayer insulating film 10.
【００６７】最後に、全面にＡｌ膜等の導電膜を堆積し
た後、この導電膜をパターニングして、ソース電極１
１、ドレイン電極１２、ゲート引き出し電極（不図示）
を形成して、ｎ型ＭＯＳＦＥＴが完成する。Finally, after depositing a conductive film such as an Al film on the entire surface, the conductive film is patterned to form the source electrode 1.
1, drain electrode 12, gate extraction electrode (not shown)
Are formed to complete the n-type MOSFET.
【００６８】以上述べたように本実施形態によれば、Ｓ
ＯＩ構造による効果およびチャネル層として歪みシリコ
ン層を用いた効果を同時に得られるＭＯＳＦＥＴを実現
できるようになる。これにより、微細化を進めても期待
通りの素子特性を有するＭＯＳＦＥＴの実現が可能とな
る。As described above, according to this embodiment, S
It becomes possible to realize a MOSFET that can simultaneously obtain the effect of the OI structure and the effect of using the strained silicon layer as the channel layer. As a result, it is possible to realize a MOSFET having the expected device characteristics even if miniaturization is advanced.
【００６９】なお、本発明は上述した実施形態に限定さ
れるものではない。例えば、上記実施形態では、歪み印
加半導体層として、ＳｉＧｅ層を用いた場合について説
明したが、ＳｉＧｅ層の代わりに、ＳｉＣやＳｉＮ等の
ようにＳｉと他の元素との混晶層、ＺｎＳｅ層等の II-
VI族混晶層もしくはＧａＡｓやＩｎＰ等の III-V族混晶
層などの互いに格子定数の異なる材料からなる混晶層で
も良い。The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the SiGe layer is used as the strain application semiconductor layer has been described, but instead of the SiGe layer, a mixed crystal layer of Si and another element such as SiC or SiN, a ZnSe layer. II-
A mixed crystal layer made of materials having different lattice constants, such as a Group VI mixed crystal layer or a III-V mixed crystal layer such as GaAs or InP, may be used.
【００７０】また、上記実施形態では、ＭＯＳＦＥＴの
場合について説明したが、本発明はチャネル半導体層に
歪みを印加することが可能な構造の半導体素子を有する
半導体装置であれば適用できる。In the above embodiment, the case of the MOSFET has been described, but the present invention can be applied to any semiconductor device having a semiconductor element having a structure capable of applying strain to the channel semiconductor layer.
【００７１】例えば、ＭＯＳ構造を有するＣＭＯＳやＢ
ｉＣＭＯＳ等の半導体素子や、ＨＥＭＴ（High Elector
on Mobility Transistor）を有する半導体装置にも適用
できる。その他、本発明の要旨を逸脱しない範囲で、種
々変形して実施できる。For example, CMOS or B having a MOS structure
Semiconductor devices such as iCMOS and HEMT (High Elector)
It can also be applied to a semiconductor device having on Mobility Transistor). In addition, various modifications can be made without departing from the scope of the present invention.
【００７２】[0072]
【発明の効果】以上詳述したように本発明によれば、Ｓ
ＯＩ構造による効果を失わずに、高品質で十分な歪みを
有するチャネル半導体層を形成できる構造の半導体装置
を提供できるようになる。As described in detail above, according to the present invention, S
It is possible to provide a semiconductor device having a structure in which a channel semiconductor layer having high quality and sufficient strain can be formed without losing the effect of the OI structure.
【図１】本発明をＳｉ系ＭＯＳＦＥＴに適用した場合の
プロセスフローを従来法のそれと比較して示す図FIG. 1 is a diagram showing a process flow when the present invention is applied to a Si-based MOSFET in comparison with that of a conventional method.
【図２】本発明の一実施形態に係るｎ型ＭＯＳＦＥＴの
素子構造を示す断面図FIG. 2 is a sectional view showing an element structure of an n-type MOSFET according to an embodiment of the present invention.
【図３】従来のＳＯＩ基板を用いたｎ型ＭＯＳＦＥＴの
素子構造を示す断面図FIG. 3 is a sectional view showing an element structure of an n-type MOSFET using a conventional SOI substrate.
１…シリコン基板 ２…ＳｉＧｅ層（歪み印加半導体層） ３…埋め込み絶縁層 ４…歪みシリコン層（チャネル半導体層） ５…素子分離絶縁膜 ６…ゲート酸化膜 ７…ゲート電極 ８…ｎ型ソース領域 ９…ｎ型ドレイン領域 １０…層間絶縁膜 １１…ソース電極 １２…ドレイン電極 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... SiGe layer (strain-applied semiconductor layer) 3 ... Buried insulating layer 4 ... Strained silicon layer (channel semiconductor layer) 5 ... Element isolation insulating film 6 ... Gate oxide film 7 ... Gate electrode 8 ... N-type source region 9 ... N-type drain region 10 ... Interlayer insulating film 11 ... Source electrode 12 ... Drain electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/338 Ｈ０１Ｌ 29/78 ３０１Ｂ 29/812 ６１８Ｂ 9447−4Ｍ 29/80 Ｈ (72)発明者 手塚 勉 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 (72)発明者 平岡 佳子 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 (72)発明者 黒部 篤 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical indication H01L 21/338 H01L 29/78 301B 29/812 618B 9447-4M 29/80 H (72) Inventor Tsutomu Tezuka 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Within the Toshiba Research and Development Center (72) Inventor Keiko Hiraoka 1 Komukai-shiba-cho, Saiwai-ku, Kawasaki, Kanagawa Toshiba Research and Development Center ( 72) Inventor Atsushi Kurobe 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research and Development Center
Claims (3)
と、 格子定数が前記チャネル半導体層のそれと異なり、前記
チャネル半導体層に歪みを印加する歪み印加半導体層
と、 この歪み印加半導体層内に形成された絶縁層とを具備し
てなることを特徴とする半導体装置。1. A channel semiconductor layer in which a channel is induced, a strain applying semiconductor layer having a lattice constant different from that of the channel semiconductor layer and applying a strain to the channel semiconductor layer, and formed in the strain applying semiconductor layer. And an insulating layer.
歪み印加半導体層はシリコンゲルマニウム層であること
を特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the channel semiconductor layer is a silicon layer, and the strain applying semiconductor layer is a silicon germanium layer.
チャネルが誘起される半導体層であることを特徴とする
請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the channel semiconductor layer is a semiconductor layer in which a channel of a MOSFET is induced.
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| JP13503796A JP3376211B2 (en) | 1996-05-29 | 1996-05-29 | Semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device |
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