JPH09321307A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH09321307A
JPH09321307A JP13503796A JP13503796A JPH09321307A JP H09321307 A JPH09321307 A JP H09321307A JP 13503796 A JP13503796 A JP 13503796A JP 13503796 A JP13503796 A JP 13503796A JP H09321307 A JPH09321307 A JP H09321307A
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layer
sige
semiconductor layer
channel
formed
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JP3376211B2 (en
Inventor
Yoshiko Hiraoka
Kiyoshi Imai
Atsushi Kurobe
Naoharu Sugiyama
Tsutomu Tezuka
Koji Usuda
聖支 今井
佳子 平岡
勉 手塚
直治 杉山
宏治 臼田
篤 黒部
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Toshiba Corp
株式会社東芝
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Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET having a structure enabling the forming of a strained Si layer having high quality and satisfactory stain, without losing the effect of the SOI structure. SOLUTION: A buried insulation layer 3 is inserted into a strain applied SiGe semiconductor layer 2 to form an upper and lower SiGe layers. A strained Si layer 4 is formed as a channel layer on the upper SiGe layer 2 which is made thin by the insulation layer 3. Before forming the Si layer 4, the SiGe layer 2 is heat treated to reduce defects such as dislocation produced in this layer 2 at forming of both layers 2 and 3.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、MOSFETやH BACKGROUND OF THE INVENTION The present invention is, MOSFET and H
EMT等のようにチャネルが誘起されるチャネル半導体層を有する半導体素子を備えた半導体装置に関する。 A semiconductor device having a semiconductor element having a channel semiconductor layer in which a channel is induced as such EMT.

【0002】 [0002]

【従来の技術】コンピュ−タ−や通信機器の重要部分には、多数のトランジスタや抵抗等を電気回路を達成するようにむすびつけ、1チップ上に集積化して形成した大規模集積回路(LSI)が多用されている。 BACKGROUND OF THE INVENTION computer - data - the important part of and communication devices, tie a number of transistors and resistors or the like to achieve electrical circuits, large scale integrated circuits formed by integrated on one chip (LSI) There has been frequently used. このため、 For this reason,
機器全体の性能は、LSI単体の性能と大きく結び付いている。 The performance of the entire equipment is linked largely to the LSI single performance.

【0003】LSI単体の性能向上、例えば、Si系M [0003] of the LSI unit performance improvement, for example, Si-based M
OSデバイス等で構成されるLSI単体の性能向上においては、高速かつ低消費電力を特徴とするMOSFET In improving the performance of single LSI constituted by OS devices such as high speed and MOSFET which is characterized by low power consumption
の改良が不可欠である。 Improvement of it is essential. このため、例えば、電子移動度等の電気的特性の向上を目的とした研究開発が精力的に行なわれている。 Thus, for example, research and development for the purpose has been vigorously carried out to improve the electrical characteristics of the electron mobility and the like.

【0004】しかし、チャネルが誘起されるチャネル半導体層の構造についての検討は、その緒についたばかりである。 [0004] However, study of the structure of the channel semiconductor layer in which a channel is induced, is only attached to the cord. 電子移動度を高めるための技術の1つとして、 One technique for increasing the electron mobility,
チャネル半導体層に歪みをかける技術が知られている。 Technology to apply a strain in the channel semiconductor layer has been known.
チャネル半導体層に歪みをかけると、そのバンド構造が変化し、その結果、縮退が解けて電子散乱が抑制されるので、電子移動度を高めることが可能となる。 When applying a strain in the channel semiconductor layer, the band structure changes, as a result, since the degeneracy melts electron scattering is suppressed, it becomes possible to increase the electron mobility.

【0005】具体的には、シリコン基板上にシリコンよりも格子定数の大きな材料からなる混晶層、例えば、G [0005] Specifically, the mixed crystal layer made of a material having a large lattice constant than silicon on a silicon substrate, for example, G
e濃度20%のSiGe混晶層(以下、単にSiGe層という)を形成し、このSiGe層上にチャネル半導体層としてのシリコン層を形成すると、格子定数の違いにより、歪みのかかったシリコン層(以下、歪みチャネル層という)が形成される。 e concentration of 20% SiGe mixed crystal layer (hereinafter, simply referred to as SiGe layer) is formed and to form a silicon layer as a channel semiconductor layer is formed on the SiGe layer, due to the difference in lattice constant, silicon layer took distortion ( hereinafter referred to strained channel layer) is formed. このような歪みチャネル層を用いると、無歪みチャネル層を用いた場合の約1.76 The use of such a strained channel layer, about 1.76 in the case of using an unstrained channel layer
倍と大幅な電子移動度の向上を達成できることが報告されている(J.Welser,JLHoyt,S.Takagi, and JFGibb Can achieve improvement in fold and substantial electron mobility has been reported (J.Welser, JLHoyt, S.Takagi, and JFGibb
ons,IEDM 94-373 )。 ons, IEDM 94-373).

【0006】他方、電子移動度の向上のために、MOS [0006] On the other hand, in order to improve the electron mobility, MOS
FETの短チャネル化を進めると、浮遊容量の影響が大きくなるため、期待通りに電子移動度を向上することは困難になる。 Continuing with reduction of the channel length of the FET, since the influence of the stray capacitance becomes large, it becomes difficult to improve the electron mobility as expected.

【0007】そこで、SOI(Silicon On Insulator) [0007] Thus, SOI (Silicon On Insulator)
基板にMOSFETを作成することが検討されている。 It is considered to create a MOSFET on the substrate.
SOI基板の形成方法としては、張り合わせ基板等の幾つかの方法が提案されているが、SOI基板の酸化層とその上のシリコン層の各々の膜厚を最適な寸法に形成できる方法として、シリコン基板に酸素イオンを注入した後、このシリコン基板に高温熱処理を施して該基板内部に埋め込み酸化層を形成するという、通称SIMOX As a method of forming the SOI substrate is several methods, such as bonding substrates have been proposed, as a method capable of forming the optimum dimensions of each of the thickness of the oxide layer and the silicon layer thereon an SOI substrate, a silicon after implanting oxygen ions into the substrate, of forming a buried oxide layer inside the substrate is subjected to high temperature heat treatment to the silicon substrate, called SIMOX
(Separation by Implanted Oxygen)と呼ばれる方法が広く用いられている。 (Separation by Implanted Oxygen) and method called is widely used.

【0008】図3に、SOI基板に作成したMOSFE [0008] FIG. 3, MOSFE that was created on the SOI substrate
Tの断面構造を示す。 It shows a cross-sectional structure of the T. 図中、51はシリコン基板、52 In the figure, 51 is a silicon substrate, 52
は酸化層、53はシリコン層を示しており、これらはS Oxide layer, 53 denotes a silicon layer, which are S
OI基板を構成している。 Constitute the OI board.

【0009】シリコン層53上にはSiGe混晶層(以下、単にSiGe層という)54が形成され、このSi [0009] SiGe mixed crystal layer on the silicon layer 53 (hereinafter, simply referred to as SiGe layer) is 54 formed, the Si
Ge層54上には歪みシリコン層55が形成されている。 On Ge layer 54 is strained silicon layer 55 is formed. これらシリコン層53、SiGe層54および歪みシリコン層55には酸化層52に達する素子分離絶縁膜56が形成されている。 These silicon layer 53, SiGe layer 54 and the strained silicon layer 55 is an element isolation insulating film 56 to reach the oxide layer 52 is formed.

【0010】歪みシリコン層55上にはゲート酸化膜5 [0010] The gate oxide film 5 is in on the strained silicon layer 55
7、ゲート電極58が順次形成されている。 7, the gate electrode 58 are sequentially formed. また、このゲート電極58をマスクに用いたイオン注入により、歪みシリコン層55およびSiGe層54には、n型ソース領域59およびn型ドレイン領域60が自己整合に形成されている。 Furthermore, by ion implantation using the gate electrode 58 as a mask, the strained silicon layer 55 and the SiGe layer 54, n-type source region 59 and the n-type drain region 60 are formed in self-alignment.

【0011】そして、全面にはゲート電極58を覆うように層間絶縁膜61が形成され、この層間絶縁膜61に開口されたコンタクトホールを介してソース電極62、 [0011] Then, the entire surface interlayer insulating film 61 to cover the gate electrode 58 is formed on the source electrode 62 through the apertured contact hole in the interlayer insulating film 61,
ドレイン電極63がそれぞれn型ソース領域59、n型ドレイン領域60に接続している。 A drain electrode 63 is connected to the n-type source region 59, n-type drain region 60, respectively.

【0012】上述したようなチャネル半導体層に歪みシリコン層55を用い、基板にSOI基板を用いたMOS [0012] The strained silicon layer 55 with the channel semiconductor layer as described above, using an SOI substrate to substrate MOS
FETを実現できれば、0.1μmルール以下の微細化に対しても有効な素子特性が得られるようになる。 If realized FET, so effective device characteristics can be obtained for the following miniaturization 0.1μm rule. すなわち、短チャンネル効果を抑えながら電子移動度の向上が図れるようになる。 That is, as can be improved electron mobility while suppressing the short channel effect.

【0013】しかしながら、このようなMOSFETの実現に際しては以下のような問題がある。 [0013] However, in realization of such a MOSFET has the following problems. 十分な歪みを有する歪みシリコン層55を得るには、厚いSiGe混晶バッファ層(以下、単にSiGeバッファ層という) To obtain a strained silicon layer 55 having a sufficient distortion, thick SiGe mixed crystal buffer layer (hereinafter, simply referred to as SiGe buffer layer)
を形成し、その上に高Ge濃度のSiGe層54を形成する必要がある。 Forming a, it is necessary to form the SiGe layer 54 of high Ge concentration thereon. 例えば、シリコン層53に対して格子定数が%オーダで異なる厚さ100nm程度のSiGe For example, the thickness of 100nm approximately SiGe differ the% order lattice constant with respect to the silicon layer 53
バッファ層を形成する。 Forming a buffer layer.

【0014】しかし、下地のシリコン層53との格子不整合によりSiGeバッファ層内にミスフィット転位や貫通転位が発生し、これら転位がSiGe層54内に引き継がれ、さらにこれら転位がSiGe層54上に形成する歪みシリコン層55に引き継がれ、素子特性が劣化するという問題が生じる。 [0014] However, misfit dislocations and dislocations in the SiGe buffer layer is generated by the lattice mismatch between the silicon layer 53 underlying these dislocations are taken over into the SiGe layer 54, further dislocations upper SiGe layer 54 taken over strained silicon layer 55 to be formed, there is a problem that device characteristics are degraded.

【0015】仮にSiGeバッファ層の結晶成長が問題なく行なわれ、SiGeバッファ層内にミスフィット転位や貫通転位が発生しなくても、後工程における高熱の熱処理中で緩和が生じて、結果的に転位が生じる可能性もある。 [0015] which if performed without crystal growth of the SiGe buffer layer is a problem, without generating misfit dislocations and threading dislocations in the SiGe buffer layer, caused relaxation in the heat treatment of the high heat in the subsequent step, resulting in there is also a possibility that the dislocation occurs.

【0016】したがって、十分な歪みを有する歪みシリコン層55を得るには、SiGe層54がシリコン層5 [0016] Therefore, in order to obtain a strained silicon layer 55 having a sufficient distortion, silicon SiGe layer 54 is layer 5
3から受ける歪みを解放した、つまり、SiGe層54 Distortion received from 3 released, i.e., SiGe layer 54
が緩和した状態で、SiGe層54上にシリコンを成長させて歪みシリコン層55を形成することが望まれる。 There in a state of relaxed, it is desired to form a strained silicon layer 55 is grown a silicon on SiGe layer 54.

【0017】これを実現するためには、SiGeバッファ層として、シリコン層53から遠ざかるに従って徐々にGe濃度が高くなる厚い傾斜組成SiGe層を作成し、この傾斜組成SiGe層上にSiGe層54、歪みシリコン層55を順次形成することが必要となる。 [0017] In order to achieve this, the SiGe buffer layer, creating a thick graded composition SiGe layer gradually Ge concentration becomes higher as the distance from the silicon layer 53, SiGe layer 54 on the inclined composition SiGe layer, the strain it is necessary to successively form the silicon layer 55.

【0018】この厚い傾斜組成SiGe層では、貫通転位、ミスフィット転位等の転位が該層中に閉じ込められる。 [0018] In the thick graded composition SiGe layer, dislocations, dislocations such as misfit dislocation is confined in the layer. また、SiGe層54を形成する傾斜組成SiGe Also, graded composition SiGe for forming the SiGe layer 54
層の表面は十分に緩和している。 Surface of the layer is sufficiently relaxed. したがって、表面に転位がなく、かつ歪みシリコン層55からの歪みが解放されたSiGe層54が得られ、これにより転位がなく十分な歪みを有する歪みシリコン層55を形成できるようになる。 Therefore, there is no dislocation to the surface, and the SiGe layer 54 strain is released from the strained silicon layer 55 is obtained, it is possible to form a strained silicon layer 55 having a sufficient strain no dislocation thereby. しかしながら、このSiGeバッファ層の厚みは、およそ1μm程度となる。 However, the thickness of the SiGe buffer layer, is approximately 1μm about.

【0019】一方、浮遊容量の低減などのSOI基板の効果を得るためには、SOI基板のSOI層の厚み(シリコン層53の膜厚とSiGe層54の膜厚と歪みシリコン層55の膜厚の合計)は0.1μm程度以下である必要がある。 Meanwhile, in order to obtain the effect of the SOI substrate, such as a reduction in stray capacitance, the thickness of the film thickness and the strained silicon layer 55 with a thickness of the SiGe layer 54 having a thickness of an SOI layer of the SOI substrate (silicon layer 53 total) is required to be not more than about 0.1 [mu] m.

【0020】したがって、上述したような厚いSiGe [0020] Therefore, thick SiGe, such as described above
バッファ層(傾斜組成SiGe層)を形成した後に、歪みシリコン層を形成したのでは、SOI基板の効果を享受できないという問題が生じる。 After forming the buffer layer (gradient composition SiGe layer), than to form a strained silicon layer, a problem that can not enjoy the effect of the SOI substrate is produced.

【0021】さらに、上述した厚いSiGeバッファ層(傾斜組成SiGe層)を形成するには、結晶成長時間がかかるという問題がある。 Furthermore, in order to form a thick SiGe buffer layer as described above (graded composition SiGe layer), there is a problem that the crystal growth time consuming. また、表面ラフネスが増加し、その上に形成する歪みシリコン層55の膜質が低下するという問題もある。 The surface roughness is increased, the film quality of the strained silicon layer 55 formed thereon is also lowered.

【0022】 [0022]

【発明が解決しようとする課題】上述の如く、チャネル半導体層に歪みシリコン層を用い、基板にSOI基板を用いたMOSFETを実現できれば、0.1μmルール以下の微細化に対しても、短チャンネル効果を抑えながら電子移動度の向上が図れるとともに、ドレイン電流も大きく取れるようになる。 As THE INVENTION Problems to be Solved] described above, using a strained silicon layer on the channel semiconductor layer, if realized MOSFET using the SOI substrate to substrate, even for less finer 0.1μm rule, short channel while suppressing the effect with can be improved electron mobility, so that the drain current is also made large.

【0023】転位がなく十分な歪みを有する歪みシリコン層の形成方法として、SiGeバッファ層としての厚い傾斜組成SiGe層上にSiGe層を形成し、このS [0023] As a method of forming the strained silicon layer having a sufficient without distortion dislocations, the SiGe layer is formed on a thick graded composition SiGe layer on the SiGe buffer layer, the S
iGe層上にシリコンを成長させて歪みシリコン層を形成する方法が知られている。 iGe method silicon is grown to form a strained silicon layer on the layer are known.

【0024】しかし、厚い傾斜組成SiGe層を形成することにより、歪みシリコン層とSOI構造を構成する酸化層との間が大きくなり、SOI構造の効果が得られなくなるという問題があった。 [0024] However, by forming a thick graded composition SiGe layer, it becomes large between the oxide layer constituting the strained silicon layer and the SOI structure, the effect of the SOI structure there is a problem that can not be obtained.

【0025】本発明は、上記事情を考慮してなされたもので、その目的とするところは、SOI構造による効果を失わずに、高品質で十分な歪みを有するチャネル半導体層を形成できる構造を有する半導体装置を提供することにある。 The present invention has been made in view of these circumstances, it is an object without losing the effect of the SOI structure, the structure capable of forming a channel semiconductor layer with sufficient distortion high quality It is to provide a semiconductor device having.

【0026】 [0026]

【課題を解決するための手段】 In order to solve the problems]

[概要]上記目的を達成するために、本発明に係る半導体装置(請求項1)は、チャネルが誘起されるチャネル半導体層と、格子定数が前記チャネル半導体層のそれと異なり、前記チャネル半導体層に歪みを印加する歪み印加半導体層と、この歪み印加半導体層内に形成された絶縁層とを備えていることを特徴とする。 To achieve the Summary above object, a semiconductor device according to the present invention (Claim 1) includes a channel semiconductor layer where a channel is induced, differs from that lattice constant of the channel semiconductor layer, the channel semiconductor layer and the strain applied semiconductor layer to apply a distortion, characterized by comprising a distortion applied semiconductor layer which is formed on the insulating layer.

【0027】また、本発明に係る他の半導体装置(請求項2)は、上記半導体装置(請求項1)において、前記チャネル半導体層がシリコン層、前記歪み印加半導体層がシリコンゲルマニウム層であることを特徴とする。 Further, another semiconductor device according to the present invention (Claim 2), in the semiconductor device (claim 1), said channel semiconductor layer is a silicon layer, the strain applied semiconductor layer is a silicon germanium layer the features.

【0028】この場合、上記絶縁層はSIMOX法により形成することが好ましい。 [0028] In this case, the insulating layer is preferably formed by a SIMOX process. また、本発明に係る他の半導体装置(請求項3)は、上記半導体装置(請求項1) Further, another semiconductor device according to the present invention (claim 3), the semiconductor device (claim 1)
において、前記チャネル半導体層が、MOSFETのチャネルが誘起される半導体層であることを特徴とする。 In the channel semiconductor layer, characterized in that a semiconductor layer where a channel of the MOSFET is induced.

【0029】[作用]本発明の如きの構造によれば、例えば、以下のような形成方法により、SOI構造による効果を失わずに、十分な歪みを有するチャネル半導体層を形成できるようになる。 According to such a structure of [Operation] The present invention, for example, by forming the following method, without losing the effect of the SOI structure, it is possible to form a channel semiconductor layer having sufficient strain.

【0030】すなわち、まず、後工程で形成するチャネル半導体層に十分な歪みを与えることができる歪み印加半導体層を形成する。 [0030] That is, first, a strain applied semiconductor layer may provide sufficient strain in the channel semiconductor layer to be formed in a later step. これは例えば歪み印加半導体層がSiGe層の場合であればGe濃度を高くすれば良い。 This example strained applied semiconductor layer may be higher Ge concentration in the case of SiGe layer.

【0031】次に歪み印加半導体層内に絶縁層を形成する。 [0031] Next an insulating layer is formed strained applied semiconductor layer. これは例えば酸素イオンを歪み印加半導体層内に注入した後、アニール処理を行なって形成する。 After this injection of the oxygen ions in the strained applied semiconductor layer for example, formed by performing an annealing process. この結果、歪み印加半導体層は絶縁層により上下二つに分離され、上部歪み印加半導体層/絶縁層/下部歪み印加半導体層が構造できる。 As a result, the strain applied semiconductor layer is separated into two upper and lower by the insulating layer, the upper strained applied semiconductor layer / insulating layer / lower strain applied semiconductor layer can be structured.

【0032】このとき、絶縁層、上部歪み印加半導体層および後工程で形成するチャネル半導体層からなるSO [0032] At this time, SO made of an insulating layer, the channel semiconductor layer formed on top strained applied semiconductor layer and a subsequent process
I構造と同じ効果を享受できるように、絶縁層を形成する位置の深さを選ぶ。 As you can enjoy the same effects as I structure, choosing the depth position to form an insulating layer. すなわち、SOI構造による効果を享受できる程度の薄い上部歪み印加層が得られるように、歪み印加半導体層内に絶縁層を形成する。 That is, such a thin upper strain applied layer enough to enjoy the effects of SOI structure can be obtained, an insulating layer is formed strained applied semiconductor layer.

【0033】さらに、上記アニール処理により、歪み印加半導体層の形成時や絶縁層の形成時に、歪み印加半導体層内に発生した転位等の欠陥が減少する。 Furthermore, the above annealing treatment, during the formation of the formation at or insulating layer of strained applying semiconductor layers, defects such as dislocation occurring in the strain applied semiconductor layer is reduced. これにより、従来の厚い歪み印加半導体層と同程度数以下の欠陥を有する高品質な薄い歪み印加半導体層が得られる。 Thus, high-quality thin strained applied semiconductor layer having a conventional thick strained applied semiconductor layer comparable number following defects are obtained.

【0034】最後に、高品質な薄い歪み印加半導体層(上部歪み印加半導体層)上にチャネル半導体層を形成する。 [0034] Finally, to form a channel semiconductor layer on the high-quality thin strained applied semiconductor layer (upper strained applied semiconductor layer). ここで、上部歪み印加半導体層は、上述したように、高品質でチャネル半導体層に十分な歪みを与えることができるように形成されているので、高品質で十分な歪みを有するチャネル半導体層が形成されることになる。 Here, the upper strain applied semiconductor layer, as described above, is formed so as to be able to provide sufficient strain in the channel semiconductor layer with high quality, the channel semiconductor layer with sufficient distortion high quality It will be formed. しかも、チャネル半導体層に歪みを印加する上部歪み印加層は薄いので、SOI構造と同等の効果は得られる。 Moreover, since the channel semiconductor layer upper strain applied layer for applying a distortion thin, an effect equivalent to that of the SOI structure is obtained. したがって、SOI構造と同等の効果を失わずに、 Therefore, without losing the same effect as SOI structure,
高品質で十分な歪みを有するチャネル半導体層を形成できることになる。 It becomes possible to form a channel semiconductor layer having a sufficient strain with high quality.

【0035】 [0035]

【発明の実施の形態】以下、図面を参照しながら本発明の実施の形態(以下、実施形態という)を説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention with reference to the drawings (hereinafter, referred to as embodiments) will be described a. (第1の実施形態)先ず、本発明の基本的な考えについて説明する。 First Embodiment First, a description will be given of the basic idea of ​​the present invention. 図1に、本発明をSi系MOSFETに適用した場合のプロセスフローを従来法のそれと比較して示す。 1, a process flow when the present invention is applied to Si-based MOSFET in comparison with that of the conventional method. この例では歪み印加半導体層としてSiGe層を用いている。 And using SiGe layer as a distortion applied semiconductor layer in this example.

【0036】従来法では、まず、シリコン基板に酸素イオンを注入し、このシリコン基板にアニール処理を施してシリコン基板内に酸化層を形成することにより、つまり、SIMOX法によりSOI基板を形成する。 [0036] In the conventional method, first, oxygen ions are implanted into the silicon substrate, by forming the oxide layer in the silicon substrate is subjected to annealing on the silicon substrate, that is, to form an SOI substrate by the SIMOX method.

【0037】次にSiGeバッファ層としてSOI基板から離れるに従って結晶中のGe濃度を徐々に高くなる傾斜組成SiGe層をSOI基板上に形成する。 [0037] Then gradually becomes higher gradient composition SiGe layer of Ge concentration in the crystal is formed on the SOI substrate as the distance from the SOI substrate as the SiGe buffer layer. 次にS Then S
iGeバッファ層上にSiGeを成長させて所望のGe iGe in the SiGe grown on the buffer layer on a desired Ge
濃度を有するSiGe層を形成する。 Forming a SiGe layer having a concentration.

【0038】最後に、SiGe層上にシリコンを成長させて歪みシリコン層を形成した後、この歪みシリコン層をチャネル半導体層とするMOSFETを形成する。 [0038] Finally, after forming the strained silicon layer is grown silicon on SiGe layer to form a MOSFET of the strained silicon layer and the channel semiconductor layer. これに対し、本発明では、まず、シリコン基板上にSiG In contrast, in the present invention, firstly, SiG on a silicon substrate
eを成長させて歪み印加半導体層としてのSiGe層を形成する。 e is grown to form a SiGe layer as a distortion applied semiconductor layer. このとき、SiGe層のGe濃度は、後工程で形成する歪みシリコン層の歪みの大きさが十分に大きくなるように選ぶ。 In this case, Ge concentration in the SiGe layer is chosen such that the magnitude of strain of the strained silicon layer to be formed in a later process becomes sufficiently large.

【0039】次にSiGe層に酸素イオンを注入した後、このSiGe層にアニール処理を施すことにより、 [0039] Then after implanting oxygen ions into the SiGe layer, by annealing to the SiGe layer,
SiGe層内に埋め込み絶縁層を形成する。 Forming an insulating layer buried in the SiGe layer. この結果、 As a result,
SiGe層は埋め込み絶縁層により上下二つに分離される。 SiGe layer is separated into two upper and lower by the buried insulating layer. 以下、分離された上側のSiGe層を上部SiGe Hereinafter, the SiGe layer of the separated upper upper SiGe
層、下側のSiGe層を下部SiGe層という。 Layer, the lower SiGe layer of that lower SiGe layer.

【0040】この工程時に、上部SiGe層の膜厚が薄くなるように、埋め込み絶縁層をSiGe層の浅い位置に形成する。 [0040] During this step, as the thickness of the upper SiGe layer is thinner, the buried insulating layer is formed at a shallow position of the SiGe layer. これにより、埋め込み絶縁層と次の工程で形成する歪みシリコン層との間を短くできるので、埋め込み絶縁層、上部SiGe層および歪みシリコン層により構成されるSOI構造と同等の浮遊容量低減等の効果を享受できるようになる。 Thus, embedding so can be shortened between the insulating layer and the strained silicon layer formed in the next step, the buried insulating layer, the effect of the stray capacitance reduction of equivalent SOI structure composed of an upper SiGe layer and a strained silicon layer It will be able to enjoy.

【0041】さらに、SiGe層に酸素イオンを注入した後のアニール処理により、SiGe層の形成時および酸素イオン注入時に生じた転位等の欠陥を修復できるので、SiGeバッファ層を形成しなくても、高品質な上部SiGe層、下側SiGe層が得られる。 [0041] Further, by annealing after implanting oxygen ions into the SiGe layer, since defects such as dislocations generated at the time of formation and during the oxygen ion implantation SiGe layer can be repaired, even without forming a SiGe buffer layer, high-quality upper SiGe layer, the lower SiGe layer.

【0042】したがって、従来よりも少ない工程数(1 [0042] Thus, fewer steps than the conventional (1
工程短縮)で、SOI構造と同等の効果を失わずに、高品質で大きな歪みを有する歪みシリコン層を形成できる高品質で薄い上部SiGe層(歪み印加半導体層)が得られることになる。 In step shorter), without losing the same effect as SOI structure, so that the thin top SiGe layer with high quality can be formed strained silicon layer having a large distortion with a high-quality (distortion applied semiconductor layer) is obtained.

【0043】最後に、上部SiGe層上にシリコンを成長させて歪みシリコン層を形成した後、この歪みシリコン層をチャネル半導体層とするMOSFETを形成する。 [0043] Finally, after forming the strained silicon layer is grown silicon on the upper SiGe layer to form a MOSFET of the strained silicon layer and the channel semiconductor layer. なお、上部SiGe層上に新たなSiGe層を形成し、このSiGe層上に歪みシリコン層を形成した後、 Incidentally, to form a new SiGe layer on the upper SiGe layer, after forming the strained silicon layer on the SiGe layer,
この歪みシリコン層にMOSFETを形成しても良い。 It may be formed MOSFET on the strained silicon layer.
この場合、より高品質なSiGe層が得られるので、さらに素子特性の優れたMOSFETを形成できるようになる。 In this case, since the higher quality SiGe layer is obtained, so that more can be formed excellent MOSFET device characteristics.

【0044】次に本発明の具体的な実施形態について説明する。 [0044] Next will be described a specific embodiment of the present invention. 図2は、本発明の一実施形態に係るn型MOS 2, n-type MOS according to an embodiment of the present invention
FETの素子構造を示す断面図である。 It is a cross-sectional view showing the element structure of the FET. これを製造工程に従い説明すると、まず、例えば、RCA法等の洗浄法を用いて自然酸化膜等が除去された清浄なシリコン基板1を準備する。 This will be described in accordance with the manufacturing process, first, for example, a natural oxide film or the like to prepare a clean silicon substrate 1 which is removed by using the cleaning method of the RCA method.

【0045】次にシリコン基板1上に厚さ1μm程度のSiGe層2を形成する。 The turn form SiGe layer 2 having a thickness of about 1μm on the silicon substrate 1. SiGe層2のGe濃度は、 Ge concentration of the SiGe layer 2,
後工程で形成する歪みシリコン層4の歪みが十分に大きくなるように高くする。 Strain of the strained silicon layer 4 to be formed in a later step is high to be sufficiently large.

【0046】ここで、Ge濃度を急激に増加させながらSiGe層2を形成すると、シリコン基板1とSiGe [0046] Here, when forming the SiGe layer 2 while sharply increasing the Ge concentration, the silicon substrate 1 and the SiGe
層2の格子定数の違いにより生じる格子不整合によって、SiGe層2中に無用の貫通転位、あるいはミスフィット転位を含む欠陥を誘起することになるので、Ge By lattice mismatch caused by difference in lattice constant of the layer 2, it means to induce defects including threading dislocations useless in the SiGe layer 2, or misfit dislocations, Ge
濃度はSiGe層2の中で徐々に増加させ、表面で所望濃度となるようにすることが好ましい。 Concentration increases gradually in the SiGe layer 2, it is preferable to have a desired concentration at the surface.

【0047】膜厚1μmという値は、SiGe層2のデバイス側に近い部分のGe組成比を0.3と設計するときに用いる典型的な値である。 The value of thickness 1μm are typical values ​​used when the Ge composition ratio of a portion close to the device side of the SiGe layer 2 designed with 0.3. Ge組成比は大きい方が良く、0.2を大きく下回る場合には、SiGe層2上に形成するMOSFETの移動度の顕著な向上は期待できない。 Ge composition ratio may a larger, if far below 0.2, a significant improvement in the mobility of the MOSFET formed on the SiGe layer 2 can not be expected. また、0.5を大きく越える場合には、SiG Further, when greatly exceeds 0.5, SiG
e層2の表面凹凸(表面ラフネス)の増加や、膜質の低下等の問題が生じる可能性がある。 Increase and surface irregularities of the e layer 2 (surface roughness), problems may arise such as degradation of film quality. これらの点を考慮してGe組成比を設定すれば、本発明の効果はより顕著に発揮されるようになる。 By setting the Ge composition ratio in consideration of these points, so that the effect of the present invention are more remarkably exhibited.

【0048】SiGe層2の具体的な成膜方法は以下の通りである。 [0048] Specific method for forming the SiGe layer 2 is as follows. すなわち、原料としてSiH 4およびGe In other words, SiH 4 and Ge as a raw material
4を用い、成長温度を500℃に設定し、成長圧力を10 -3 Paに設定して、真空容器中でCVD法により形成する。 Using H 4, setting the growth temperature to 500 ° C., by setting the growth pressure to 10 -3 Pa, formed by a CVD method in a vacuum chamber.

【0049】SiGeを成長させるには、このようなC [0049] In order to grow the SiGe, such C
VD法や、MBE(Molecular BeamEpitaxy)法等のエピタキシャル成長法が広く用いられるが、Ge組成比の制御が可能な結晶成長方法であれば、他の成膜法を用いても良い。 VD method and, although MBE (Molecular BeamEpitaxy) Epitaxial growth method or the like is widely used, as long as the crystal growth method capable of controlling the Ge composition ratio may be any other film forming method.

【0050】例えば、LPE(Liquid Phase Epitaxy) [0050] For example, LPE (Liquid Phase Epitaxy)
法等の液相成長法や、ポリSiGe層あるいはアモルファスSiGe層の加熱による固相成長法でもSiGe層2を形成できる。 Liquid phase growth method or the like method, to form a SiGe layer 2 in the solid phase growth method by heating the poly SiGe layer or an amorphous SiGe layer.

【0051】また、ここでは、真空下(成長圧力10 -3 [0051] In addition, here, under vacuum (growth pressure of 10 -3
Pa)でのCVD法の場合について説明したが、数百T Has been described for the case of CVD method at Pa), several hundred T
orrの成長圧力による減圧あるいは常圧、加圧下でも成長が可能である。 Reduced pressure or normal pressure by a growth pressure of orr, even under pressure are possible growth.

【0052】Si原料としてはSiH 4 、Si 26 [0052] SiH 4, Si 2 H 6 as the Si raw material,
Si 24 Cl 2等、Ge原料としてはGeH 4 、Ge Si 2 H 4 Cl 2, etc., as the Ge raw material GeH 4, Ge
4 、Ge 28等が適している。 F 4, Ge 2 H 8 and the like are suitable. これら原料のガスはキャリアガスを用いて真空容器内に導入しても良い。 These raw material gases may be introduced into the vacuum chamber using a carrier gas. キャリアガスとしては、例えば、水素ガス、窒素ガス、ヘリウムガスまたはアルゴン等の不活性ガス等があげられる。 As the carrier gas, e.g., hydrogen gas, nitrogen gas, inert gas such as helium gas or argon and the like.

【0053】また、原料を予めプラズマ、光等により分解して、成長に必要なエネルギーを有する成長に寄与する種を生成し、これを結晶成長に利用しても良い。 [0053] Further, the raw material in advance plasma, is decomposed by light or the like, to produce the contributing species to the growth with the energy required for growth, which may be used in crystal growth. また、SiGe層2を形成する際に、B、As、P等の不純物源となるB 26 、AsH 3 、PH 3等を原料と同時に真空容器内に導入して、SiGe層2が所定の導電型になるようにしても良いし、あるいはSiGe層2を形成した後にB、As、P等を拡散によりSiGe層2 Further, when forming the SiGe layer 2, B, As, and B 2 H 6 as a source of impurities such as P, the AsH 3, PH 3 or the like is introduced at the same time the vacuum vessel as a raw material, SiGe layer 2 is given of may be made such that the conductivity type, or B after forming the SiGe layer 2, as, SiGe layer by diffusing P, etc. 2
内に導入して、SiGe層2が所定の導電型になるようにしても良い。 Is introduced within, SiGe layer 2 may be a predetermined conductivity type. また、B、As、P以外にGa、Sb、 Also, B, As, besides P Ga, Sb,
Sn、Al、N等を用いても良い。 Sn, Al, may be used N, and the like.

【0054】次にドーズ量5×10 17 cm -2の条件で酸素イオンをSiGe層2の上から注入した後、1300 [0054] Then after the oxygen ions were injected from the top of the SiGe layer 2 at a dose of 5 × 10 17 cm -2, 1300
℃のアニール処理を施して、良好な埋め込み絶縁層3をSiGe層2内に形成する。 ℃ subjected to annealing treatment, to form a satisfactory buried insulating layer 3 in the SiGe layer 2.

【0055】SiGe層2は埋め込み絶縁層3により上下二つに分離される。 [0055] SiGe layer 2 is separated into two upper and lower by the buried insulating layer 3. 以下、分離された上側のSiGe Hereinafter, the separated upper SiGe
層2を上部SiGe層2、下側のSiGe層2を下部S The layers 2 upper SiGe layer 2, the lower S a SiGe layer 2 of the lower
iGe層2という。 That iGe layer 2.

【0056】この工程時に、上部SiGe層2の膜厚が薄くなるように、埋め込み絶縁層3をSiGe層2の浅い位置に形成する。 [0056] During this step, as the thickness of the upper SiGe layer 2 becomes thinner, a buried insulating layer 3 is formed at a shallow position of the SiGe layer 2. また、上記アニール処理でSiGe Further, SiGe above annealing treatment
層2内の転位等の欠陥が修復され、高品質なSiGe層2が形成される。 Repaired defects such as dislocations, in layer 2, high-quality SiGe layer 2 is formed.

【0057】したがって、埋め込み絶縁層3上には、歪み印加半導体層として、高品質で薄い上部SiGe層2 [0057] Thus, on the buried insulating layer 3, as a distortion applied semiconductor layer, a thin upper SiGe layer with high quality 2
が形成されることになる。 So that but is formed. 次に成長温度を500℃に設定してCVD法により上部SiGe層2上にシリコンを成長させて厚さ30nmの歪みシリコン層4を形成する。 Then the silicon is grown on the upper SiGe layer 2 by by setting the growth temperature to 500 ° C. CVD method to form a strained silicon layer 4 having a thickness of 30nm to. この歪みシリコン層4の歪みは引っ張り歪みである。 Distortion of the strained silicon layer 4 is a tensile strain.

【0058】上部SiGe層2のGe濃度は高いので、 [0058] Since the Ge concentration of the upper SiGe layer 2 is high,
歪みシリコン層4は、電子移動度の向上を図るのに十分な大きさの引っ張り歪みを有したものとなる。 Strained silicon layer 4 becomes one having a tensile strain large enough to improve the electron mobility. さらに、 further,
上部SiGe層2内の転位等の欠陥は低減されているので、高品質な歪みシリコン層4が形成される。 Since defects such as dislocations in the upper SiGe layer 2 is reduced, high-quality strained silicon layer 4 is formed.

【0059】さらまた、本実施形態では、埋め込み絶縁層3、上部SiGe層2および歪みシリコン層4によりSOI構造(SiGe On Insulator 構造)が形成されているが、上部SiGe層2の膜厚は薄いので、上記SOI [0059] Further also, in the present embodiment, the buried insulating layer 3, but the upper SiGe layer 2 and the strained silicon layer 4 SOI structure (SiGe On Insulator structure) is formed, the thickness of the upper SiGe layer 2 is thinner since, the SOI
構造による浮遊容量低減等の効果は十分に発揮される。 Effects such as stray capacitance reduction by the structure is sufficiently exerted.

【0060】したがって、本実施形態によれば、上記S [0060] Therefore, according to this embodiment, the S
OI構造の利点およびチャネル層として歪みシリコン層を用いた利点を有するMOSFETを実現できるようになる。 It becomes possible to realize a MOSFET having the advantages of using a strained silicon layer as an advantage and the channel layer of the OI structure.

【0061】また、MOSFETの短チャネル効果の抑制または駆動電流の向上、あるいはこれらを同時に効果的に図るためには、歪みシリコン層4の膜厚は20nm [0061] Moreover, improvement of the suppression or the driving current of the short-channel effect of MOSFET, or in order to achieve them simultaneously effective, the film thickness of the strained silicon layer 4 is 20nm
以下であることが望ましい。 Less it is desirable.

【0062】次にトレンチ分離法により素子分離絶縁膜5を形成する。 [0062] Next, forming an element isolation insulating film 5 by a trench isolation method. なお、トレンチ分離法の代わりにLOC It should be noted that, LOC in place of the trench isolation method
OS分離法等の他の素子分離法を用いても良い。 Other isolation methods such as OS separation method may be used. この素子分離絶縁膜5により、n型MOSFETの形成予定領域と、これに隣り合う別のデバイス、例えば、p型MO The element isolation insulating film 5, and the formation region of the n-type MOSFET, another device adjacent thereto, for example, p-type MO
SFETの形成予定領域とが分離される。 A formation region of the SFET are separated.

【0063】次に歪みシリコン層4の表面を熱酸化してできるだけ薄いゲート酸化膜6を形成する。 [0063] Then the surface of the strained silicon layer 4 to form a gate oxide film 6 as thin as possible by thermal oxidation. ゲート酸化膜6の膜厚は10nm程度以下であることが望ましい。 The thickness of the gate oxide film 6 is preferably not more than about 10 nm.
次にしきい値電圧調整用の不純物イオンをゲート酸化膜6を介してチャネル領域に注入し、n型チャネル領域を形成する。 Next, impurity ions for adjusting the threshold voltage injected into the channel region through the gate oxide film 6, to form an n-type channel region.

【0064】次にゲート酸化膜6上にゲート電極7となる多結晶シリコン膜を減圧CVD法により形成した後、 [0064] Next, a polycrystalline silicon film serving as the gate electrode 7 on the gate oxide film 6 was formed by low pressure CVD,
上記多結晶シリコン膜を反応性イオンエッチング(RI The polycrystalline silicon film by reactive ion etching (RI
E)等の異方性エッチングによりパターニングして、ゲート電極7を形成する。 It is patterned by anisotropic etching of E) or the like to form a gate electrode 7. このとき、ゲート酸化膜6も同様にパターニングし、ゲート電極7下以外のゲート酸化膜6を除去する。 At this time, the gate oxide film 6 is similarly patterned to remove the gate oxide film 6 other than below the gate electrode 7.

【0065】次にゲート電極7をマスクにして、n型M [0065] Next, the gate electrode 7 as a mask, n-type M
OSFET形成領域にリンイオン等のn型不純物イオンを選択的に注入した後、800℃程度のアニール処理を施して、n型ソース領域8、n型ドレイン領域9を自己整合的に形成する。 After selectively implanting n-type impurity ions such as phosphorus ions OSFET forming region is subjected to an annealing treatment at about 800 ° C., to form an n-type source region 8, n-type drain region 9 in a self-aligned manner.

【0066】次に全面にシリコン酸化膜またはシリコン窒化膜などの層間絶縁膜10をCVD法により形成した後、この層間絶縁膜10にゲート領域、ソース領域、ドレイン領域に対するコンタクトホールを開口する。 [0066] Then after forming by CVD an interlayer insulating film 10 such as a silicon oxide film or a silicon nitride film on the entire surface, contact holes in the interlayer insulating film 10 a gate region, a source region, for the drain region.

【0067】最後に、全面にAl膜等の導電膜を堆積した後、この導電膜をパターニングして、ソース電極1 [0067] Finally, after depositing a conductive film of Al film or the like on the entire surface, patterning the conductive film, the source electrode 1
1、ドレイン電極12、ゲート引き出し電極(不図示) 1, the drain electrode 12, the gate lead-out electrode (not shown)
を形成して、n型MOSFETが完成する。 To form, n-type MOSFET is completed.

【0068】以上述べたように本実施形態によれば、S [0068] According to the present embodiment as described above, S
OI構造による効果およびチャネル層として歪みシリコン層を用いた効果を同時に得られるMOSFETを実現できるようになる。 Effect so can be realized with MOSFET simultaneously obtained using a strained silicon layer as an effect and the channel layer by OI structure. これにより、微細化を進めても期待通りの素子特性を有するMOSFETの実現が可能となる。 Thus, it is possible to realize the MOSFET having device characteristics expected even miniaturized.

【0069】なお、本発明は上述した実施形態に限定されるものではない。 [0069] The present invention is not limited to the embodiments described above. 例えば、上記実施形態では、歪み印加半導体層として、SiGe層を用いた場合について説明したが、SiGe層の代わりに、SiCやSiN等のようにSiと他の元素との混晶層、ZnSe層等の II- For example, in the above embodiment, as the strain applied semiconductor layer, has been described using SiGe layer, instead of the SiGe layer, the mixed crystal layer of Si and other elements as such SiC or SiN, ZnSe layer etc. II-
VI族混晶層もしくはGaAsやInP等の III-V族混晶層などの互いに格子定数の異なる材料からなる混晶層でも良い。 Group VI mixed crystal layer or may be a mixed crystal layer of different materials from each other lattice constants, such as group III-V mixed crystal layer, such as GaAs or InP.

【0070】また、上記実施形態では、MOSFETの場合について説明したが、本発明はチャネル半導体層に歪みを印加することが可能な構造の半導体素子を有する半導体装置であれば適用できる。 [0070] In the above embodiment, the description has been given of the MOSFET, the present invention can be applied to any semiconductor device having a semiconductor device having a structure capable of applying a strain in the channel semiconductor layer.

【0071】例えば、MOS構造を有するCMOSやB [0071] eg, CMOS and B having a MOS structure
iCMOS等の半導体素子や、HEMT(High Elector Semiconductor devices such as iCMOS and, HEMT (High Elector
on Mobility Transistor)を有する半導体装置にも適用できる。 on Mobility Transistor) it can be applied to a semiconductor device having a. その他、本発明の要旨を逸脱しない範囲で、種々変形して実施できる。 Other, without departing from the scope of the present invention can be variously modified.

【0072】 [0072]

【発明の効果】以上詳述したように本発明によれば、S According to the present invention as described in detail above, S
OI構造による効果を失わずに、高品質で十分な歪みを有するチャネル半導体層を形成できる構造の半導体装置を提供できるようになる。 Without losing the effect of the OI structure, it is possible to provide a semiconductor device having a structure capable of forming a channel semiconductor layer having a sufficient strain with high quality.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明をSi系MOSFETに適用した場合のプロセスフローを従来法のそれと比較して示す図 Shows compared to that of the present invention; FIG conventional method process flow when applied to Si-based MOSFET the

【図2】本発明の一実施形態に係るn型MOSFETの素子構造を示す断面図 Sectional view showing an n type MOSFET according to an embodiment of the present invention; FIG

【図3】従来のSOI基板を用いたn型MOSFETの素子構造を示す断面図 3 is a cross-sectional view showing an n-type MOSFET using the conventional SOI substrate

【符号の説明】 DESCRIPTION OF SYMBOLS

1…シリコン基板 2…SiGe層(歪み印加半導体層) 3…埋め込み絶縁層 4…歪みシリコン層(チャネル半導体層) 5…素子分離絶縁膜 6…ゲート酸化膜 7…ゲート電極 8…n型ソース領域 9…n型ドレイン領域 10…層間絶縁膜 11…ソース電極 12…ドレイン電極 1 ... silicon substrate 2 ... SiGe layer (strained applied semiconductor layer) 3 ... buried insulating layer 4 ... strained silicon layer (channel semiconductor layer) 5 ... isolation insulating film 6 ... gate oxide film 7 ... gate electrode 8 ... n-type source region 9 ... n-type drain region 10 ... interlayer insulation film 11 ... source electrode 12 ... drain electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 6識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/338 H01L 29/78 301B 29/812 618B 9447−4M 29/80 H (72)発明者 手塚 勉 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 平岡 佳子 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 黒部 篤 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 ────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. in Docket No. FI art display portion 6 identifications Agency H01L 21/338 H01L 29/78 301B 29/812 618B 9447-4M 29/80 H (72) inventor Tsutomu Tezuka Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho, address 1 Co., Ltd. Toshiba research and development in the Center (72) inventor Keiko Hiraoka Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho, address 1 Co., Ltd. Toshiba research and development within the Center ( 72) inventor Kurobe Atsushi Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho, address 1 Co., Ltd., Toshiba research and development Center in

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】チャネルが誘起されるチャネル半導体層と、 格子定数が前記チャネル半導体層のそれと異なり、前記チャネル半導体層に歪みを印加する歪み印加半導体層と、 この歪み印加半導体層内に形成された絶縁層とを具備してなることを特徴とする半導体装置。 And 1. A channel semiconductor layer where a channel is induced, differs from that lattice constant of the channel semiconductor layer, and the strain applied semiconductor layer for applying a distortion to the channel semiconductor layer, formed on the strained applied semiconductor layer wherein a formed by including an insulating layer.
  2. 【請求項2】前記チャネル半導体層はシリコン層、前記歪み印加半導体層はシリコンゲルマニウム層であることを特徴とする請求項1に記載の半導体装置。 2. A semiconductor device according to claim 1, wherein the channel semiconductor layer is a silicon layer, the strain applied semiconductor layer is a silicon germanium layer.
  3. 【請求項3】前記チャネル半導体層は、MOSFETのチャネルが誘起される半導体層であることを特徴とする請求項1に記載の半導体装置。 Wherein the channel semiconductor layer, the semiconductor device according to claim 1, wherein the channel of the MOSFET is a semiconductor layer induced.
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