JP3372158B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Recently, attempts have been made to utilize a heterostructure of silicon and germanium in order to increase the speed of a silicon MOSFET. For example, in order to increase the speed of NMOSFETs, a strained silicon germanium buffer layer is formed on a silicon substrate, over which a strained silicon layer is formed, and this strained silicon layer is used as a channel. The method of doing is proposed. It is known that this tensile-strained silicon layer has a higher electron mobility than bulk silicon, and thus can speed up the MOSFET (IEDM Tech.Digest, 1994, p3 73).
-376). However, in order to obtain a tensile-strained silicon layer using this technique, it is necessary to form the silicon germanium buffer layer as thick as about 2 μm in order to bring it into a lattice relaxation state. In the MOSFET manufactured using such a thick film, the parasitic capacitance between the source and drain increases, and as a result, it becomes difficult to increase the speed.

As a method for solving this problem, SOI (silicon on in) having a thin silicon layer (SOI layer) on the surface is used.
A technique for forming a lattice-relaxed silicon-germanium buffer layer on a substrate is proposed (Appl. Phys. Lett, 64 (14), p1856-1858, 1994).
In this method, after forming a laminated structure of SiGe layer / SOI layer / SiO2 layer, low temperature heat treatment at about 700 ° C is performed to generate dislocations only in the SOI layer, so that the SiGe layer is lattice-relaxed without dislocations. be able to. At this time, SiGe
In order to fully relax the layer, the thickness of the SOI layer should be set to SiGe.
It should be thinner than the layers. After this, by forming a thin Si layer of about 50 nm on the SiGe layer by using the epitaxial method, the tensile strain state on the thin SiGe layer of about several hundred nm
A Si layer can be formed.

Here, the epitaxial process of the Si layer and the SiGe layer is described in “Low tmperature” of BS Meyerson et al.
silicon epitaxy by UHV / CVD ”Appl.Phys.Lett, vol4
8, p797-799, 1986 and “Cooperative growth phenomena.
in silicon / germanium low-temperature epitaxy ”Ap
pl. Phys. Lett, vol53, p2555-2557, 1988.

On the other hand, in order to increase the speed of PMOSFET, Si
A method is known in which a compressively strained SiGe layer is formed on a substrate and is used as a channel. This compressive strain state
Since the SiGe layer has higher hole mobility than bulk Si, it is possible to speed up the PMOSFET (IEEE E
LECTRON DEVICE LETTERS, VOL15, NO.10,1994, P402-40
Five). Here, in order to form a compressively strained SiGe layer, the film thickness of the SiGe layer must be below the critical film thickness determined by the composition ratio of Ge and the growth temperature (J.Appl.Phys, vol7
0, No. 4, 1991, P2136-2151).

[0006]

[Problems to be Solved by the Invention] High integration and low power consumption
In order to manufacture LSI, NMOSFET and PMOSFET must be combined to form an integrated transistor.
However, the above-mentioned NMOS using the tensile strained Si layer
It is difficult to integrate them on the same substrate because the required strain state of the SiGe layer differs between the FET and the PMOSFET that uses the compressively strained SiGe layer.

The present invention has been made in view of the above problems, and its purpose is to achieve high speed and high performance by forming a tensile strained Si layer and a compressive strained SiGe layer on the same substrate with good compatibility. To provide a highly integrated transistor.

[0008]

In order to solve the above problems, the present invention (claim 1) provides a silicon substrate, an insulating layer formed on the silicon substrate, and a silicon formed on the insulating layer. Layer, a lattice-relaxed silicon germanium layer formed on the silicon layer, a tensile strained silicon layer formed on the silicon germanium layer, and a source formed in the tensile strained silicon layer A region, a channel region, a drain region, a gate region formed on the channel region, a compression-strained silicon germanium layer formed directly on the surface of the silicon substrate on which the insulating layer is not formed, and A source region, a channel region, and a drain region formed in a compressively strained silicon germanium layer, and a region formed on the channel region. That it comprises a gates region to provide a semiconductor device according to claim.

Further, according to the present invention (claim 2), the silicon germanium layer in the lattice relaxation state and the silicon germanium layer in the compressive strain state are formed at the same time. I will provide a.

According to a third aspect of the present invention, a silicon substrate, an insulating layer formed on the silicon substrate, a first region silicon layer formed on the insulating layer, and the insulating layer are provided. A silicon layer in a second region which is formed on the silicon layer in the first region and has a thickness larger than that of the silicon layer in the first region; and a silicon germanium layer in a lattice relaxation state formed on the silicon layer in the first region, A tensile strained silicon layer formed on the silicon germanium layer, a source region, a channel region, and a drain region formed in the tensile strained silicon layer, and a gate region formed on the channel region, A compressively strained silicon germanium layer formed on the silicon layer in the second region;
There is provided a semiconductor device including a source region, a channel region, and a drain region formed in the silicon germanium layer in the compressive strain state, and a gate region formed on the channel region.

According to the present invention (claim 4), the channel region formed in the tensile-strained silicon layer is mainly used as an electron flow region, and the channel region formed in the compression-strained silicon germanium is used. 3. A semiconductor device according to claim 1, 2 or 3, wherein is mainly a region through which holes flow.

According to the present invention (claim 5), a substrate having a silicon layer formed on a silicon substrate via an insulating layer is prepared, and the silicon layer and a part of the insulating layer are opened to form a silicon substrate. By the step of exposing the surface and the epitaxial process, a silicon germanium layer in a lattice relaxation state is formed on the silicon layer on the insulating layer, and a silicon germanium layer in a compression strain state is formed on the exposed surface of the silicon substrate at the same time. And a step of forming the semiconductor device.

Further, according to the present invention (claim 6), a step of forming an amorphous silicon layer on the entire surface of a silicon substrate having an insulating layer partially opened on the surface and heat treatment of the opened insulating layer are performed. A step of crystallizing the amorphous silicon from the exposed portion of the silicon substrate surface, and a lattice-relaxed silicon germanium layer on the crystallized silicon layer formed on the insulating layer by an epitaxial process, And a step of simultaneously forming a compressively strained silicon germanium layer on a crystallized silicon substrate formed in an opening of an insulating layer.

According to the present invention (claim 7), the insulating layer of the silicon substrate is present by an epitaxial process and a step of partially forming an insulating layer inside the silicon substrate by ion implantation and subsequent heat treatment. And a step of simultaneously forming a lattice-relaxed silicon germanium layer on the region and a compression-strained silicon germanium layer on the region of the silicon substrate where the insulating layer does not exist. A manufacturing method is provided.

Further, according to the present invention (claim 8), a tensile strained silicon layer is formed on the lattice-relaxed silicon germanium layer by an epitaxial process. A method for manufacturing a semiconductor device is provided.

[0016]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIGS. 1 to 9 are sectional views showing respective steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. First, as shown in Fig. 1, the surface has a thickness of 5n.
Si layer (SOI layer) 2 of about m and insulating layer of about 100 nm thick
A silicon substrate 1 having 3 is prepared. SOI layer 2 here
Can be thinned to a desired thickness by repeating the step of thermally oxidizing this and the step of subsequently etching this thermal oxide film. Here, the film thickness of the SOI layer is preferably an appropriate thickness, that is, a range of 4 nm to 150 nm, which is sufficiently thin so that the SiGe layer 4 laminated thereon has a lattice relaxation state.

Next, as shown in FIG. 2, this silicon substrate
The opening 20 is formed by selectively etching the SOI layer 2 and the insulating layer 3 of 1 to expose the single crystal surface of the silicon substrate 1.

Next, as shown in FIG. 3, this silicon substrate
After cleaning 1 by, for example, the RCA method, a Si0.7Ge0.3 layer 4 with a thickness of about 30 nm was formed at a growth temperature of 500 ° C by an epitaxial process, and then heat-treated at 1000 ° C for about 1 hour in a crystal growth furnace. , Si0.7Ge0.3 layer 4 on insulating layer 3 was lattice-relaxed. At this time, in order to bring the Si0.7Ge0.3 layer 4 formed on the opening into a compressive strain state, it is necessary to make the film thickness below the critical film thickness determined by the Ge composition ratio and the growth temperature. Here, the Ge percentage of the SiGe layer 4 is preferably in the range of 20 to 50%. This is because if the Ge percentage is less than 20%, the mobility cannot be expected to increase in the tensile-strained Si layer 5 laminated thereon. On the other hand, when it is more than 50%, the film quality and morphology of the SiGe layer 4 are deteriorated, and improvement in electrical characteristics cannot be expected. The film thickness of the SiGe layer 4 corresponds to a Ge percentage of 20 to 50% when the growth temperature is set to about 500 ° C.
The range of 40 to 300 nm is preferred. This is because it is difficult to bring the SiGe layer 4 formed in the opening 20 into a compressive strain state when it is larger than the above range.

Next, by the same epitaxial process as above, at a growth temperature of 500 ° C., a 30 nm thick Si film was formed on the Si0.7Ge0.3 layer 4.
Layer 5 was formed. As a result, lattice-relaxed Si0.7Ge0.3 layer
A tensile-strained Si layer 5 is formed on the surface 4. After that, P-type and N-type well regions (not shown) are formed on the substrate.

Next, as shown in FIG. 4, an element isolation region 6 is formed by a LOCOS isolation method or a trench isolation method,
The NMOSFET formation planned region and the PMOSFET formation planned region are separated from each other.

Next, as shown in FIG. 5, a resist is applied, exposed and developed to form a resist pattern 7 in the region where the NMOSFET is to be formed. This resist pattern 7
Using the mask as a mask, the Si layer 5 on the surface of the PMOSFET formation planned area is exposed to normal CDE (chemical dry etching) or RIE
(Reactive ion etching) is used to reduce the thickness to about 5 nm. This step is necessary in order to suppress the short channel effect of the MOSFET and improve the drive current by subsequently thermally oxidizing the Si layer 5 to form a gate oxide film as thin as possible. For that purpose, it is desirable that the thickness of the Si layer 5 be 5 nm or less.

Next, as shown in FIG. 6, a resist pattern
After removing 7, the entire surface is thermally oxidized to form a gate oxide film 8 having a thickness of about 10 nm. At this time, it is desirable that the thermal oxide film on the PMOSFET formation region side is formed without thermal oxidation to the Si0.7Ge0.3 layer 4 in the compression strain state. Generally, when a SiGe layer is thermally oxidized to form a gate insulating film,
This is because the interface state density becomes high, which causes an increase in leak current during device operation. After that, ion implantation for threshold adjustment is performed on the channel layer through the gate oxide film to form an N channel region (not shown) and a P channel region (not shown).

Next, as shown in FIG. 7, after forming a polycrystalline silicon layer on the gate oxide film by a low pressure CVD method, this polycrystalline silicon layer is processed by RIE to form a gate electrode 9
To form. At this time, the gate oxide film 8 is simultaneously formed by RIE.
Is also patterned at the same time.

Next, as shown in FIG. 8, phosphorus is selectively ion-implanted into the NMOSFET formation region using the gate electrode 9 as a mask to form an N-type source region 10 and an N-type drain region 11, and a PMOSFET is formed. Boron is selectively ion-implanted into the region to be formed so that the P-type source region 12 and the P-type drain region 13 are formed.
To form. After that, impurities are activated by heat treatment at about 800 ° C.

Next, as shown in FIG. 9, an interlayer insulating film 14 such as a silicon oxide film is formed on the entire surface by the CVD method, and then contact holes for each MOSFET region are opened in this interlayer insulating film 14. Finally, after depositing a conductive film such as an Al film on the entire surface, this conductive film is patterned to form the source electrode 1.
5, drain electrode 16, gate extraction electrode (not shown),
The source electrode 17 and the drain electrode 18 are formed to complete the integrated transistor.

According to the present embodiment, an NMOSFET using a tensile strained Si layer in the channel region and a PMOSFET using a compressive strained SiGe layer in the channel region can be formed on the same substrate. The characteristics of the layers can be sufficiently brought out, and high speed and high performance of the integrated transistor can be achieved.

In addition, since the SOI structure is used for the substrate in the present embodiment, the parasitic capacitance of the device can be greatly reduced by utilizing its features, and as a result, the high speed and high performance of the integrated transistor can be promoted. can do. Further, in this example, the SOI layer and the insulating film layer were selectively etched with the same width before forming the SiGe layer, but even if the SOI layer is selectively etched so as to remain only under the NMOSFET channel formation region, it is possible to perform the selective etching. The invention can be achieved.

(Embodiment 2) FIGS. 10 to 12 are sectional views showing respective steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

The parts corresponding to those of the semiconductor device according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The main difference between the semiconductor device of this example and that of Example 1 is that the SOI structure is formed by a solid phase epitaxial process.

First, as shown in FIG. 10, an insulating film 3 is formed on the surface.
A part of the Si substrate 1 having is opened by selective etching. Next, as shown in FIG. 11, an amorphous Si film 2 having a thickness of about 20 nm is formed on the entire surface of the substrate by the CVD method. After that, when this substrate is heat-treated at about 600 ° C. in an N 2 atmosphere using, for example, an electric furnace, the amorphous Si layer 2 is crystallized from the opening, whereby the SOI structure can be formed. For the subsequent steps, those shown in Example 1 can be used similarly. FIG. 12 shows the structure of the integrated transistor of this embodiment.

(Embodiment 3) FIGS. 13 to 15 are sectional views in each step showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

The parts corresponding to those of the semiconductor device according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The main difference between the semiconductor device of the present embodiment and that of the first embodiment is that the thickness of the SOI layer in each of the NMOSFET and PMOSFET formation planned regions is controlled by using selective etching.
The point is that the lattice-relaxed SiGe layer and the compressively strained SiGe layer are formed on the same substrate.

First, as shown in FIG. 13, the surface has a thickness of 500 n.
Si layer (SOI layer) 2 of about m and insulating layer of about 100 nm thick
A silicon substrate 1 having 3 is prepared. Next, as shown in FIG. 14, the Si layer 2 on the surface of the silicon substrate 1 is selectively etched to a region of about 5 nm on the side where the NMOSFE is to be formed, and the PMOSFET
Thin the area to be formed to about 100 nm. Thinning methods include RIE, CDE, thermal oxidation and repeated wet etching processes.

After cleaning such a substrate by, for example, the RCA method, a growth temperature of 500 is obtained by an epitaxial process.
A Si0.7Ge0.3 layer 4 of about 30 nm and a Si layer of about 30 nm are continuously grown at ℃. As a result, a tensile strained Si layer can be formed on the NMOSFET formation planned region side, and a compressive strained Si0.7Ge0.3 layer can be formed on the PMOSFET formation planned region side. Here, in order to put the Si0.7Ge0.3 layer on the side of the PMOSFET formation region into the compressive strain state, the film thickness must be below the critical film thickness determined by the Ge composition ratio and the growth temperature. Subsequent steps may be performed in the same manner as the manufacturing steps shown in the first embodiment. FIG. 15 is a sectional view of the integrated transistor according to this example.

(Embodiment 4) FIGS. 16 to 17 are sectional views showing respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIG. 18 is a plan view of this semiconductor device as seen from above. The parts corresponding to those of the semiconductor device according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device of this example is different from that of Example 1 mainly in that the SOI substrate is formed by oxygen ion implantation and a subsequent heat treatment process.

First, as shown in FIG. 16, the surface of the Si substrate 1 is oxidized to form an oxide film having a thickness of about 1 μm, and the oxide film is patterned by a normal photoetching method to form a PMOSFET. Oxide film pattern 19 in the area to be formed
To form.

Next, as shown in FIG. 17, oxide film pattern
Oxygen is ion-implanted using 19 as a mask to form a high concentration layer 3 of oxygen in the Si substrate 1. The conditions for ion implantation are
Implant energy 180 KeV, Implant amount 4E17cm ^-2 , Substrate temperature 600
℃ was made.

Next, after removing the oxide film pattern, the sample substrate is heat-treated at 1350 ° C. for about 4 hours in a mixed gas atmosphere of argon and oxygen using, for example, an electric furnace to form a buried oxide film layer 3 and Retained crystallinity on its surface
The SOI layer 3 is formed.

For the subsequent steps, those shown in Example 1 can be used in the same manner. FIG. 18 shows the structure of the integrated transistor of this embodiment. FIG. 19 is a plan view of this integrated transistor. In the figure, since there is no buried oxide film layer 3 below the channel region (hatched portion) of the PMOSFET, the SiGe layer 4 formed in this region is subjected to compressive strain. Here, in order to put the SiGe layer 4 into a compressive strain state,
The film thickness must be below the critical film thickness determined by the Ge composition ratio and the growth temperature. In addition, although oxygen was used as an element for ion implantation when manufacturing an SOI substrate in this example, the present invention can also be achieved when nitrogen is used as an element.

(Embodiment 5) FIGS. 20 to 23 are sectional views in each step showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. The sectional view of the semiconductor device of this embodiment is the same as FIG. The parts corresponding to those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The main difference between the semiconductor device of this embodiment and that of the first embodiment is that the SOI structure is formed by a selective epitaxial process and a solid phase epitaxial process. First, as shown in FIG. 20, an insulating film 3 is provided on the surface.
Prepare Si substrate 1.

Next, as shown in FIG. 21, the insulating film 3 is partially opened by selective etching. Next, as shown in FIG. 22, a single crystal Si film 21 is formed in the opening by a selective epitaxial process.

Next, as shown in FIG. 23, the entire substrate surface is
An amorphous Si film 2 having a thickness of about 20 nm is formed by the CVD method.
The thickness of the amorphous Si film 2 is Si0.
It is made thinner than the film thickness of 7Ge0.3 layer 4. Next, this substrate is subjected to a heat treatment at about 600 ° C. in an N2 atmosphere using, for example, an electric furnace, and the single crystal Si film 21 in the opening is used as a seed portion for the amorphous Si film.
An SOI structure can be produced by crystallizing 2. Then, according to the manufacturing process shown in the first embodiment, a similar integrated transistor can be manufactured. Various modifications are possible without departing from the scope of the present invention.

[0045]

As described above, according to the present invention, an NMOSFET using a tensile strained Si layer and a compressive strained Si layer on the same substrate.
Since the PMOSFET using the Ge layer can be formed with good matching, it is possible to realize a high-speed, high-performance integrated transistor in which the characteristics of these two strained layers are sufficiently extracted.

[Brief description of drawings]

FIG. 1 is a sectional view of each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view of each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view of each step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a sectional view of each step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 13 is a sectional view of each step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 14 is a sectional view of each step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a sectional view of each step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 17 is a sectional view of each step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 18 is a sectional view of a semiconductor device according to fourth and fifth embodiments of the present invention.

FIG. 19 is a top view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 20 is a sectional view of each step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 21 is a sectional view of each step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 22 is a sectional view of each step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 23 is a sectional view of each step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

[Explanation of symbols]

1 ... Silicon substrate; 2 ... SOI layer; 3 ... Insulating layer; 4 ... Silicon germanium layer; 5 ... Silicon layer; 6 ... Element isolation layer; 7 ... Resist pattern; 8 ... Gate oxide film; 9 ... Gate electrode; N-type source region substrate; 11 ... N-type drain region; 12 ... P-type source region; 13 ... P-type drain region; 14 ... Interlayer insulating film; 15 ... Source electrode; 16 ... Drain electrode; 17 ... Source electrode; 18 ... Drain electrode

Front page continuation (72) Inventor Tsutomu Tezuka 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center Co., Ltd. (72) Inventor Keiko Hiraoka Komukai-shi Toshiba-cho, Kawasaki-shi, Kanagawa 1-share Company Toshiba Research & Development Center (72) Inventor Atsushi Kurobe 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Toshiba Research & Development Center (56) Reference JP-A-60-52052 (JP, A) JP Flat 3-187269 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336 H01L 21/092 H01L 27/08 H01L 27/092 H01L 21/8238

Claims (9)

(57) [Claims] 1. A silicon substrate, an insulating layer formed on the silicon substrate, a silicon layer formed on the insulating layer, a lattice-relaxed silicon germanium layer formed on the silicon layer, A tensile-strained silicon layer formed on the silicon-germanium layer; a source region, a channel region, and a drain region formed in the tensile-strained silicon layer; and a gate region formed on the channel region. , wherein the insulating layer of the silicon substrate is formed in direct contact with the surface that has not been formed, and has the insulating layer is formed
The part located on the non-surface is in a compressive strain state.The silicon germanium layer and the insulating layer of the silicon germanium layer are formed.
A channel formed in an area located on an open surface
Region, the silicon germanium layer sandwiching this channel region
The semiconductor device according to claim source region formed in arm layer, and the drain region, that includes a gate region formed on said channel region. 2. The lattice-relaxed silicon germanium layer and the insulating layer of the silicon substrate are not formed.
2. The semiconductor device according to claim 1, wherein a silicon germanium layer formed directly in contact with the other surface is formed at the same time. 3. Formed in the tensile strained silicon layer.
The formed channel region is mainly used as an electron flow region.
On the surface of the silicon substrate where the insulating layer is not formed
Formed in silicon germanium formed by direct contact
The open channel region is mainly used as a hole flow region.
The semiconductor device according to claim 1, wherein: 4. A silicon substrate, an insulating layer formed on the silicon substrate, a first region silicon layer formed on the insulating layer, and a first region formed on the insulating layer. A silicon layer in a second region thicker than the silicon layer in the first region, a silicon germanium layer in a lattice relaxation state formed on the silicon layer in the first region, and a tension formed on the silicon germanium layer. A strained silicon layer, a source region, a channel region, and a drain region formed in the tensile strained silicon layer, a gate region formed on the channel region, and a silicon layer in the second region. And a source region, a channel region, and a drain formed in the compressively strained silicon germanium layer Semiconductor device characterized by comprising a band, and the formed gate region to the channel region. 5. A channel region formed mainly in the tensile-strained silicon layer is used as an electron flow region, and a channel region formed mainly in the compressive-strained silicon germanium is mainly used as hole flow regions. The semiconductor device according to claim 4 , wherein: 6. A step of preparing a substrate in which a silicon layer is formed on a silicon substrate via an insulating layer, exposing a surface of the silicon substrate by opening a part of the silicon layer and the insulating layer, and epitaxially. A step of simultaneously forming a lattice-relaxed silicon germanium layer on the silicon layer on the insulating layer and a compressive strained silicon germanium layer on the exposed surface of the silicon substrate by a process. A method for manufacturing a semiconductor device, comprising: 7. A step of forming an amorphous silicon layer on the entire surface of a silicon substrate having a partially opened insulating layer on the surface thereof, and a heat treatment exposing the silicon substrate surface of the opened insulating layer. A step of crystallizing the amorphous silicon from a portion, and a lattice-relaxed silicon germanium layer on the crystallized silicon layer formed on the insulating layer and an opening portion of the insulating layer by an epitaxial process. And a step of simultaneously forming a compressively strained silicon germanium layer on the crystallized silicon layer . 8. By ion implantation and subsequent heat treatment,
By the process of partially forming an insulating layer inside the silicon substrate and the epitaxial process, the lattice-relaxed silicon germanium layer is formed on the region where the insulating layer of the silicon substrate exists, and the insulating layer of the silicon substrate exists. And a step of simultaneously forming a compression-strained silicon germanium layer on a region not to be formed. 9. A tensile-strained silicon layer is formed on the lattice-relaxed silicon-germanium layer by an epitaxial process .
7. The method for manufacturing a semiconductor device according to 7 or 8 .