KR100697141B1 - A semiconductor device and manufacturing method thereof - Google Patents

Abstract

 An object of the present invention is to provide a fully depleted SOI field effect transistor in which transistors having different threshold voltages are integrated. A high Ge composition SiGe film and a low Ge composition SiGe film are formed on the insulating film, and a strained Si film is formed thereon, respectively. As a result, transistors having different channel voltages can be integrated by forming transistors each having a channel region in the resulting strained Si film.

 Field Effect Transistors, Full Depletion, Lattice Mitigation, Flush Isolation, Strain

Description

 Semiconductor device and manufacturing method therefor {A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a cross sectional view of each semiconductor fabrication process of the first embodiment of the invention.

Fig. 3 is a cross sectional view of the semiconductor device of the first embodiment of the present invention in each manufacturing step;

4 is a cross-sectional view of each semiconductor fabrication process of a second embodiment of the present invention.

Fig. 5 is a sectional view of each semiconductor process of the semiconductor device according to the second embodiment of the present invention.

6 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention.

Fig. 7 is a band diagram of a channel region in the MOSFET of the semiconductor device according to the third embodiment of the present invention.

Fig. 8 is a band diagram of a channel region in a pMOSFET of a semiconductor device according to the first embodiment of the present invention.

9 is a cross-sectional view of each semiconductor manufacturing process of the third embodiment of the present invention.

Fig. 10 is a cross sectional view of the semiconductor device of the third embodiment of the present invention in each manufacturing step;

11 is a sectional view of a semiconductor device according to a modification of the present invention.

<Explanation of symbols for main parts of drawing>

1: silicon substrate

2: buried insulation film

3, 30: lattice relaxed SiGe film

4, 40: strain Si film

5, 50: channel area

6, 60: gate insulating film

7, 70: gate electrode

8, 80: source area

9, 90: drain region

100: n-type field effect transistor

101: p-type field effect transistor

110: voltage V _SS

111: boot voltage applying device

112: power supply voltage

The present invention relates to a semiconductor device and a method of manufacturing the same.

In recent years, the power consumption of large-scale integrated circuits (LSIs) is on the rise due to the higher integration density of transistors and higher operating frequencies. Already in high-end processors, power consumption is over 100W.

In order to suppress the power consumption of such LSI, it is effective to lower the power supply voltage of each transistor.

On the other hand, in addition to lowering the power supply voltage, in order to improve the driving capability of the transistor, the threshold voltage of each transistor must be set lower. However, when the threshold voltage of the transistor is set low, an inconsistency arises in that the off current increases and standby power consumption increases.

This contradiction is expected to become remarkable when the generation after the gate length of the transistor is 100 nm or less, that is, when the power supply voltage is 1V and the threshold voltage is 0.3V or less.

As a method of solving the problem of increasing standby power, a method of integrating two types of transistors, a transistor having a high threshold voltage and a low transistor, on one LSI chip has been proposed. In one method, transistors with low threshold voltage and fine high-speed operation but high off-current transistors are used in the main CMOS logic circuit. In the other method, transistors with high threshold voltage and excellent blocking characteristics are used. It is used to cut off the leakage current at the time of OFF.

In addition, even in an LSI in which an analog CMOS circuit and a digital CMOS circuit are integrated on one chip, it is necessary to integrate transistors having different threshold voltages. This is because the transistor size and power supply voltage are different in the digital part and the analog part.

As such, there is a need to integrate transistors having different threshold voltages on the LSI chip. For this reason, in the conventional bulk silicon, transistors having different threshold voltages are integrated by changing the impurity concentration of the wells. This is because in bulk silicon, since the potential of the substrate is grounded and fixed, the difference between the metal work function used for the gate electrode and the potential of the semiconductor can be changed by changing the impurity concentration of the well, thereby controlling the threshold voltage. .

On the other hand, as the transistors are further miniaturized and highly integrated, many field effect transistors using SOI substrates capable of greatly reducing the junction capacitance are used. Among field effect transistors using SOI substrates, fully depleted field effect transistors in which the depletion layer reaches the buried insulating layer of the SOI substrate during operation can suppress the short channel effect even when the gate length is 100 nm or less, and the transistor operates. It is attracting attention as possible.

However, a fully depleted field effect transistor has a problem in the following points. Since it completely depletes on the buried insulating film of the SOI substrate, the body cannot be grounded and the threshold value cannot be controlled by changing the impurity concentration. This is because, since the body is not grounded, the difference between the metal work function used for the gate electrode and the potential of the semiconductor cannot be changed well and control is difficult even if impurities are changed.

On the other hand, there has been a need to integrate a plurality of field effect transistors having different threshold voltages by controlling the threshold voltages as described above.

As described above, there is a problem in that a fully depleted field effect transistor capable of significantly reducing the junction capacitance cannot be integrated by controlling different threshold voltages.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of integrating transistors having different threshold voltages into one LSI chip and a method of manufacturing the same.

The first embodiment provides the first lattice relaxation Si _{1 - x} Ge _x formed in the first region on the insulating film. (0 ≦ x <1) film and a second lattice relaxed SiGe film formed in the second region on the insulating layer having a higher Ge composition than the first lattice relaxed Si _{1- x} Ge _x (0 ≦ x <1) film. And a first strained Si film formed on the first lattice relaxed Si _{1- x} Ge _x (0 ≦ x <1) film, a second strained Si film formed on the second lattice relaxed SiGe film, and the first A first depletion type first field effect transistor having a strained Si film as a channel, and a second depletion type field effect transistor having a second strained Si film as a channel, wherein the first field effect transistor and the second electric field are provided. There is provided a semiconductor device characterized by a different threshold voltage from the effect transistor.

A second aspect includes a substrate, an insulating film formed on the substrate, a first lattice relaxed Si _{1- x} Ge _x (0 ≦ x <1) film formed in a first region on the insulating film, and the first lattice relaxed Si A first strained Si film formed on a _1-x Ge _x (0 ≦ x <1) film, a first gate insulating film formed on the first strained Si film, and a first gate electrode formed on the first gate insulating film And a first field effect transistor formed in the first strained Si film and spaced apart from each other, the first field effect transistor including a first source region and a first drain region disposed such that a channel region is located therebetween, and a second region on the insulating film. A second lattice relaxed SiGe film formed, a second strained Si film formed on the second lattice relaxed SiGe film, a second gate insulating film formed on the second strained Si film, and a second formed on the second gate insulating film It is formed in the 2nd gate electrode and the said 2nd strained Si film, and spaced apart, And a second field effect transistor including a second source region and a second drain region disposed so that the channel region is located, wherein the first field effect transistor and the second field effect transistor have different threshold voltages. A semiconductor device is provided.

That is, the first lattice relaxed film constituting the first field effect transistor may be a Si film, and Ge may be included in the Si _{1- x} Ge _x (0 ≦ x <1) range in the Si film.

In the case where the second field effect transistor is composed of a plurality of field effect transistors such as, for example, a complementary field effect transistor circuit, some of the plurality or the plurality of field effect transistors may be used in the first field effect transistor. It may be configured to have a threshold voltage different from.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention.

<First Embodiment>

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. This semiconductor device constitutes a complementary field effect transistor using a transistor having a p-channel region and a transistor having an n-channel region in a strained Si film, and the leakage blocking electric field having a high threshold voltage in the complementary field effect transistor. The effect transistor is connected. In addition, in the following description, the term corresponding to the component of this invention is shown in parentheses.

In this semiconductor device, a buried insulating film 2 made of silicon oxide is formed on a silicon substrate 1 having a (001) plane on its main surface. On the buried insulating film 2, an n-type field effect transistor (second field effect transistor: 100) having a low threshold voltage and a p-type field effect transistor (second field effect transistor: 101) having a low threshold voltage are formed, and these are formed. Complementary transistor is formed by. The high speed logic section A is formed by this complementary transistor.

Similarly, an n-type field effect transistor (first field effect transistor) 102 having a higher threshold voltage than the n-type field effect transistor 100 is formed on the buried insulating film 2. The drain region (first drain region: 9) of the n-type field effect transistor 102 is connected to the source region (second source region: 80) of the n-type field effect transistor 100, and is connected to the wiring. . The voltage V _SS 110 is applied to this wiring. This n-type field effect transistor 102 functions as a leakage cutoff switch portion B which is turned off so that no leakage current flows while the high speed logic portion A is in the standby state. In FIG. 1, the source region (first source region) 8 of the transistor 102 is grounded, and the power source voltage V _DD 112 is applied to the drain region (second drain region 91) of the transistor 101. The gate electrode (first gate electrode) 7 of the leakage blocking transistor 102 is connected to the boost wiring and is connected to the boost voltage V _Boost applying device 111.

The leakage blocking transistor 102 includes a lattice relaxed Si _0.84 Ge _0.16 film (first lattice relaxed SiGe film 3) formed on the buried insulating film 2 and a strained Si film formed on the lattice relaxed SiGe film 3. (first variant Si layer: 4) and the strained Si film 4, a gate insulating film made of SiO ₂ formed on the (first gate insulating film: 6), and a gate made of a tungsten is formed on the gate insulating film 6 It is formed to be spaced apart from the electrode (first gate electrode 7), the channel region (first channel region 5) formed in the strained Si film 4 under the gate insulating film 6, and the strained Si film 4, It consists of a source region (first source region: 8) and a drain region (first drain region: 9) provided with the channel region 5 positioned therebetween.

In addition, one constituting the complementary field effect transistors n-type field effect transistor 100 includes a buried dielectric film (2) Si _{0 .6} a lattice relaxation formed on the Ge _{0 .4} film (second lattice relaxed SiGe film: 30) And a gate insulating film (second gate insulating film: 60) formed of a strained Si film (second strained Si film) 40 formed on the lattice relaxed SiGe film 30 and SiO ₂ formed on the strained Si film 40. ), A gate electrode (second gate electrode) 70 made of tungsten formed on the gate insulating film 60, and a channel region (second channel region: formed in the strained Si film 40 under the gate insulating film 60). 50 and a source region (second source region: 80) and a drain region (second drain region: 90) formed so as to be spaced apart from each other in the strained Si film 40, and having the channel region 50 positioned therebetween. It consists of.

In addition, the other p-type field effect transistor 101 constituting the complementary field effect transistor is a Si _{0 .6} lattice relaxation formed on a buried insulating film (2) Ge _{0 .4} film (second lattice relaxed SiGe film: 31 ), A strained Si film (second strained Si film 41) formed on the lattice relaxed SiGe film 31, and a gate insulating film (second gate insulating film :) formed of SiO ₂ formed on the strained Si film 41. 61, a gate electrode (second gate electrode) 71 made of tungsten formed on the gate insulating film 61, and a channel region (second channel region) formed in the strained Si film 41 under the gate insulating film 61. : 51 and a source region (second source region: 81) and a drain region (second drain region: 91) formed so as to be spaced apart from each other in the strained Si film 41, and having a channel region 51 positioned therebetween. )

These transistors have a so-called SOI structure.

The voltage applied to each wire is 0≤V _SS ≤V _DD <V _Boost . The film thickness of the thick lattice relaxed SiGe film 3 is 50 nm, and the film thickness of the thin lattice relaxed SiGe films 30 and 31 is 10 nm. The film thickness of the strained Si films 4, 40, and 41 is 5 nm. N-type impurities are diffused in the source regions 8 and 80 and the drain regions 9 and 90 of the leakage blocking transistor 102 and the n-type field effect transistor 100. The diffusion range is not only the strained Si films 4 and 40 but also the lattice relaxed SiGe films 3 and 30. In addition, p-type impurities are diffused into the source region 81 and the drain region 91 of the p-type field effect transistor 101 constituting the CMOS. The diffusion range is not only the strained Si film 41 but also the lattice relaxed SiGe film 31.

In this semiconductor device, the Ge concentration in the lattice relaxed SiGe film 3 under the leakage blocking transistor 102 is Ge of the lattice relaxed SiGe films 30 and 31 under the transistors 100 and 101 forming the CMOS. It is getting smaller than the concentration. Therefore, the strained Si film 4 constituting the channel region 5 has a smaller deformation amount than the strained Si films 40 and 41 constituting the channel regions 50 and 51. In this case, the threshold voltage of the leakage blocking transistor 102 is higher than that of the CMOS transistors 100 and 101. At this time, the Ge composition x of the lattice relaxed SiGe film 3 can be arbitrarily selected under conditions lower than the Ge composition y of the lattice relaxed SiGe films 30 and 31.

The energy of the base level of the conduction band of the n-type MOSFET having the strained Si film as the channel region changes as ΔEc = -0.5x with respect to the Ge composition x of the underlying Si _{1 - x} Ge _x (0 ≦ x ≦ 1) film. do. Therefore, in order to change the threshold current of the ideal S parameter (S = 60 mA / decade) by one digit, it is necessary to change the minimum x by 0.12 or more. In order to obtain the smallest x single-digit threshold current change, the transistor 102 in FIG. 1 is made of a typical SOI-MOSFET of only a Si film whose composition ratio of Ge composition in the region B is 0 atomic%, that is, in the region B When the composition ratio of the Ge composition of the substantial portion of the SiGe film 3 is 0 atomic%, the composition ratio of the Ge composition of the lattice relaxation SiGe films 30 and 31 of the region A is at least equivalent to the SiGe film 3 of the region B. Although it is good to be higher than 0 atomic% of the composition ratio of the Ge composition of a part, Preferably, the Ge composition of the lattice relaxation SiGe film | membrane 30 and 31 of the area | region A should be made high by 12 atomic% or more difference.

Moreover, the range of the difference between the composition ratio of the Ge composition of the lattice relaxation SiGe films 30 and 31 of the region A and the composition ratio of the Ge composition of the region B is more preferable than the composition ratio of the Ge composition of the region B. Is high and is more than 25 atomic percent. This is because the larger the Ge composition, the higher the mobility of electrons or holes in the strained Si film, and the driving force increases. If the electron is a carrier, the compositional ratio of Ge is 15 atomic%, and if the hole is a carrier, the compositional ratio of Ge is about 25 atomic%, so that the mobility increase is saturated. This is because the maximum mobility can be obtained in both the p-channel and the n-channel when the atomic ratio of the Ge composition of B is 25 atomic percent or more higher than the atomic percent.

Fig. 8 is a band diagram of the channel portion of the MOSFET in the CMOS of this embodiment.

As shown in Fig. 8, in the modified Si-MOSFET, when the Ge composition of the underlying SiGe increases, phi ms and Eg-phi ms decrease, so that the absolute values of the threshold voltages of the p and n channel pMOSFETs and nMOSFETs decrease. Here, Eg is a band gap of strain Si, phi ms is a difference between the work function of the gate electrode and the electron affinity of strain Si. However, the dependence of the threshold voltage on the Ge composition (or strain amount of strained Si) of the underlying SiGe film is larger in the n-channel nMOSFET than in the p-channel pMOSFET.

Next, a modification to the present embodiment will be described. First, in addition to tungsten, a laminated structure of a high melting point metal such as molybdenum and tantalum, polysilicon or polysilicon germanium, or silicides thereof (TiSi ₂ , CoSi ₂ , NiSi) can be used for the gate electrode. In addition, in consideration of good operation as a CMOS, the absolute value of the threshold voltage of the p-channel pMOSFET and the n-channel nMOSFET may be provided. Therefore, the composition of the SiGe film of the underlying layer may be different in the p-channel and n-channel MOSFETs. Preferably, the Ge composition of the SiGe under the p-channel pMOSFET is set higher than the Ge composition of the SiGe under the n-channel nMOSFET.

Thus, even in a fully depleted field effect transistor, transistors 100 and 101 having a low threshold voltage and fine high-speed operation but having a large off current are used in the main CMOS logic circuit portion A, and the threshold voltage is high on one side and a blocking characteristic. This excellent transistor 102 can be used as a leakage blocking transistor.

Next, the manufacturing method of the semiconductor device shown in FIG. 1 is demonstrated using FIG. 2 and FIG.

First, as shown in FIG. 2A, the inclined composition SiGe layer 10 is formed on the silicon substrate 1 whose main surface is (100). As this film formation method, epitaxial growth by CVD method or MBE method can be used. The gradient composition Si _{1 - x} Ge _x layer 10 adjusts the flow rate of the Ge source gas to gradually change the Ge composition x from 0 to 0.1 from the surface of the silicon substrate 1. Then, as to form a Si _{0 .9 0 .1} Ge layer 11 on the SiGe gradient composition layer 10.

Next, move the substrate in the ion implanter from the film-forming device, and implanting oxygen ions from a surface of the Si _{0 .9} Ge _{0 .1} layer 11. At this time, the ion implantation energy was 160 keV and the dose was 4 × 10 ¹⁷ cm ^-2 . When the substrate is heat treated at 1350 ° C. for 6 hours, a buried insulating film 2 having a thickness of 100 nm and a SiGe layer 12 having a thickness of 300 nm are formed as shown in Fig. 2B. By the heat treatment step, the buried insulating film 2 becomes SiO ₂ , and Ge atoms in the gradient composition SiGe layer 10 shown in FIG. 2A diffuse into the Si substrate 1. In addition, the SiGe layer 12 is lattice relaxed by this heat treatment.

Next, after the lattice relaxed SiGe layer 12 is thinned to 80 nm by chemical dry etching, a part of the substrate is protected by a mask and a part of the lattice relaxed SiGe layer 12 is thinned again by chemical dry etching. . Thus, as shown in Fig. 2C, a thick lattice relaxed SiGe film (thickness: 80 nm) and a thin lattice relaxed SiGe film (thickness: 50 nm) are formed. The thick lattice relaxed SiGe film 13 and the thin lattice relaxed SiGe film 14 are separated by a photolithography process. By these processes, the first SiGe film 13 and the second SiGe film 14 having different thicknesses are formed on the insulating film 2.

Next, the substrate is subjected to dry thermal oxidation at 1100 ° C. By the oxidation process of claim 1 SiGe layer 13 and the SiGe film 2 (14) by being oxidized from the surface, the SiO ₂ film 15 is formed on the surface. Then, the Si atoms in the first SiGe film 13 and the second SiGe film 14 are used for bonding with oxygen atoms, whereas the Ge atoms come out of the oxide film. These Ge atoms are accumulated in the remaining portions of the first SiGe film 13 and the second SiGe film 14.

On the other hand, in the buried insulating film 2, in order to prevent the Ge atoms from diffusing into the silicon substrate 1, the oxidation progresses and the Ge composition in the first SiGe film 13 and the second SiGe film 14 increases. . In addition, the interface between the buried insulating film 2, the first SiGe film 13 and the second SiGe film 14 becomes weak at high temperatures of 1000 ° C or higher. Therefore, the deformation caused by the change of the lattice constant due to the increase of the Ge composition is not newly introduced into the first SiGe film 13 and the second SiGe film, and the lattice relaxation state is maintained.

In this manner, as shown in FIG. 3A, a first lattice relaxed SiGe film 3 and a second lattice relaxed SiGe film 30 having different Ge compositions are formed on the insulating film 2.

In this embodiment, the first SiGe film 13 and the second SiGe film 14 (FIG. 2C) are lattice relaxed at the same time when the buried insulating film 2 is formed by the SIMOX process. Alternatively, an SOI substrate may be purchased in advance, and the first SiGe film 13 and the second SiGe film 14 (c) of FIG. 2 (c) having different film thicknesses may be epitaxially grown on the SOI substrate. In this case, the first SiGe film 13 and the second SiGe film 14 (FIG. 2C) are in a deformed state, and the lattice simultaneously with the oxidation process for different Ge composition shown in FIG. The lattice relaxed SiGe film 3 and the second lattice relaxed film 30 can be formed.

At this time, if the thickness of the SiGe film before oxidation is T1 and the thickness of the SiGe film after oxidation is T2, the Ge composition after oxidation is T1 / T2 times before oxidation. Therefore, the Ge composition before oxidation is x (0 ≦ x ≦ 1), the thickness of the thick SiGe film 3 is Ti, the thickness of the thin SiGe film 30 is Ti-Δ (difference Δ), and the thickness consumed by oxidation. When both the Tc and the Ge composition after oxidation of the thick SiGe film 3 and the thin SiGe film 30 are xa (0 ≦ xa ≦ 1) and xb (0 ≦ xb ≦ 1), respectively, xa = x {Ti / ( Ti-Tc)} and xb = x {(Ti-Δ) / (Ti-Δ-Tc)}.

Then, since xb / xa = {1- (Δ / Ti)} / [1- {Δ / (Ti-Tc)}]> 1, the Ge composition of the thin SiGe film 30 is thick SiGe film 3. Greater than

In this embodiment, a lattice relaxed SiGe film having a different Ge composition was formed on the buried insulating film based on the above principle. In the present embodiment, specifically, the thickness of the thick SiGe film 3 is set to 80 nm to 50 nm, and the thickness of the thin SiGe film 30 is made thin by oxidation from 40 nm to 10 nm. As a result, a lattice relaxed SiGe film 3 having a Ge composition of 16 atomic% and a thin one having a Ge composition of 40 atomic% having a Ge composition is formed.

Next, as shown in Fig. 3B, the oxide film 15 formed in Fig. 3A is peeled off with hydrofluoric acid, and the strained Si films 4 and 40 are lattice relaxed SiGe films, respectively, by CVD or the like. Epitaxial growth on (3, 30). By doing so, different strains are applied to the strained Si films 4 and 40 according to the lattice constants of the first lattice relaxed SiGe film 3 and the second lattice relaxed SiGe film 30 which are the respective base films.

Next, as shown in FIG. 3C, gate insulating films 6 and 60 are formed on the strained Si films 4 and 40, and gate electrodes 7 and 70 are formed on the gate insulating films 6 and 60. ). Thus, the transistor is formed by the normal CMOS forming process and the wiring is formed. In this manner, the semiconductor device shown in FIG. 1 can be formed. In FIG. 3C, the same parts as in FIG. 1 are designated by the same reference numerals, and description thereof is omitted.

<2nd Example>

Next, the manufacturing method of another semiconductor device is demonstrated using FIG. 4 and FIG. 5 with respect to the semiconductor device shown in FIG.

First, as shown in FIG. 4A, the inclined composition SiGe layer 10 is formed on the silicon substrate 1 whose main surface is (100). As this film formation method, epitaxial growth by CVD method or MBE method can be used. The gradient composition Si _{1 - x} Ge _x layer 10 adjusts the flow rate of the Ge source gas so as to gradually change the Ge composition x from 0 to 0.1 from the surface of the silicon substrate 1. Then, as to form a Si _{0 .9} Ge _{0 .1} layer 11 on the SiGe gradient composition layer 10.

Next, move the substrate in the ion implanter from the film-forming device, and implanting oxygen ions from a surface of the Si _{0 .9} Ge _{0 .1} layer 11. At this time, the ion implantation energy was 160 keV and the dose was 4 × 10 ¹⁷ cm ^-2 . When the substrate is heat-treated at 1350 ° C. for 6 hours, a buried oxide film 2 having a thickness of 100 nm and a SiGe layer 12 having a thickness of 300 nm are formed as shown in Fig. 4B. By this heat treatment step, the buried oxide film 2 becomes SiO ₂ , and the SiGe layer 12 is lattice relaxed.

Next, after the lattice relaxation SiGe layer 12 is thinned to 80 nm by chemical dry etching, as shown in FIG. 4C, a mask 16 having openings is formed of Si ₃ N ₄ on the substrate. ). The SiGe film 17 region in which the mask 16 is formed is separated from the SiGe film 18 region in which the mask 16 is not exposed and exposed to the opening.

Next, the substrate is subjected to dry thermal oxidation at 1100 ° C. By this oxidation process, the SiGe film 18 exposed to the opening portion is oxidized from the surface to form a thin film, thereby increasing the Ge composition. In this way, as shown in Fig. 5A, the first SiGe film 3 positioned under the mask and the second SiGe film 30 positioned in the opening are formed simultaneously with different Ge compositions. The Ge composition of the thick 1st SiGe film 3 at this time was 0.1 and 80 nm in thickness, and the Ge composition of the thin 2nd SiGe film 30 was 0.4 and 20 nm in thickness.

By this oxidation process, the SiGe film [18: FIG. 4 (c)] is oxidized from the surface to form an SiO ₂ film [15: FIG. 5 (a)] on the surface. Then, the Si atoms in the SiGe film [18: FIG. 4 (c)] are used for bonding with oxygen atoms, while Ge atoms are released from the oxide film. This Ge atom is accumulated in the remaining portion of the SiGe film [18: FIG. 4 (c)].

On the other hand, in the buried insulating film 2, in order to prevent the Ge atoms from diffusing into the silicon substrate 1, oxidation progresses and the Ge composition in the SiGe film 18 (Fig. 4 (c)) increases. In addition, the interface between the buried insulating film 2 and the SiGe film 18 becomes weak at high temperatures of 1000 ° C or higher. Therefore, the deformation due to the change in the lattice constant due to the increase in the Ge composition is not newly introduced into the SiGe film 18 and the lattice relaxed state is maintained.

In this manner, as shown in FIG. 5A, a first lattice relaxed SiGe film 3 and a second lattice relaxed SiGe film 30 having different Ge compositions are formed on the insulating film 2.

In this embodiment, the SiGe film 17 and the SiGe film 18 (FIG. 4C) are lattice relaxed at the same time when the buried insulating film 2 is formed by the SIMOX process. On the other hand, an SOI substrate may be purchased in advance, and the SiGe film 17 and the SiGe film [18: FIG. 4 (c)] may be epitaxially grown on the SOI substrate. In this case, the SiGe film 17 and the SiGe film 18 (FIG. 4C) are deformed and lattice relaxed at the same time as the oxidation process for varying the Ge composition shown in FIG. 5A. The first lattice relaxed SiGe film 3 and the second lattice relaxed film 30 can be formed.

Thus, in this oxidation process, a mask is formed on one SiGe film and not oxidized, so that a lattice relaxed SiGe film having a different Ge concentration after oxidation can be formed on the substrate.

Next, as shown in FIG. 5B, the oxide film 15 and the mask 16 formed in FIG. 5A are peeled off with hydrofluoric acid, and the strained Si films 4 and 40 are removed by CVD or the like. Epitaxial growth is carried out on the lattice relaxed SiGe films 3 and 30, respectively. By doing so, different strains are applied to the strained Si films 4 and 40 according to the lattice constants of the lattice relaxed SiGe films 3 and 30, which are respective base films.

Next, as shown in FIG. 5C, gate insulating films 6 and 60 are formed on the strained Si films 4 and 40, and gate electrodes 7 and 70 are formed on the gate insulating films 6 and 60. ). Thus, the transistor is formed by the normal CMOS forming process and the wiring is formed. In this manner, the semiconductor device shown in FIG. 1 can be formed. In FIG. 5C, the same parts as in FIG. 1 are designated by the same reference numerals, and description thereof is omitted.

<Third Embodiment>

6 is a cross-sectional view of a semiconductor device according to a third exemplary embodiment of the present invention. This semiconductor device forms a complementary field effect transistor using a transistor formed with a p-channel region in a strained SiGe film and a transistor formed with an n-channel region in a strained Si film, and has a high threshold voltage for the complementary field effect transistor. A leakage effect field effect transistor is connected.

A buried insulating film 2 made of silicon oxide is formed on a silicon substrate 1 having a (001) plane on its main surface. On the buried insulating film 2, an n-type field effect transistor (second field effect transistor) 103 having a low threshold voltage and a p-type field effect transistor (third field effect transistor: 104) having a low threshold voltage are formed and complementary to each other. It constitutes a type transistor. The high speed logic portion A is formed by these transistors.

Similarly, on the buried insulating film 2, an n-type field effect transistor (first field effect transistor) 102 having a threshold voltage higher than that of the n-type field effect transistor 103 is formed. The drain region (first drain region: 9) of the n-type field effect transistor 102 is connected to the source region (third source region: 83) of the p-type field effect transistor 104, and is connected to the wiring. The voltage V _SS 110 is applied to this wiring. This n-type field effect transistor 102 functions as a leakage cutoff switch section B which is turned off so that no leakage current flows while the complementary transistor of the high speed logic section A is turned off. In FIG. 6, the source region (first source region 8) of the transistor 102 is grounded, and the power supply voltage V _DD 112 is applied to the drain region (second drain region 92) of the transistor 103. The gate electrode (first gate electrode 7) of the leakage blocking transistor 102 is connected to the boost wiring and is connected to the boost voltage V _Boost applying device 111.

The leakage blocking transistor 102 includes a lattice relaxed Si _0.84 Ge _0.16 film (first lattice relaxed SiGe film 3) formed on the buried insulating film 2 and a strained Si film formed on the lattice relaxed SiGe film 3. (first variant Si layer: 4) and the strained Si film 4, a gate insulating film made of SiO ₂ formed on the (first gate insulating film: 6), and a gate made of a tungsten is formed on the gate insulating film 6 It is formed to be spaced apart from the electrode (first gate electrode 7), the channel region (first channel region 5) formed in the strained Si film 4 under the gate insulating film 6, and the strained Si film 4, It consists of a source region (first source region: 8) and a drain region (first drain region: 9) provided with the channel region 5 positioned therebetween.

Further, n-type field effect transistor 103 of the one constituting the complementary field effect transistor is a Si _{0 .6} lattice relaxation formed on a buried insulating film (2) Ge _{0 .4} film (second lattice relaxed SiGe film: 32 ) And a gate insulating film (second gate insulating film) composed of a strained Si film (second strained Si film) 42 formed on the lattice relaxed SiGe film 32 and SiO ₂ formed on the strained Si film 42. 62, a gate electrode (second gate electrode) 72 made of tungsten formed on the gate insulating film 62, and a channel region (second channel region) formed in the strained Si film 42 under the gate insulating film 62. : 52 and a source region (second source region: 82) and a drain region (second drain region: 92) which are formed apart from each other in the strained Si film 42 and provided with the channel region 52 therebetween. )

In addition, other p-type field effect transistor 104 constituting the complementary field effect transistor formed on a strain Si film 33 and the Si film 33 formed on the buried insulating film (2) Si _{0 .8} Ge _{0 .2} film 43 and the deformation Si Ge _{0 0 .8 .2} gate insulating film made of a Si film and gaepmak 19 is formed on the (43), such as SiO ₂ formed on the Si gaepmak 19 ( Third gate insulating film 63, a gate electrode (third gate electrode 73) made of tungsten or the like formed on the gate insulating film 63, and a channel formed in the strained SiGe film 43 under the gate insulating film 63. A source region (third source region: 83) and a drain region formed between the region (third channel region 53) and the strained SiGe film 43, and disposed so as to position the channel region 53 therebetween; Third drain region 93 is formed.

As a modification of the p-type field effect transistor, a structure in which the modified SiGe film 53 as shown in the transistor 105 of Fig. 11A is in direct contact with the gate insulating film 63 can be used.

In addition, a structure in which the modified SiGe film 53 as shown in the transistor 106 of FIG. 11B is directly inserted into the gate insulating film 63 and the buried oxide film 2 is also possible.

In Fig. 6, the voltage applied to each wiring is 0 ≦ V _SS ≦ V _DD <V _Boost . The film thickness of the lattice relaxed SiGe film 3 is 50 nm, and the film thickness of the lattice relaxed SiGe film 32 is 10 nm. The film thickness of the strained Si films 4 and 42 is 5 nm. N-type impurities are diffused into the source regions 8 and 82 and the drain regions 9 and 92 of the leakage blocking transistor 102 and the n-type field effect transistor 103. The diffusion range is not only the strained Si films 4 and 42 but also the lattice relaxed SiGe films 3 and 32.

In this semiconductor device, the Ge concentration in the lattice relaxed SiGe layer 3 under the leakage blocking transistor 102 becomes smaller than the Ge concentration in the lattice relaxed SiGe film 32 under the transistor 103 constituting the CMOS. have. Therefore, the amount of deformation of the strained Si film 4 constituting the channel region 5 is smaller than that of the strained Si film 42 constituting the channel region 52. In this case, the threshold voltage of the leakage blocking transistor 102 is larger than that of the CMOS transistor 103.

Thus, even in a fully depleted SOI-MOSFET, the transistor 103 having the low threshold voltage, fineness, and high-speed operation, but high off current is used in the main CMOS logic circuit portion A, on the other hand, the threshold voltage is high and the blocking characteristic is high. The subsequent transistor 102 can be used as a leakage blocking transistor.

In the present embodiment, the p-type field effect transistor 104 has a hole channel mainly formed at an interface between the strained SiGe film 43 and the Si gap film 19. The use of the modified SiGe MOSFET as the pMOSFET is for obtaining the matching of the threshold voltage with the n-channel transistor 103 in the same manner as the Ge composition of the p-channel is increased in the modification of the semiconductor device of the first embodiment.

Fig. 7 is a band diagram of the p-channel portion of the pMOSFET in the CMOS of this embodiment.

As shown in Fig. 7, in the modified SiGe MOSFET, when the Ge composition of the channel increases, Eg-? Ms decreases, so the absolute value of the threshold voltage decreases. Here, Eg is the band gap of the strained SiGe, and φms is the difference between the work function of the gate electrode and the electron affinity of the strained SiGe. Since the dependence of the threshold voltage on the Ge composition (or strain amount) in the SiGe film is larger than that of the pMOSFET of strained Si, a larger threshold voltage adjustment range is obtained.

Next, the manufacturing method of the semiconductor device shown in FIG. 6 is demonstrated using FIG. 9 and FIG.

First, as shown in FIG. 9A, an SOI substrate composed of a buried insulating layer 2 made of SiO ₂ formed on a silicon substrate 1 and a silicon layer 21 having a thickness of 20 nm formed thereon is formed. Prepare. A mask 20 made of Si ₃ N ₄ is formed in the region where the pMOSFET is formed on the SOI substrate.

Next, using the epitaxial growth method by CVD method or MBE method, thereby growing the Si _{0 .9} Ge _{0 .1} to front substrate as shown in (b) of FIG. At this time, Si _{0 .9} having a lattice strain formed on the silicon layer (21) Ge _{0 .1} membrane (22: 80㎚ thickness) is formed, the mask 20 on the polycrystalline Si _{0 .9 .1} film is Ge ₀ (123: thickness 80 nm) is formed.

Next, as shown in FIG. 8C, the polycrystalline Si _0.9 Ge _0.1 film 123 formed on the mask 20 is peeled off. Then, the protection by a portion of a substrate to a mask and a thin film region of the Si _{0 .9} Ge _{0 .1} film forming the CMOS by a chemical dry etching. Thus CMOS forming region, the thin film Si _{0 .9} Ge _{0 .1} [Claim 2 SiGe film 23: thickness 40㎚], the leakage blocking transistor formation region has thick Si _{0 .9} Ge _{0 .1} film for [A 1 SiGe film 22: thickness 80 nm]. In addition, the leakage blocking transistor, the pMOSFET, and the nMOSFET forming regions are each formed by separating grooves by a photolithography process. By these steps, the first SiGe film 22 and the second SiGe film 23 having different thicknesses are formed on the insulating film 2.

Next, the substrate is subjected to dry thermal oxidation at 1100 ° C. By the oxidation process of claim 1 SiGe layer 22 and the SiGe film 2 (23) by being oxidized from the surface, the SiO ₂ film 15 is formed on the surface. Then, the Si atoms in the first SiGe film 22 and the second SiGe film 23 are used for bonding with oxygen atoms, while Ge atoms are released from the oxide film. These Ge atoms are accumulated in the remaining portions of the first SiGe film 22 and the second SiGe film 23.

On the other hand, a part of Ge atoms in the first SiGe film 22 and the second SiGe film 23 is diffused into the underlying silicon layer, but the buried insulating film 2 is used to prevent the Ge atoms from diffusing into the silicon substrate 1. For this purpose, as a result, oxidation progresses and the Ge composition in the first SiGe film 22 and the second SiGe film 23 increases. In addition, the interface between the buried insulating film 2 and the silicon layer becomes weak at high temperatures of 1000 ° C or higher. Accordingly, as the lattice relaxation proceeds, a thick first lattice relaxed SiGe film (thickness: 50 nm) and a thin second lattice relaxed SiGe film (thickness: 32 nm) can be formed.

In this way, also (d) a Ge composition different first lattice relaxation Si _{0 .84} Ge _{0 .16} film 3 and the second lattice relaxation on the insulating film 2, as shown in the Si 9 _{0 .6} the Ge _{0 .4} film 32 is formed. Reference numeral 15 is an oxide film.

Next, as shown in FIG. 10A, the oxide film 15 formed in FIG. 9D is peeled off with hydrofluoric acid, and the strained Si films 4 and 42 are first lattice relaxed by CVD or the like, respectively. Epitaxial growth is carried out on the SiGe film 3 and the second lattice relaxed SiGe film 32. By doing so, the strained Si films 4 and 42 are subjected to different strains according to the lattice constants of the lattice relaxed SiGe films 3 and 30 which are the respective underlying films. At this time, the polycrystalline silicon film 24 is formed on the mask 20.

Next, as shown in FIG. 10B, the strained SiGe film 43 and the Si gap film are covered with the CVD oxide film 25 in addition to the pMOSFET formation region and the polycrystalline silicon film 24 and the mask 20 are removed. (19) is sequentially grown epitaxially.

Next, as shown in FIG. 10C, the CVD oxide film 25 (FIG. 10B) is peeled off, and the gate insulating film 6 is formed on the strained Si films 4 and 42 and the Si gap film 19. , 62, 63, and gate electrodes 7, 72, 73 are formed on the gate insulating layers 6, 62, 63. Thus, the transistor is formed by the normal CMOS forming process and the wiring is formed. In this manner, the semiconductor device shown in FIG. 6 can be formed. In FIG. 10C, the same parts as in FIG. 1 are designated by the same reference numerals, and description thereof is omitted.

As described above, the present invention is not limited to each embodiment, but can be applied to many other threshold logic circuits. It can also be applied to digital and analog mixed LSIs as well as digital logic circuits. In this case, since the effective voltage amplitude can be increased by constructing an analog circuit with a transistor having a lower threshold voltage, the S / N ratio can be increased.

As stated above, in the present invention, a fully depleted field effect transistor having a different threshold voltage can be integrated on one LSI chip. As a result, a high speed and low power consumption LSI is obtained.

While the embodiments of the present invention have been described above, those skilled in the art will readily understand that additional advantages and modifications are possible in addition to the above-described features and advantages. Accordingly, the invention is not limited to the specific embodiments and representative embodiments described above, and various changes may be made without departing from the spirit or scope of the group of inventive concepts as defined by the appended claims and their equivalents. .

Claims (18)

A first lattice relaxed SiGe film formed in a first region on the insulating film, A second lattice relaxed SiGe film formed in a second region on the insulating film having a Ge composition higher than that of the first lattice relaxed SiGe film; A first strained Si film formed on the first lattice relaxed SiGe film and having a first strain amount subjected to Si strain by the first lattice relaxed SiGe film; A second strained Si film formed on the second lattice relaxed SiGe film and having a second strain amount subjected to Si strain by the second lattice relaxed SiGe film; A first depletion type first n-type field effect transistor having the first strained Si film as a channel, A second depletion type second n-type field effect transistor having the second strained Si film as a channel; Threshold voltages of the first n-type field effect transistor and the second n-type field effect transistor are different from each other, And the first n-type field effect transistor and the second n-type field effect transistor are integrated on one LSI chip. Substrate, An insulating film formed on the substrate, a first lattice relaxed SiGe film formed in a first region on the insulating film, and a first lattice relaxed SiGe film formed on the first lattice relaxed SiGe film and subjected to Si deformation by the first lattice relaxed SiGe film A first strained Si film having a first strain amount, a first gate insulating film formed on the first strained Si film, a first gate electrode formed on the first gate insulating film, and the first gate insulating film below the first gate insulating film A first channel region formed in the strained Si film, and a first source region and a first drain region formed to be spaced apart from the first strained Si film, and having the first channel region positioned therebetween, A first n-type field effect transistor comprising a first channel region, the first gate insulating layer, the first gate electrode, the first source region, and the first drain region; A second strained Si having a second lattice relaxed SiGe film formed in a second region on said insulating film and a second strain amount formed on said second lattice relaxed SiGe film and subjected to Si strain by said second lattice relaxed SiGe film; A second channel formed in the film, the second gate insulating film formed on the second strained Si film, the second gate electrode formed on the second gate insulating film, and the second strained Si film under the second gate insulating film. And a second source region and a second drain region, which are formed to be spaced apart from each other in the second strained Si film, and having the second channel region positioned therebetween, wherein the second channel region and the second drain region are formed. A second n-type field effect transistor comprising a gate insulating film, the second gate electrode, the second source region, and the second drain region, The first n-type field effect transistor and the second n-type field effect transistor have a different threshold voltage, And the first n-type field effect transistor and the second n-type field effect transistor are integrated on one LSI chip. The method of claim 2, A strained SiGe film formed in the third region on the insulating film, a third gate insulating film formed on the strained SiGe film, a third gate electrode formed on the third gate insulating film, and the strained SiGe under the third gate electrode A third channel region formed in the film, and a third source region and a third drain region formed to be spaced apart from the strained SiGe film, and having the third channel region positioned therebetween, wherein the third channel region is provided. A p-type field effect transistor comprising the third gate insulating film, the third gate electrode, the third source region and the third drain region, And the first n-type field effect transistor or the second n-type field effect transistor and the p-type field effect transistor constitute a complementary field effect transistor circuit. The method of claim 2, A strained SiGe film formed on the insulating film, a Si film formed on the strained SiGe film, a third gate insulating film formed on the Si film, a third gate electrode formed on the third gate insulating film, and the third A third channel region formed in the Si and SiGe films under the gate electrode, and a third source region and a third drain region formed to be spaced apart from the Si film, and having the third channel region positioned therebetween. And a p-type field effect transistor including the third channel region, the third gate insulating layer, the third gate electrode, the third source region, and the third drain region, And the first n-type field effect transistor or the second n-type field effect transistor and the p-type field effect transistor constitute a complementary field effect transistor circuit. A first lattice relaxed SiGe film formed in a first region on the insulating film, A second lattice relaxed SiGe film formed in a second region on the insulating film having a Ge composition higher than that of the first lattice relaxed SiGe film; A first strained Si film formed on the first lattice relaxed SiGe film and having a first strain amount subjected to Si strain by the first lattice relaxed SiGe film; A second strained Si film formed on the second lattice relaxed SiGe film and having a second strain amount subjected to Si strain by the second lattice relaxed SiGe film; A first depletion type first p-type field effect transistor having the first strained Si film as a channel, A second depletion type second p-type field effect transistor having the second strained Si film as a channel; Threshold voltages of the first p-type field effect transistor and the second p-type field effect transistor are different from each other, And the first p-type field effect transistor and the second p-type field effect transistor are integrated on one LSI chip. Substrate, An insulating film formed on the substrate, a first lattice relaxed SiGe film formed in a first region on the insulating film, and a first lattice relaxed SiGe film formed on the first lattice relaxed SiGe film and subjected to Si deformation by the first lattice relaxed SiGe film A first strained Si film having a first strain amount, a first gate insulating film formed on the first strained Si film, a first gate electrode formed on the first gate insulating film, and the first gate insulating film below the first gate insulating film A first channel region formed in the strained Si film, and a first source region and a first drain region formed to be spaced apart from the first strained Si film, and having the first channel region positioned therebetween, A first p-type field effect transistor comprising a first channel region, the first gate insulating layer, the first gate electrode, the first source region, and the first drain region; A second strained Si having a second lattice relaxed SiGe film formed in a second region on said insulating film and a second strain amount formed on said second lattice relaxed SiGe film and subjected to Si strain by said second lattice relaxed SiGe film; A second channel formed in the film, the second gate insulating film formed on the second strained Si film, the second gate electrode formed on the second gate insulating film, and the second strained Si film under the second gate insulating film. And a second source region and a second drain region, which are formed to be spaced apart from each other in the second strained Si film, and having the second channel region positioned therebetween, wherein the second channel region and the second drain region are formed. A second p-type field effect transistor comprising a gate insulating film, the second gate electrode, the second source region, and the second drain region, The first p-type field effect transistor and the second p-type field effect transistor have different threshold voltages, And the first p-type field effect transistor and the second p-type field effect transistor are integrated on one LSI chip. The semiconductor device according to any one of claims 1 to 6, wherein the Ge composition of the first lattice relaxed SiGe film is 0 and the Ge composition of the second lattice relaxed SiGe film is 12 atomic% or more. The semiconductor device according to any one of claims 1 to 6, wherein a difference in Ge composition between the first lattice relaxed SiGe film and the second lattice relaxed SiGe film is 12 atomic% or more. The Ge composition of any one of claims 1 to 6, wherein a difference in Ge composition between the first lattice relaxed SiGe film and the second lattice relaxed SiGe film is 12 atomic% or more, and the Ge composition of the second lattice relaxed SiGe film is It is 25 atomic% or more, The semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of claims 1 to 6, wherein the second lattice relaxed SiGe film is thinner than the first lattice relaxed SiGe film. Forming a first SiGe film and a second SiGe film having different thicknesses on the insulating film, Forming a first lattice relaxed SiGe film and a second lattice relaxed SiGe film having a different Ge composition by oxidizing the first SiGe film and the second SiGe film from a surface; Forming a first strained Si film having a first strain amount subjected to Si strain by the first lattice relaxed SiGe film on the first lattice relaxed SiGe film; Forming a second strained Si film having a second strain amount subjected to Si strain by the second lattice relaxed SiGe film on the second lattice relaxed SiGe film; Forming a gate insulating film on each of said first and second strained Si films; Forming a gate electrode on each of the gate insulating films, and forming the gate electrode in one LSI chip. Forming a SiGe film on the insulating film, Forming a mask having an opening formed on the SiGe film; Oxidizing the SiGe film exposed to the opening from the surface, and simultaneously forming a first lattice relaxed SiGe film located under the mask having a different Ge composition and a second lattice relaxed SiGe film located in the opening; Removing the mask; Forming a first strained Si film having a first strain amount subjected to Si strain by the first lattice relaxed SiGe film on the first lattice relaxed SiGe film; Forming a second strained Si film having a second strain amount subjected to Si strain by the second lattice relaxed SiGe film on the second lattice relaxed SiGe film; Forming a gate insulating film on each of said first and second strained Si films; Forming a gate electrode on each of the gate insulating films, and forming the gate electrode in one LSI chip. delete delete delete delete delete delete

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