JP2001257351A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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JP2001257351A
JP2001257351A JP2000065911A JP2000065911A JP2001257351A JP 2001257351 A JP2001257351 A JP 2001257351A JP 2000065911 A JP2000065911 A JP 2000065911A JP 2000065911 A JP2000065911 A JP 2000065911A JP 2001257351 A JP2001257351 A JP 2001257351A
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layer
semiconductor
semiconductor layer
insulating layer
formed
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JP3512701B2 (en
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Tetsuo Hatakeyama
Tomohisa Mizuno
Naoharu Sugiyama
Shinichi Takagi
Tsutomu Tezuka
Koji Usuda
勉 手塚
直治 杉山
智久 水野
哲夫 畠山
宏治 臼田
信一 高木
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Toshiba Corp
株式会社東芝
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Abstract

PROBLEM TO BE SOLVED: To provide a structure for forming a semiconductor element of high performance at a low cost and its manufacturing method by applying selectively sufficient strain to a channel layer in a desired semiconductor element alone, according to required element characteristic without losing effect by means of an SOI structure.
SOLUTION: Two semiconductor layers of different compositions which are separated by an insulation layer are formed on an Si substrate, and a semiconductor device of desired characteristic is formed on each semiconductor layer.
COPYRIGHT: (C)2001,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は格子歪を有する半導体層にチャネル領域を形成した半導体装置及びその製造方法に関する。 The present invention relates to relates to a semiconductor device and a manufacturing method thereof to form a channel region in a semiconductor layer having a lattice strain.

【0002】 [0002]

【従来の技術】Siを材料とする半導体素子、とりわけMOSFETの性能は、大規模集積回路(LSI)の進歩と共にこれまで年々向上してきたが、近年、リソグラフィ技術の微細化対応への限界、Siの理論的なキャリア移動度の飽和などの問題が指摘され、更なる高性能化は、困難になってきている。 BACKGROUND ART Semiconductor devices and the Si material, especially the performance of the MOSFET, has been improved year by year so far with advances in large-scale integrated circuit (LSI), in recent years, a limit to the corresponding miniaturization of lithography technology, Si are problems such as the theoretical carrier mobility of the saturation of the pointed out, higher performance is becoming difficult.

【0003】現在、Siの電子移動度を向上させMOS [0003] Currently, MOS to improve the electron mobility of the Si
FETを高性能化する方法の一つとして、Si層に格子歪を形成する技術が注目されている。 One method of high performance of the FET, techniques for forming a lattice strain in the Si layer has received attention. 一般に半導体層に格子歪を形成すると、そのバンド構造が変化し、チャネル中のキャリアの散乱が抑制されるため電子移動度の向上が期待できる。 In general, to form the lattice strain in the semiconductor layer, the band structure changes, improvement in electron mobility due to scattering of carriers in the channel is suppressed can be expected.

【0004】具体的には、Si基板上にSiよりも格子定数の大きな材料からなる混晶層、例えばGeを20% [0004] Specifically, the mixed crystal layer made of a material having a large lattice constant than Si on a Si substrate, for example, a Ge 20%
含むSiGe混晶層(以下、単にSiGe層という) SiGe mixed crystal layer containing (hereinafter, simply referred to as SiGe layer)
を、格子歪が緩和されるように厚く(数μm)形成し、 The, as the lattice strain is relaxed thick (several [mu] m) was formed,
このSiGe層上に薄いSi層(数nm)を形成すると、SiGeとSiの格子定数差による格子歪の内在するSi層(以下、歪Si層と称する。)が形成される。 When forming the thin Si layer SiGe layer (a few nm), Si layer underlying the lattice strain due to the lattice constant difference SiGe and Si (hereinafter, referred to as a strained Si layer.) Are formed.

【0005】この歪Si層をMOSFETのチャネルに用いると、格子歪のないSi層をチャネルに用いた場合の約1.76倍と大幅な電子移動度の向上を達成できることが報告されている(J.Welser, J.L. [0005] Using this strained Si layer on the channel of the MOSFET, the improvement of approximately 1.76 times the substantial electron mobility in the case of using a no lattice strain Si layer on the channel can be achieved has been reported ( J.Welser, J.L.
Hoyl,S. Hoyl, S. Tagkagi, and J. Tagkagi, and J. F. F. G
ibbons,IEDM 94−373)。 ibbons, IEDM 94-373).

【0006】一方、Siの電子移動度を向上させる別の方法として、MOSFETのチャネル長をより短くする方法があるが、チャネル長が短くなると浮遊容量の影響が大きくなるため、期待通りに電子移動度を向上することが困難になる。 On the other hand, as another method of improving the electron mobility of the Si, there is a method of shortening the channel length of the MOSFET, since the influence of the stray capacitance channel length is shortened increases, electron transfer as expected it becomes difficult to improve the degree. この浮遊容量の問題を解決するため、 In order to solve the problem of the stray capacitance,
絶縁膜上のSi層にチャネル層等を設けるSOI(Si SOI providing the channel layer or the like on the Si layer on the insulating film (Si
licon On Insulator)構造が注目されている。 licon On Insulator) structure has been attracting attention.

【0007】この構造では素子の作られるSi層が絶縁膜によりアイソレーションされるので、浮遊容量の低減や素子分離が容易となり、さらなる低消費電力化、高集積化が実現すると期待されている。 [0007] Since Si layer made of elements in this structure is the isolation by an insulating film, it is easy to reduce or isolation of stray capacitance, further reduction in power consumption, it is expected that high integration can be realized.

【0008】 [0008]

【発明が解決しようとする課題】そこで、電子移動度の向上を期待できる歪Si層を、浮遊容量の低減や素子分離が容易となるSOI構造に適用するため次のような試みが行われた。 [SUMMARY OF THE INVENTION Therefore, a strained Si layer can be expected to improve the electron mobility, attempts as follows were made to apply the SOI structure which facilitates reduction and isolation of stray capacitance .

【0009】Si基板に酸素をイオン注入した後、高温アニールを施して埋め込み酸化層を形成するSIMOX [0009] After the ion implantation of oxygen into an Si substrate, SIMOX forming a buried oxide layer is subjected to high-temperature annealing
(Silicon Implanted Oxyge (Silicon Implanted Oxyge
n)工程を用いてSOI基板を準備し、このSOI基板表面にSiより格子定数の大きいSiGe層をSOI基板表面のSi層よりも十分厚く形成する。 The SOI substrate was prepared using n) process to form sufficiently thicker than the Si layer of the large SiGe layer of the SOI substrate surface in lattice constant from Si to the SOI substrate surface.

【0010】この後、アニールを施して、Si層を塑性変形させ転位を導入することにより、SiGe層からS [0010] After this, by performing annealing, by introducing a dislocation of Si layer is plastically deformed, S a SiGe layer
i層にかかる引っ張り応力を緩和し、同時にSiGe層の格子歪を緩和する。 Relaxed according tensile stress in the i layer to reduce lattice strain in the SiGe layer at the same time. そして、格子歪の緩和されたSi Then, the lattice strain relaxed Si
Ge層上に薄膜のSi層を形成すると、引っ張り歪を有する歪Si層が形成される。 When forming the Si layer of a thin film on a Ge layer, a strained Si layer having a tensile strain is formed.

【0011】上述の方法では、SOI基板表面のSi層の塑性変形によって、そのSi層中に貫通転位やミスフィット転位などの転位が発生するが、その転位がその後の熱履歴によって1個/10μm2程度の密度でSiG [0011] In the above method, the plastic deformation of the Si layer of the SOI substrate surface, although dislocations such as threading dislocations and misfit dislocations that Si layer occurs, one of which dislocations by the subsequent thermal history / 10Myuemu2 SiG at a density of degree
e層の表面にも伝播し、歪Si層の結晶性を劣化させることが分かった。 Also propagates to the surface of e layer, were found to degrade the crystallinity of the strained Si layer. この歪Si層の結晶性劣化はその上に作製される半導体素子の特性を大きく劣化させる可能性があり、半導体素子が微細化されるほど顕著になると予想される。 The crystalline degradation of the strained Si layer may significantly degrade the characteristics of semiconductor devices to be fabricated on the semiconductor device is expected to become significant enough to be miniaturized.

【0012】従って、歪Si層の結晶性劣化させるような転位のSiGe表面への伝播を抑えるためには、これまでのところSiGe層を数μm以上の厚さで厚く形成しなければならない。 Accordingly, in order to suppress the propagation of the dislocations in the SiGe surface such as to crystallinity degradation of the strained Si layer, past the SiGe layer must thickly formed by several μm or more thick place.

【0013】しかしながら、浮遊容量の影響を抑えるS [0013] However, S to suppress the influence of the stray capacitance
OI構造の効果を十分に発揮するためには、SiO2層からチャネル層である歪Si層までの厚みを極力抑えることが必要であり、歪Si層の結晶性とSOI構造の効果とを両立させることができない。 To sufficiently exhibit the effect of the OI structure, it is necessary to suppressed as much as possible the thickness of up to the strained Si layer is a channel layer of SiO2 layers, satisfying both the effect of crystallinity and SOI structure of the strained Si layer it can not be.

【0014】また、最近の開発動向を見るに、メモリ、 [0014] In addition, in view of recent development trends, memory,
CPUなどの単一または特定機能のみのデバイスでは商品付加価値が低く、高速論理素子と記憶保持用メモリを同一基板上に有するような混載デバイス、或いはシステムLSI等と呼ばれものが注目されているが、この様な混載型の半導体装置を製造する場合、高速演算を行う半導体素子には、高速動作が可能な歪Si層利用の半導体素子が有効である一方で、記憶保持用メモリに利用される半導体素子、例えばDRAMを構成するMOSFET The single or specific functions only device such as a CPU low product value added, hybrid device that has a high-speed logic device and a storage holding memory on the same substrate, or what is called a system LSI or the like has attracted attention but, when manufacturing such a hybrid type semiconductor device, the semiconductor device to perform high-speed operation, while the semiconductor device of the strained Si layer offers high-speed operation is enabled, is used in the storage holding memory semiconductor devices that, for example, MOSFET constituting the DRAM
に要求される重要な素子特性は信頼性であって、歪Si Important elements characteristics required for is a reliable, strained Si
層中の欠陥は無視出来ない。 Defects in the layer can not be ignored.

【0015】本発明は、かかる事情に鑑みて成されたものであって、浮遊容量の小さな所望のSOI構造に、上述の結晶性劣化の問題を抑えた歪み半導体層を組み込んだ半導体装置及びその製造方法を提供することを目的とする。 [0015] The present invention, which was made in view of such circumstances, small desired SOI structure of the stray capacitance, the semiconductor device and incorporating a strained semiconductor layer which suppresses the problem of the above-mentioned crystalline degradation and to provide a manufacturing method.

【0016】 [0016]

【課題を解決するための手段】Si基板表面から酸素をイオン注入する際、イオン注入条件とその後のアニール条件を制御すると、イオン注入の濃度ピークとダメージ・ピークの各位置に、二層の埋め込み酸化層を形成可能であることが判っている(A.Ogura,Appl. When the oxygen from the Si substrate surface Means for Solving the Problems] ion implantation, by controlling the ion implantation conditions and subsequent annealing condition, in each position of the concentration peaks and damage-peak ion implantation, implantation of two layers it has been found that it is possible to form an oxide layer (A.Ogura, Appl.
Phys. Phys. Lett. Lett. vol. vol. 74, no. 74, no. 1
5, P2188, 1999)が、本発明では、半導体層、例えばSi層表面に、組成の異なる半導体層、例えばSiGe層を積層するように成長した半導体基板に、酸素をイオン注入し、濃度ピークとダメージピークの各位置に、二層の埋め込み酸化層を形成した。 5, P2188, 1999) is, in the present invention, a semiconductor layer, for example Si layer surface, semiconductor layers having different compositions, for example, the grown semiconductor substrate so as to laminate the SiGe layer, oxygen ions are implanted, and concentration peaks each position of the damage peak, to form a buried oxide layer of the bilayer.

【0017】その結果、例えばSiGe層、酸化層、S [0017] As a result, for example SiGe layer, oxide layer, S
i層、酸化層、Si層の順に二層の異なる組成を持つS i layer, S having a different composition of the oxide layer, the two layers in the order of Si layer
OI構造が形成できることを見出した。 Found that OI structure can be formed. しかも、この二層の異なる組成を持つSOI構造では、従来の技術の欄で説明したような、Si層の塑性変形による転位導入工程がないため、SiGe層の格子歪を緩和させるための高温アニールで、貫通転位等が歪半導体層に影響することがない。 Moreover, the SOI structure with different compositions of the two-layer, as described in the section of the prior art, since there is no dislocation introduced step by plastic deformation of the Si layer, high-temperature annealing for relieving lattice strain of the SiGe layer in, never penetrating dislocation or the like affects the strained semiconductor layer.

【0018】上記目的を達成するために、請求項1に係る発明は、一主面を有する半導体基板と、この半導体基板の内部に前記一主面とは略平行に離間して形成された第1絶縁層と、この第1絶縁層上に位置させられた第1 [0018] To achieve the above object, the invention according to claim 1, formed by spaced substantially parallel to the semiconductor substrate, and internal to said one main surface of the semiconductor substrate having one main surface 1 an insulating layer, a first which is then positioned on the first insulating layer
半導体層と、この第1半導体層上に選択的に形成された第2絶縁層と、前記第1半導体層とは異なる組成で前記第2絶縁層上に位置させられた第2半導体層と、前記第1半導体層とは異なる組成で前記第1半導体層上に積層して形成された第3半導体層とを備え、前記第2半導体層がチャネル領域として使用された電界効果トランジスタ及び第3半導体層がチャネル領域として使用された電界効果トランジスタとにより集積回路が構成されていることを特徴とする半導体装置を提供する。 A semiconductor layer, a second insulating layer selectively formed on the first semiconductor layer, a second semiconductor layer which is then positioned on the second insulating layer in a different composition from that of the first semiconductor layer, wherein a third semiconductor layer formed by laminating the first semiconductor layer with a different composition than the first semiconductor layer, said field effect transistor and the third semiconductor used second semiconductor layer as a channel region layer to provide a semiconductor device which is characterized in that the integrated circuit by the field effect transistor used as a channel region is formed.

【0019】また、請求項2に係る発明は、一主面を有する半導体基板と、この半導体基板の内部に前記一主面とは略平行に離間して形成された第1絶縁層と、この第1絶縁層上に位置させられた第1半導体層と、この第1 [0019] The invention according to claim 2 includes a semiconductor substrate having one main surface, and inside the one main surface of the semiconductor substrate and the first insulating layer formed spaced apart substantially parallel, the a first semiconductor layer which is then positioned on the first insulating layer, the first
半導体層上に選択的に形成された第2絶縁層と、前記第1半導体層とは異なる組成で前記第2絶縁層上に位置させられた第2半導体層と、この第2半導体層とは異なる組成で前記第2半導体層上に積層形成された第4半導体層とを備え、前記第1半導体層がチャネル領域として使用された電界効果トランジスタ及び第4半導体層がチャネル領域として使用された電界効果トランジスタとにより集積回路が構成されていることを特徴とする半導体装置を提供する。 A second insulating layer selectively formed on the semiconductor layer, a second semiconductor layer wherein the first semiconductor layer is is positioned on the second insulating layer with different composition, and the second semiconductor layer and a fourth semiconductor layer which is laminated on the second semiconductor layer with a different composition, the first semiconductor layer is a field-effect transistor and a fourth semiconductor layer which is used as a channel region is used as a channel region field effect transistor and the integrated circuit to provide a semiconductor device which is characterized by being composed.

【0020】また、請求項3に係る発明は、一主面を有する半導体基板と、この半導体基板の内部に前記一主面とは略平行に離間して形成された第1絶縁層と、この第1絶縁層上に位置させられた第1半導体層と、この第1 Further, The invention according to claim 3, a semiconductor substrate having one main surface, and inside the one main surface of the semiconductor substrate and the first insulating layer formed spaced apart substantially parallel, the a first semiconductor layer which is then positioned on the first insulating layer, the first
半導体層上に選択的に形成された第2絶縁層と、前記第1半導体層とは異なる組成で前記第2絶縁層上に位置させられた第2半導体層と、前記第1半導体層とは異なる組成で前記第1半導体層上に積層して形成された第3半導体層と、前記第2半導体層とは異なる組成で前記第2 A second insulating layer selectively formed on the semiconductor layer, the second semiconductor layer which is then positioned on the second insulating layer at a different composition than the first semiconductor layer, and the first semiconductor layer a third semiconductor layer formed by laminating the first semiconductor layer with a different composition, the second with a different composition than the second semiconductor layer
半導体層上に積層形成された第4半導体層とを備え、前記第3半導体層がチャネル領域として使用された電界効果トランジスタ及び第4半導体層がチャネル領域として使用された電界効果トランジスタとにより集積回路が構成されていることを特徴とする半導体装置を提供する。 And a fourth semiconductor layer which are laminated on the semiconductor layer, the third semiconductor layer is an integrated circuit by the field effect transistor FET and a fourth semiconductor layer which is used is used as the channel region as a channel region There is provided a semiconductor device which is characterized by being composed.

【0021】また、請求項4に係る発明は、請求項1又は請求項3に係る半導体装置の前記第3半導体層が、前記第1半導体層とは異なる格子定数を有し、圧縮歪みを有することを特徴とする半導体装置を提供する。 [0021] The invention according to claim 4, wherein the third semiconductor layer of a semiconductor device according to claim 1 or claim 3 has a lattice constant different from that of the first semiconductor layer has a compressive strain to provide a semiconductor device, characterized in that.

【0022】また、請求項5に係る発明は、請求項2又は請求項3に係る半導体装置の前記第4半導体層が、前記第2半導体層とは異なる格子定数を有し、引っ張り歪みを有することを特徴とする半導体装置を提供する。 [0022] The invention according to claim 5, wherein the fourth semiconductor layer of a semiconductor device according to claim 2 or claim 3, having a lattice constant different from that of the second semiconductor layer has a tensile strain to provide a semiconductor device, characterized in that.

【0023】また、請求項6に係る発明は、請求項1乃至請求項5に係る半導体装置の前記第1半導体層がSi [0023] The invention according to claim 6, wherein the first semiconductor layer of a semiconductor device according to claims 1 to 5 is Si
単結晶層であり、且つ前記第2半導体層がSiGe混晶層であることを特徴とする半導体装置を提供する。 A single crystal layer, and said second semiconductor layer to provide a semiconductor device which is a SiGe mixed crystal layer.

【0024】また、請求項7に係る発明は、請求項1乃至請求項5に係る半導体装置の前記第1半導体層がS [0024] The invention according to claim 7, wherein the first semiconductor layer of a semiconductor device according to claims 1 to 5 S
i、B、As、P、C、Ge、Ga、In、Al、Z i, B, As, P, C, Ge, Ga, In, Al, Z
n、Seから選ばれた少なくとも一つの材料で構成される結晶または混晶層であることを特徴とする半導体装置を提供する。 n, to provide a semiconductor device which is a crystal or mixed crystal layer composed of at least one material selected from Se.

【0025】また、請求項8に係る発明は、請求項1乃至請求項5に係る半導体装置の前記半導体基板が、Ga [0025] The invention according to claim 8, wherein the semiconductor substrate of the semiconductor device according to claims 1 to 5, Ga
As、ZnSe、SiC、Ge、SiGe、サファイア、有機ガラス、無機ガラス、プラスティックから選ばれた少なくとも一つの材料で構成される基板と積層されていることを特徴とする半導体装置を提供する。 As, it provided ZnSe, SiC, Ge, SiGe, sapphire, organic glass, inorganic glass, a semiconductor device which is characterized in that it is laminated with the substrate composed of at least one material selected from plastic.

【0026】また、請求項9に係る発明は、請求項1乃至請求項5に係る半導体装置の前記第2絶縁層と前記第2半導体層のとが、ウェハーの張り合わせ技術により一体化されていることを特徴とする半導体装置を提供する。 [0026] The invention according to claim 9 are integrated by transgressions of the second insulating layer and the second semiconductor layer of a semiconductor device according to claims 1 to 5, bonded wafer technology to provide a semiconductor device, characterized in that.

【0027】また、請求項10に係る発明は、請求項1 [0027] The invention according to claim 10, claim 1
乃至請求項6に係る半導体装置の前記第1半導体層の厚さが100nm以下であることを特徴とする半導体装置を提供する。 Or the thickness of the first semiconductor layer of a semiconductor device according to claim 6 provides a semiconductor device which is characterized in that at 100nm or less.

【0028】また、請求項11に係る発明は、半導体基板の一主面に、その半導体基板と異なる組成の第1半導体層を形成する工程と、イオン注入による損傷ピークと濃度ピークが前記半導体基板内部において異なる深さとなる条件で、前記半導体基板内部に前記一主面側から酸素をイオン注入する工程と、前記半導体基板を加熱し、 [0028] The invention according to claim 11, on one main surface of the semiconductor substrate, forming a first semiconductor layer of a different composition and its semiconductor substrate, the damage peak and peak concentration by ion implantation the semiconductor substrate under conditions such that a different depth inside the oxygen from the one main surface side within said semiconductor substrate is heated and a step of ion implantation, the semiconductor substrate,
前記半導体基板内部に注入された酸素と半導体基板構成材料との酸化物を形成することにより、前記半導体基板内部のより深い位置に第1絶縁層を、その第1絶縁層よりも浅い位置に第2絶縁層を互いに離間させて形成する工程とを具備することを特徴とする半導体装置の製造方法を提供する。 By forming the oxide of the semiconductor substrate inside injected oxygen and the semiconductor substrate constituting material, a first insulating layer in a deeper position inside the semiconductor substrate, first a position shallower than the first insulating layer 2 insulating layer was spaced apart from each other to provide a method of manufacturing a semiconductor device characterized by comprising the step of forming.

【0029】また、請求項12に係る発明は、請求項1 [0029] The invention according to claim 12, claim 1
1に係る半導体装置の製造方法に更に、前記第1絶縁層上の半導体基板の一部に、前記半導体基板とは異なる組成の第2半導体層を、前記半導体基板の一部に積層して形成する工程を備えることを特徴とする半導体装置の製造方法を提供する。 Furthermore the method for manufacturing a semiconductor device according to 1, a portion of the semiconductor substrate on the first insulating layer, a second semiconductor layer having a composition different from that of the semiconductor substrate, and laminating a portion of the semiconductor substrate formed further comprising the step of providing a method of manufacturing a semiconductor device according to claim.

【0030】また、請求項13に係る発明は、請求項1 [0030] The invention according to claim 13, claim 1
1に係る半導体装置の製造方法に更に、前記第1半導体層とは異なる組成の第3半導体層を前記第1半導体層上に積層して形成する工程を備えることを特徴とする半導体装置の製造方法を提供する。 Furthermore the method for manufacturing a semiconductor device according to 1, fabrication of a semiconductor device characterized by comprising the step of forming by stacking a third semiconductor layer of a different composition to the first semiconductor layer and said first semiconductor layer to provide a method.

【0031】 [0031]

【作用】本発明によれば、Si層の塑性変形による転位導入工程がなく、SiGe層の格子歪を緩和させるための高温アニールで、貫通転位等が歪半導体層に影響することがないため、格子歪が緩和された状態で、互いに絶縁された、組成の異なる二層の半導体層、例えばSiG According to the present invention, without rearrangement introducing step by plastic deformation of the Si layer, a high temperature annealing for relieving lattice strain of the SiGe layer, since no threading dislocations and the like will affect the strained semiconductor layer, in a state in which the lattice strain is relaxed, insulated from each other, the semiconductor layer of two layers having different compositions, for example SiG
e層とSi層を結晶性良く且つ薄く、また同時に得ることが可能になり、素子特性の劣化等の問題も解消される。 The e layer and the Si layer with good crystallinity and thin and it is possible to obtain at the same time, is solved the problem of deterioration of element characteristics.

【0032】 [0032]

【発明の実施の形態】以下、図面を参照しながら、本発明の実施例を説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention. (実施例1)図1は、本発明の半導体装置の一部を示す断面図である。 (Example 1) FIG. 1 is a sectional view showing a part of a semiconductor device of the present invention. 図1の半導体装置は、Si基板1の一主面側からその内部にイオン注入された酸素を、濃度ピークとダメージ・ピークの近傍において、夫々、基板構成材料であるSiと反応させ、SiO2の絶縁層3及び絶縁層4を形成し、SiGe層6及びSi層5を絶縁層4 The semiconductor device of FIG. 1, the one principal surface of the Si substrate 1 therein the ion implanted oxygen in the vicinity of the concentration peak and damage-peak, respectively, are reacted with Si which is a substrate constituting material, the SiO2 forming an insulating layer 3 and the insulating layer 4, an insulating layer 4 of the SiGe layer 6 and Si layer 5
により電気的に分離した二層のSOI構造を利用して構成されている。 It is constructed by utilizing the SOI structure of electrically isolated two layers by.

【0033】イオン注入後の高温アニール処理により格子歪の緩和されたSiGe層(以下、緩和SiGe層と称する。)6及びSi層5は、SOI構造にける寄生容量の低減効果を十分に発揮させるため、非常に薄く形成されており、夫々の厚さはSi層5、緩和SiGe層6 The relaxed SiGe layer of the lattice strain by high-temperature annealing after ion implantation (hereinafter, referred to as a relaxed SiGe layer.) 6 and the Si layer 5 is sufficiently exhibit the effect of reducing the parasitic capacitance takes the SOI structure Therefore, it is formed very thin, the thickness of each of Si layer 5, a relaxed SiGe layer 6
共に、10nm〜200nmの範囲に制御されている。 Both are controlled in the range of 10 nm to 200 nm.

【0034】また、緩和SiGe層6上には比較的に高速な動作を要求される半導体素子を作りこむため、引っ張り歪を有するSi層(以下、歪Si層と称する。)7 Further, since the upper relaxed SiGe layer 6 fabricate a semiconductor device requiring a high speed operation relatively, Si layer having a tensile strain (hereinafter, referred to as a strained Si layer.) 7
がCVD(Chemical Vapor Depos There CVD (Chemical Vapor Depos
ition)や、MBE(Molecular Bea ition) and, MBE (Molecular Bea
m Epitaxy)等で形成されている。 It is formed by m Epitaxy) or the like. この歪Si The strained Si
層7には、この層を利用して作り込まれるMOSFET The layer 7, MOSFET to be built using this layer
のチャンネル領域の導電型を決定するため、P型ウェル領域8及びN型ウェル領域9がB,As,P等の不純物を導入して形成されている。 To determine the conductivity type of the channel region, P-type well region 8 and N-type well region 9 is B, As, it is formed by introducing an impurity such as P.

【0035】更に、P型ウェル領域8には、選択的にP Furthermore, the P-type well region 8, selectively P
等のN型不純物が導入され、MOSFETのソース領域12及びドレイン領域13が形成されている。 N-type impurity is introduced etc., the source region 12 and drain region 13 of the MOSFET is formed. それ等、 It, etc.,
ソース領域12及びドレイン領域13間のチャンネル領域上にはゲート機能を付与するためゲート絶縁層16及びゲート電極17が積層されている。 The on the channel region between the source region 12 and drain region 13 a gate insulating layer 16 and the gate electrode 17 to impart the gate function are stacked.

【0036】同様に、N型ウェル領域9には、選択的にB等のP型不純物が導入され、MOSFETのソース領域14及びドレイン領域15が形成されている。 [0036] Similarly, the N-type well region 9, the P-type impurities such as selectively B is introduced, the source region 14 and drain region 15 of the MOSFET is formed. それ等、ソース領域14及びドレイン領域15間のチャネル領域上にはゲート機能を付与するためゲート絶縁層18 It like, a gate insulating layer for imparting gate function on a channel region between the source and drain regions 14 and 15 18
及びゲート電極19が積層されている。 And a gate electrode 19 are stacked.

【0037】ゲート絶縁層16としては、熱酸化膜、T [0037] As the gate insulating layer 16, the thermal oxide film, T
EOS、CVD膜等を用いることができる。 EOS, can be used CVD film. また、ゲート電極17に、減圧CVD法により形成された多結晶S Further, the gate electrode 17, a polycrystalline S formed by low pressure CVD
i層を用いれば、RIE(反応性イオンエッチング)により、ゲート電極形状は容易にパターニングできる。 Using the i layer by RIE (reactive ion etching), a gate electrode shape can be easily patterned.

【0038】図1で示されている範囲では、緩和SiG [0038] In the ranges shown in FIG. 1, the relaxation SiG
e層6上に構成された半導体素子は、Pチャンネル型M Semiconductor elements configured on the e layer 6, P-channel type M
OSFET及びNチャンネル型MOSFETの夫々一素子分であるが、実際のデバイスを構成するには、Pチャンネル型MOSFET及びNチャンネル型MOSFET It is a OSFET and each one sensing component of the N-channel MOSFET, to constitute a real device, P channel MOSFET and N channel MOSFET
共に多数を作り込む必要がある。 It is necessary to Komu together to make a large number.

【0039】また、歪Si層7を利用して作り込まれるMOSFETは、格子歪の無いSi層を利用して作られる半導体素子に比較し、高速な動作が期待できるので、 Further, MOSFET to be built by using a strained Si layer 7, compared to the semiconductor device produced by using the Si layer without lattice distortion, so high-speed operation can be expected,
回路的にはCMOS構成でロジックIC部として構成されるのに適している。 The circuit manner is suitable to be configured as a logic IC unit in CMOS configuration.

【0040】一方、絶縁層3上のSi層5は、CDE On the other hand, the Si layer 5 on the insulating layer 3, CDE
(ケミカル・ドライ・エッチング)や、RIEなどのドライ・エッチング処理により絶縁層4及び緩和SiGe (Chemical dry etching) or the insulating layer 4 and the relaxed SiGe by dry etching process such as RIE
層6が選択的に除去された露出表面を有しており、この表面から比較的信頼性の高い動作を要求される半導体素子が作り込まれている。 Has an exposed surface that the layer 6 is selectively removed, the semiconductor device is fabricated that require relatively reliable operation from the surface.

【0041】絶縁層4及び緩和SiGe層6が除去されたSi層5の表面からは、B,As,P等の不純物が導入され、この層を利用して作り込まれるMOSFETのチャネル領域の導電型を決定するため、P型ウェル領域10及びN型ウェル領域11が形成されている。 [0041] from the surface of the Si layer 5 insulating layer 4 and the relaxed SiGe layer 6 has been removed, B, As, is introduced impurities such as P, conductive channel region of the MOSFET to be built using this layer to determine the type, P-type well region 10 and the N-type well region 11 is formed.

【0042】更に、P型ウェル領域10には、選択的にP等のN型不純物が導入され、MOSFETのソース領域20及びドレイン領域21が形成されている。 [0042] Further, the P-type well region 10, selectively introduces N-type impurities such as P, the source region 20 and drain region 21 of the MOSFET is formed. それ等、ソース領域20及びドレイン領域21間のチャンネル領域上にはゲート機能を付与するためゲート絶縁層2 It like, a gate insulating layer for imparting gate function on the channel region between the source region 20 and drain region 21 2
4及びゲート電極25が積層されている。 4 and the gate electrode 25 are stacked.

【0043】ゲート絶縁層24としては、熱酸化膜、T [0043] As the gate insulating layer 24, the thermal oxide film, T
EOS、CVD膜等を用いることができる。 EOS, can be used CVD film. また、ゲート電極25に、減圧CVD法により形成された多結晶S Further, the gate electrode 25, a polycrystalline S formed by low pressure CVD
i層を用いれば、RIE(反応性イオンエッチング)により、ゲート電極形状は容易にパターニングできる。 Using the i layer by RIE (reactive ion etching), a gate electrode shape can be easily patterned.

【0044】同様にN型ウェル領域11には、選択的にB等のP型不純物が導入され、MOSFETのソース領域22及びドレイン領域23が形成されている。 [0044] Similarly to the N-type well region 11 is introduced P-type impurities such as selective B, the source region 22 and drain region 23 of the MOSFET is formed. それ等、ソース領域22及びドレイン領域23間のチャネル領域上にはゲート機能を付与するためゲート絶縁層26 It like, the gate insulating layer 26 since on a channel region between the source region 22 and drain region 23 to impart a gate function
及びゲート電極27が積層されている。 And a gate electrode 27 are stacked.

【0045】図1で示されている範囲では、上部に絶縁層4及び緩和SiGe層6が存在しない部分のSi層5 [0045] In the ranges shown in FIG. 1, Si layer portion insulating layer 4 and the relaxed SiGe layer 6 on top there is no 5
を利用した半導体素子は、Pチャンネル型MOSFET A semiconductor device using a can, P-channel MOSFET
及びNチャンネル型MOSFETの夫々一素子分であるが、実際のデバイスを構成するには、Pチャンネル型M And is a respective one sensing component of the N-channel-type MOSFET, to configure the actual devices, P-channel type M
OSFET及びNチャンネル型MOSFET共に多数を作り込む必要がある。 It is necessary to fabricate a large number OSFET and N-channel type MOSFET together.

【0046】また、Si層5は、結晶欠陥及び格子歪が共に極力減少させて製造されるSi基板1と同等の状態にあるため、信頼性及び安定性のある動作が期待できるので、回路的にはDRAM等のメモリ部として構成されるのに適している。 [0046] Also, Si layer 5, the crystal defects and lattice strain are both much as possible equal and the Si substrate 1 produced by reducing state, the reliable and stable operation can be expected, circuit manner It is suitable to be configured as a memory unit such as a DRAM on.

【0047】尚、ソース領域12,14,20,22及びドレイン領域13,15,21,23には、電極2 [0047] Incidentally, the source region 12,14,20,22 and drain regions 13, 15, 21, and 23, the electrodes 2
8,29,30,31,32,33が、絶縁層34及び35に選択的に設けられた開口を介してオーミックに接続されている。 8,29,30,31,32,33 is connected to the ohmic through an opening formed selectively in the insulating layer 34 and 35.

【0048】図1の実施例によれば、引っ張り歪が存在するSi層を用いたMOSFETと結晶欠陥及び格子歪が共に少ないSi層を用いたMOSFETとを同じ基板上のSOI構造上に形成できるので、両Si層の特性を十分引き出し半導体装置の高速・高性能化を図ることができる。 [0048] According to the embodiment of FIG. 1, can be formed the MOSFET MOSFET crystal defects and lattice strain using Si layer tensile strain is present with both less Si layer on the SOI structure on the same substrate since the characteristics of both Si layer can be performed at high speed and high performance of sufficiently drawer semiconductor device.

【0049】この実施例では、歪Si層7中にソース領域12,13及びドレイン領域14,15を形成したが、歪Si層7をゲート絶縁層16,18直下のみ選択的に形成してチャンネル領域とし、そのチャンネル領域に隣接させて緩和SiGe層6中にソース領域12,1 The channel in this embodiment, forming the source regions 12 and 13 and drain regions 14, 15 in the strained Si layer 7, and a strained Si layer 7 is selectively formed only directly under the gate insulating layers 16 and 18 and region, the source region relaxed in the SiGe layer 6 by adjacent to the channel region 12, 1
3及びドレイン領域14,15を形成しても良い。 3 and drain regions 14 and 15 may be formed.

【0050】図2乃び図3は、本発明に係る半導体装置の製造方法の一部の工程を示す部分断面図である。 [0050] Figure 2 乃 beauty Figure 3 is a partial cross-sectional view showing a part of steps of a method of manufacturing a semiconductor device according to the present invention. 図2 Figure 2
乃び図3により二層のSOI構造を得るための製造方法を詳述する。 By 乃 beauty Figure 3 details the production method for obtaining the SOI structure of two layers.

【0051】まず、図2に示すように、Si基板1上に格子歪を有するSiGe層(以下、歪SiGe層と称する。)2が100nm程度の厚さで形成されたウェハを用意する。 [0051] First, as shown in FIG. 2, SiGe layer having a lattice strain on the Si substrate 1 (hereinafter, referred to as strain SiGe layer.) 2 to prepare a wafer formed of about 100nm thickness. この歪SiGe層2は、40〜300nmの範囲の膜厚が好ましく、CVD(Chemical V The strain SiGe layer 2, the film thickness in the range of 40~300nm preferably, CVD (Chemical V
apor Deposition)、MBE(Mole apor Deposition), MBE (Mole
cular Beam Epitaxy)等により形成される。 Formed by cular Beam Epitaxy) or the like.

【0052】例えばCVDで形成する場合は、Siの原料ガスとGeの原料ガスを、550℃に加熱したSi基板1上に導入してSiGe層を堆積する。 [0052] For example, when formed by CVD is a raw material gas of the material gas and Ge in Si, to deposit a SiGe layer by introducing on the Si substrate 1 heated to 550 ° C.. Ge濃度は2 Ge concentration is 2
%以上50%以下の範囲で選択して良いが、素子特性の向上の観点から10%〜40%程度が望ましく、20% % May be selected in the range of 50% or less, but preferably about 10% to 40% from the viewpoint of improving device characteristics, 20%
〜30%の範囲が最適である。 To 30% of the range is optimal.

【0053】次に、所望の加速電圧及び、ドーズ量で、 Next, at a desired acceleration voltage and a dose of,
Si基板1中に酸素をイオン注入する。 Oxygen ions are implanted into the Si substrate 1. 酸素のイオン注入条件は、注入エネルギー180KeV、注入量4E1 Ion implantation conditions of oxygen implantation energy 180 KeV, implantation dose 4E1
7cm−2、基板温度600℃とした。 7 cm-2, and a substrate temperature of 600 ° C..

【0054】この段階では、歪SiGe層2とSi基板1の界面からSi基板1側へ10nm〜2μmの範囲で、好ましくは500nm〜600nmの位置に酸素の濃度ピークが、その濃度ピークよりも歪SiGe層2側に200nm〜300nm寄った位置にダメージ・ピークが存在するが、いわゆる酸化層は形成されていない。 [0054] At this stage, in the range of 10nm~2μm from the interface of the strained SiGe layer 2 and the Si substrate 1 to the Si substrate 1 side, preferably oxygen concentration peak of the position of 500nm~600nm is distorted than its concentration peak there is damage peak at a position closer 200nm~300nm the SiGe layer 2 side, but the so-called oxide layer is not formed.

【0055】このイオン注入の後、高温アニールを施すことによって、図3に示すように、濃度ピーク近傍に絶縁層3が、ダメージ・ピーク近傍に絶縁層4が形成され、二層のSOI構造、即ち、格子歪の緩和された10 [0055] After the ion implantation, by performing high-temperature annealing, as shown in FIG. 3, an insulating layer 3 in the vicinity of the concentration peak, the insulating layer 4 in the vicinity of the damage peak is formed, the two-layer SOI structure, That was mitigated lattice strain 10
nm〜200nmのSiGe層(以下、緩和SiGe層と称する。)6、10nm〜500nmのSiO2層(絶縁層4)、10nm〜200nmのSi層5、10 SiGe layer Nm~200nm (hereinafter, referred to as a relaxed SiGe layer.) SiO2 layer 6,10Nm~500nm (insulating layer 4), Si layers 5 and 10 of 10nm~200nm
nm〜500nmのSiO2層(絶縁層3)、及びSi SiO2 layer Nm~500nm (insulating layer 3), and Si
基板1の積層構造が形成される。 Layered structure of the substrate 1 is formed.

【0056】この高温アニールは、真空中でも、Ar、 [0056] The high temperature annealing, also in a vacuum, Ar,
水素、He、窒素などの不活性ガスのいずれか1種類の雰囲気中、或いはそれ等の不活性ガスの混合雰囲気中でも良く、更には、上記不活性ガスに酸素ガスを加えた混合ガス雰囲気中であっても良い。 Hydrogen, He, in any one of an atmosphere of an inert gas such as nitrogen, or it, or the like. Alternatively, even in a mixed atmosphere of an inert gas, further, in a mixed gas atmosphere by adding oxygen gas to the inert gas it may be. アニール温度は、絶縁層3及び4が図3の如く形成される温度であることが必要で、SiO2層により形成する場合は、1000℃〜 The annealing temperature must be insulating layers 3 and 4 is at a temperature that is formed as shown in FIG. 3, when forming the SiO2 layer, 1000 ° C. ~
1400℃の間であることが望ましいが、1270〜1 It is desirable that between 1400 ° C. However, 1270-1
370℃が最適である。 370 ℃ is optimal.

【0057】また、この高温アニールにより、図2の歪SiGe層2の格子歪は緩和され、格子歪が緩和された状態のSiGe混晶層、即ち緩和SiGe層6が形成される。 [0057] Moreover, this high temperature anneal, the lattice strain of the strained SiGe layer 2 of FIG. 2 is relaxed, SiGe mixed crystal layer in the state where lattice strain is relaxed, i.e. relaxed SiGe layer 6 is formed.

【0058】尚、高温アニール直後は、最上層のSiG [0058] It should be noted that, immediately after high-temperature annealing, the uppermost SiG
e層6表面にも酸化層が形成されているが、この酸化層はその後のWet処理により取り除かれるので、図3ではその酸化層の除去後の構造を示した。 Although oxide layer to e layer 6 are formed on the surface, since this oxide layer are removed by the subsequent Wet process, showing the structure after removal of the 3 oxidation layer.

【0059】また、上述の高温アニール工程で、絶縁層3及び絶縁層4の形成に要するアニール時間が長い場合には、SiGe層2中のGeが、Si層5に1%以上も拡散することがある。 [0059] Further, in the above-described high-temperature annealing process, if a long annealing time required for forming the insulating layer 3 and the insulating layer 4, Ge in the SiGe layer 2, also diffuse more than 1% in the Si layer 5 there is. これを避け、且つ図3と同様のS Avoid this, and similar to FIG. 3 of the S
i基板1、絶縁層3、Si層5、絶縁層4、及び緩和S i substrate 1, an insulating layer 3, Si layer 5, the insulating layer 4, and relaxed S
iGe層6の積層構造を得たい場合には、次の様な工程により製造することが好ましい。 If it is desired to obtain a laminated structure of iGe layer 6 is preferably manufactured by the following such processes.

【0060】即ち、SIMOX工程を用いて一層のSO [0060] That is, more of SO with SIMOX process
I基板を準備し、そのSOI基板表面のSi層に予め酸化膜を形成して、SiGe層を有する基板とウェハの張り合せ技術により接合する。 Prepare I substrate, to form a pre-oxidized film on the Si layer of the SOI substrate surface, joined by tension fit technique substrate and the wafer having a SiGe layer. ウェハの張り合せ技術によれば、比較的低温での接合が可能なため、Geの拡散を抑制することができ、元々のSiGe層中のGe濃度を大きく変えることなく図3に示される積層構造を得ることができる。 According to tension combined technology of the wafer, relatively because it can be bonded at a low temperature, it is possible to suppress the diffusion of Ge, layered structure shown in FIG. 3 without largely changing the Ge concentration of the original SiGe layer it is possible to obtain. (実施例2)図4は、本発明の第2の実施例に係る半導体装置を示す断面図である。 (Embodiment 2) FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

【0061】尚、図1の実施例における半導体装置と対応する部分には同一符号を付し、その詳細な説明は省略する。 [0061] Incidentally, the same reference numerals are given to portions corresponding to the semiconductor device in the embodiment of FIG. 1, and detailed description thereof will be omitted.

【0062】この実施例では、Si層5の上に更に圧縮歪を有するSiGe層100(以下、圧縮歪SiGe層と称する。)を形成し、この層をチャネル層として利用するゲート構造を、ゲート絶縁層101及びゲート電極102を形成して構成したものである。 [0062] In this embodiment, the SiGe layer 100 having a further compressive strain on the Si layer 5 (hereinafter, referred to as compressive strain SiGe layer.) Is formed, a gate structure utilizing the layer as a channel layer, a gate it is constructed by forming the insulating layer 101 and the gate electrode 102. ソース領域22 The source region 22
及びドレイン領域23は、チャンネル層である圧縮歪S And the drain region 23, the compressive strain S is a channel layer
iGe層100に隣接するよう形成されている。 It is formed to adjacent iGe layer 100.

【0063】このような構成にすることで、一層目のS [0063] With such a configuration, the first layer of S
OI構造上にも高速動作を必要とする半導体素子が形成可能となる。 Semiconductor devices that require high-speed operation also on OI structure becomes possible form. また、この形態で一層目のSOI構造上に高速動作を必要とする半導体素子を形成する場合は、歪Si層7の形成を省略して緩和SiGe層6により信頼性及び安定性の要求されるメモリ素子等を形成しても良い。 In the case of forming a semiconductor device that requires a high speed operation in the first layer of the SOI structure on this form is the reliability and stability required by the relaxed SiGe layer 6 is omitted formation of the strained Si layer 7 it may be formed memory element. (実施例3)図5は、本発明の第3の実施例に係る半導体装置を示す断面図である。 (Embodiment 3) FIG. 5 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

【0064】尚、図1の実施例における半導体装置と対応する部分には同一符号を付し、その詳細な説明は省略する。 [0064] Incidentally, the same reference numerals are given to portions corresponding to the semiconductor device in the embodiment of FIG. 1, and detailed description thereof will be omitted.

【0065】この実施例では、絶縁層3より上に形成されている二層のSOI構造が、緩和SiGe層200及び緩和SiGe層201で形成されている。 [0065] In this embodiment, SOI structures two layers are formed above the insulating layer 3 is formed in the relaxed SiGe layer 200 and the relaxed SiGe layer 201. 緩和SiG Relaxation SiG
e層201上には引っ張り歪みを有する歪Si層7が形成され、この層がチャネル層として利用できるように、 The on e layer 201 is formed strained Si layer 7 having a tensile strain, so that this layer can be used as a channel layer,
ゲート絶縁層16とゲート電極17が形成されていること等は第1の実施例と同様である。 It like gate insulating layer 16 and the gate electrode 17 is formed is the same as in the first embodiment.

【0066】上述の構成を得るためには、図2により説明した製造方法における歪SiGe層2の厚さを、酸素イオン注入の際のダメージ・ピーク及び濃度ピークの深さが共にSi基板1との界面を上回らないように設定すればよい。 [0066] To obtain the above structure, the thickness of the strained SiGe layer 2 in the manufacturing method described with reference to FIG. 2, the depth of the damage peak and concentration peak at the time of oxygen ion implantation and Si substrate 1 together it may be set so as not to exceed the interfaces. (実施例4)図6は、本発明の半導体装置に用いる図1 (Example 4) FIG. 6, FIG. 1 used in the semiconductor device of the present invention
乃至図3で説明された基板とは別の基板を示す断面図である。 To the substrate described in FIG. 3 is a sectional view showing another substrate.

【0067】尚、図1の実施例における半導体装置と対応する部分には同一符号を付し、その詳細な説明は省略する。 [0067] Incidentally, the same reference numerals are given to portions corresponding to the semiconductor device in the embodiment of FIG. 1, and detailed description thereof will be omitted.

【0068】図6では、図3の絶縁層4上の緩和SiG [0068] In Figure 6, the relaxation of the insulating layer 4 of FIG. 3 SiG
e層6とSi層5の上下が逆になった構造を示している。 Upper and lower e layer 6 and the Si layer 5 indicates a structure reversed. 即ち、Si層7、SiO2層(絶縁層4)、緩和S That, Si layer 7, SiO2 layer (insulating layer 4), relaxation S
iGe層6、SiO2層(絶縁層3)、Si基板1の順に積層された二層のSOI構造が示されている。 iGe layer 6, SiO2 layer (insulating layer 3), SOI structures two layers are laminated in this order on the Si substrate 1 is shown. このような二層のSOI構造を得るには、図2で用意したウェハの歪SiGe層2の表面に、更にSi層を上述のMB Thus obtaining the SOI structure of a two-layer, on the surface of the strained SiGe layer 2 of the wafer prepared in FIG. 2, further above MB the Si layer
E及びCVD等の手法で連続成長させたウェハを用いることが必要である。 It is necessary to use a wafer is continuously grown in E and techniques such as CVD.

【0069】また、その後のイオン注入工程では、高温アニール後に緩和SiGe層6に接した絶縁層4が形成されるように、歪SiGe層2上のSi層中の適切な位置にダメージ・ピークを形成するよう制御する必要がある。 [0069] In the subsequent ion implantation process, as the insulating layer 4 in contact with the relaxed SiGe layer 6 after high temperature annealing is formed, the damage peak in position Si layer on strain SiGe layer 2 it is necessary to control so as to form. しかしながら、その他のイオン注入時の濃度ピークの位置や、高温アニール等の処理については、上記図1 However, the position and the concentration peak when other ion implantation, the processing such as high temperature annealing, FIG 1
の実施例で説明したものと同様に行えば良い。 It may be performed similarly to that described in Examples.

【0070】この図6に示される二層のSOI構造を用いる場合には、絶縁層3及び絶縁層4の間にある緩和S [0070] Relaxation S In the case of using the SOI structure of two layers shown in FIG. 6, that is between the insulating layer 3 and the insulating layer 4
iGe層6の一部を選択的に露出させ、その表面に歪S Some of iGe layer 6 selectively expose the distortion S on its surface
i層を積層して高速動作素子を形成すればよく、一方高信頼性素子はSi層7を利用して作り込めば良い。 By laminating the i-layer may be formed of high-speed operation element, whereas highly reliable device can be Kome made using a Si layer 7.

【0071】 [0071]

【発明の効果】以上、本発明によれば、SOI構造の効果を損なわずに、元素、組成の異なる連続した二層のS Effect of the Invention] According to the present invention, without impairing the effect of the SOI structure, an element, different continuous bilayer compositions S
OI構造が提供できるため、例えば、歪Si系の高速論理演算素子と、高信頼性が要求されるDRAM等の素子とを同一基板上の任意の位置に作り分けることが可能である。 Because OI structure can be provided, for example, it is possible to separately form the strained Si-based high-speed logic operation device, and a device such as DRAM which high reliability is required at an arbitrary position on the same substrate. 従って、従来よりも、素子特性の劣化を抑え、低消費電力化、高集積化が可能となり、半導体素子の高性能化が実現できる。 Accordingly, even conventionally, suppressing deterioration of the device characteristics, low power consumption, enables high integration, high performance of the semiconductor device can be realized.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施例に半導体基板の部分断面図。 Figure 1 is a partial cross-sectional view of a semiconductor substrate to a first embodiment of the present invention.

【図2】本発明の半導体装置の製造方法の工程を示す部分断面図。 Partial cross sectional view showing a step of the manufacturing method of the semiconductor device of the present invention; FIG.

【図3】本発明の半導体装置の製造方法の工程を示す部分断面図。 Partial cross sectional view showing a step of the manufacturing method of the semiconductor device of the present invention; FIG.

【図4】本発明の第2の実施例に係る半導体装置の部分断面図。 Partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention; FIG.

【図5】本発明の第3の実施例に係る半導体装置の部分断面図。 Figure 5 is a partial cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

【図6】本発明の半導体装置に使用される基板の部分断面図。 Partial cross-sectional view of a substrate used in a semiconductor device of the present invention; FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1・・・Si基板 2・・・歪SiGe層 3,4,34,35・・・絶縁層 4・・・絶縁層 5・・・緩和Si層 6・・・緩和SiGe層 7・・・歪Si層 8,10・・・P型ウェル領域 9,11・・・N型ウェル領域 12,14,20,22・・・ソース領域 13,15,21,23・・・ドレイン領域 16,18,24,26・・・ゲート絶縁層 17,19,25,27・・・ゲート電極層 28〜33・・・電極 1 ... Si substrate 2 ... strained SiGe layer 3,4,34,35 ... insulating layer 4 ... insulating layer 5 ... relaxed Si layer 6 ... relaxed SiGe layer 7 ... strain Si layer 8, 10 ... P-type well region 9, 11 ... N-type well region 12,14,20,22 ... source region 13, 15, 21, and 23 ... drain regions 16, 18, 24, 26 ... gate insulating layer 17,19,25,27 ... gate electrode layer 28 to 33 ... electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 水野 智久 神奈川県横浜市磯子区新杉田町8番地 株 式会社東芝横浜事業所内 (72)発明者 畠山 哲夫 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 杉山 直治 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 高木 信一 神奈川県横浜市磯子区新杉田町8番地 株 式会社東芝横浜事業所内 Fターム(参考) 5F110 AA04 AA09 BB04 BB06 CC02 DD01 DD02 DD04 DD05 DD13 EE09 EE45 FF02 FF23 FF29 GG01 GG02 GG12 GG19 GG25 GG32 GG42 GG44 NN78 QQ17 ────────────────────────────────────────────────── ─── front page of the continuation (72) inventor Tomohisa Mizuno Yokohama, Kanagawa Prefecture Isogo-ku, Shinsugita-cho, address 8 Co., Ltd. Toshiba Yokohama workplace (72) inventor Tetsuo Hatakeyama Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho 1 address Co., Ltd., Toshiba research and development in the Center (72) inventor Naoji Sugiyama Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho, address 1 Co., Ltd. Toshiba research and development in the Center (72) inventor Shinichi Takagi Yokohama, Kanagawa Prefecture Isogo-ku, Shinsugita town address 8 Co., Ltd. Toshiba Yokohama workplace F-term (reference) 5F110 AA04 AA09 BB04 BB06 CC02 DD01 DD02 DD04 DD05 DD13 EE09 EE45 FF02 FF23 FF29 GG01 GG02 GG12 GG19 GG25 GG32 GG42 GG44 NN78 QQ17

Claims (13)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】一主面を有する半導体基板と、 この半導体基板の内部に前記一主面とは略平行に離間して形成された第1絶縁層と、 この第1絶縁層上に位置させられた第1半導体層と、 この第1半導体層上に選択的に形成された第2絶縁層と、 前記第1半導体層とは異なる組成で前記第2絶縁層上に位置させられた第2半導体層と、 前記第1半導体層とは異なる組成で前記第1半導体層上に積層して形成された第3半導体層とを備え、 前記第2半導体層がチャネル領域として使用された電界効果トランジスタ及び第3半導体層がチャネル領域として使用された電界効果トランジスタとにより集積回路が構成されていることを特徴とする半導体装置。 And 1. A semiconductor substrate having one main surface, said one main surface inside the semiconductor substrate and the first insulating layer formed by spaced substantially parallel, is positioned in the first insulating layer a first semiconductor layer which is a second insulating layer selectively formed on the first semiconductor layer, a second that is is positioned on the second insulating layer in a different composition from that of the first semiconductor layer and the semiconductor layer, wherein a third semiconductor layer formed by laminating the first semiconductor layer with a different composition than the first semiconductor layer, said field effect transistor in which the second semiconductor layer is used as a channel region and a semiconductor device in which the third semiconductor layer, characterized in that the integrated circuit by the field effect transistor used as a channel region is formed.
  2. 【請求項2】一主面を有する半導体基板と、 この半導体基板の内部に前記一主面とは略平行に離間して形成された第1絶縁層と、 この第1絶縁層上に位置させられた第1半導体層と、この第1半導体層上に選択的に形成された第2絶縁層と、 前記第1半導体層とは異なる組成で前記第2絶縁層上に位置させられた第2半導体層と、 この第2半導体層とは異なる組成で前記第2半導体層上に積層形成された第4半導体層とを備え、 前記第1半導体層がチャネル領域として使用された電界効果トランジスタ及び第4半導体層がチャネル領域として使用された電界効果トランジスタとにより集積回路が構成されていることを特徴とする半導体装置。 2. A semiconductor substrate having one main surface, said one main surface inside the semiconductor substrate and the first insulating layer formed by spaced substantially parallel, is positioned in the first insulating layer a first semiconductor layer which is a second insulating layer selectively formed on the first semiconductor layer, a second that is is positioned on the second insulating layer in a different composition from that of the first semiconductor layer and the semiconductor layer, this and a fourth semiconductor layer which is laminated on the second semiconductor layer with a different composition than the second semiconductor layer, said field effect transistor the first semiconductor layer is used as a channel region and the 4 semiconductor device in which a semiconductor layer is characterized in that the integrated circuit by the field effect transistor used as a channel region is formed.
  3. 【請求項3】一主面を有する半導体基板と、 この半導体基板の内部に前記一主面とは略平行に離間して形成された第1絶縁層と、 この第1絶縁層上に位置させられた第1半導体層と、 この第1半導体層上に選択的に形成された第2絶縁層と、 前記第1半導体層とは異なる組成で前記第2絶縁層上に位置させられた第2半導体層と、 前記第1半導体層とは異なる組成で前記第1半導体層上に積層して形成された第3半導体層と、 前記第2半導体層とは異なる組成で前記第2半導体層上に積層形成された第4半導体層とを備え、 前記第3半導体層がチャネル領域として使用された電界効果トランジスタ及び第4半導体層がチャネル領域として使用された電界効果トランジスタとにより集積回路が構成されていることを特徴とする半導体装置。 3. A semiconductor substrate having one main surface, said one main surface inside the semiconductor substrate and the first insulating layer formed by spaced substantially parallel, is positioned in the first insulating layer a first semiconductor layer which is a second insulating layer selectively formed on the first semiconductor layer, a second that is is positioned on the second insulating layer in a different composition from that of the first semiconductor layer a semiconductor layer, a third semiconductor layer formed by laminating the first semiconductor layer with a different composition from that of the first semiconductor layer, said second semiconductor layer with a different composition than the second semiconductor layer and a fourth semiconductor layer which are stacked, the third semiconductor layer is formed an integrated circuit by the field effect transistor FET and a fourth semiconductor layer which is used is used as the channel region as a channel region wherein a it is.
  4. 【請求項4】前記第3半導体層は、前記第1半導体層とは異なる格子定数を有し、圧縮歪みを有することを特徴とする請求項1又は請求項3記載の半導体装置。 Wherein said third semiconductor layer, said has a different lattice constant from the first semiconductor layer, a semiconductor device according to claim 1 or claim 3 wherein characterized in that it has a compressive strain.
  5. 【請求項5】前記第4半導体層は、前記第2半導体層とは異なる格子定数を有し、引っ張り歪みを有することを特徴とする請求項2又は請求項3記載の半導体装置。 Wherein said fourth semiconductor layer has a lattice constant different from that of the second semiconductor layer, a tensile semiconductor device according to claim 2 or claim 3 wherein characterized in that it has a distortion.
  6. 【請求項6】前記第1半導体層はSi単結晶層であり、 Wherein said first semiconductor layer is a Si single crystal layer,
    前記第2半導体層はSiGe混晶層であることを特徴とする請求項1乃至請求項5記載の半導体装置。 The semiconductor device of claim 1 to claim 5, wherein said second semiconductor layer is a SiGe mixed crystal layer.
  7. 【請求項7】前記第1半導体層はSi、B、As、P、 Wherein said first semiconductor layer is Si, B, As, P,
    C、Ge、Ga、In、Al、Zn、Seから選ばれた少なくとも一つの材料で構成される結晶または混晶層であることを特徴とする請求項1乃至請求項5記載の半導体装置。 C, Ge, Ga, In, Al, Zn, a semiconductor device of claims 1 to 5, wherein it is a crystal or mixed crystal layer composed of at least one material selected from Se.
  8. 【請求項8】前記半導体基板は、GaAs、ZnSe、 Wherein said semiconductor substrate is, GaAs, ZnSe,
    SiC、Ge、SiGe、サファイア、有機ガラス、無機ガラス、プラスチックから選ばれた少なくとも一つの材料で構成される基板と積層されていることを特徴とする請求項1乃至請求項5記載の半導体装置。 SiC, Ge, SiGe, sapphire, organic glass, inorganic glass, a semiconductor device of claims 1 to 5, wherein it is laminated with the substrate composed of at least one material selected from plastic.
  9. 【請求項9】前記第2絶縁層と前記第2半導体層のとは、ウェハーの張り合わせ技術により一体化されていることを特徴とする請求項1乃至請求項5記載の半導体装置。 9. and said second insulating layer of said second semiconductor layer is a semiconductor device that claims 1 to 5, wherein are integrated by wafer bonding technology.
  10. 【請求項10】前記第1半導体層の厚さが100nm以下であることを特徴とする請求項1乃至請求項6記載の半導体装置。 10. A semiconductor device according to claim 1 to claim 6, wherein the thickness of said first semiconductor layer is 100nm or less.
  11. 【請求項11】半導体基板の一主面に、その半導体基板と異なる組成の第1半導体層を形成する工程と、 イオン注入によるダメージ・ピークと濃度ピークが前記半導体基板内部において異なる深さとなる条件で、前記半導体基板内部に前記一主面側から酸素をイオン注入する工程と、前記半導体基板を加熱し、前記半導体基板内部に注入された酸素と半導体基板構成材料との酸化物を形成することにより、前記半導体基板内部のより深い位置に第1絶縁層を、その第1絶縁層よりも浅い位置に第2絶縁層を互いに離間させて形成する工程とを具備することを特徴とする半導体装置の製造方法。 11. A one main surface of a semiconductor substrate, comprising the steps of forming a first semiconductor layer of a different composition and its semiconductor substrate, and different depths Damage peak and peak concentration by ion implantation inside the semiconductor substrate conditions in a step of the ion implantation of oxygen from the one principal surface the inside semiconductor substrate, said heating the semiconductor substrate to form an oxide of the said injected into the semiconductor substrate oxygen and the semiconductor substrate constituting material the semiconductor device characterized by comprising the step of forming said first insulating layer in a deeper position in the semiconductor substrate, each other by separating the second insulating layer at a position shallower than the first insulating layer the method of production.
  12. 【請求項12】前記第1絶縁層上の半導体基板の一部に、前記半導体基板とは異なる組成の第2半導体層を、 12. A part of the semiconductor substrate on the first insulating layer, a second semiconductor layer having a composition different from that of the semiconductor substrate,
    前記半導体基板の一部に積層して形成する工程を更に備えることを特徴とする請求項11記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming by stacking a portion of the semiconductor substrate.
  13. 【請求項13】前記第1半導体層とは異なる組成の第3 13. The third composition different from that of the first semiconductor layer
    半導体層を前記第1半導体層上に積層して形成する工程を更に備えることを特徴とする請求項11または請求項12記載の半導体装置の製造方法。 Claim 11 or claim a method of manufacturing a semiconductor device of claim 12 wherein further comprising the step of forming stacked on the first semiconductor layer of the semiconductor layer.
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