JPH08222625A - Manufacture of dielectric isolation board - Google Patents

Abstract

PURPOSE: To eliminate a bent of a substrate at the time of heat treating at a high temperature by forming an insulating film on a single crystalline silicon substrate having grooves, then removing the film of the part which is not used as an integrated circuit, and simultaneously depositing a single crystalline silicon layer together with a polycrystalline silicon layer on the other part. CONSTITUTION: Insulating films 3, 4 are formed on a single crystalline silicon substrate 1 having grooves 2 on one main surface, and a polycrystalline silicon 6 is deposited on the main surface having the grooves 2 by a vapor growing method. Then, the surface of the silicon layer 6 is ground and polished to be flattened mirror surface, and a dielectric isolation substrate 13 is manufactured via the step of laminating the mirror surface and the main surface of a single crystalline silicon substrate 10. In this case, the film 3 of the part 5 which is not used as an integrated circuit on the main surface having the grooves 3 is removed, and a single crystalline silicon 7 is deposited at the part simultaneously by a vapor growing method to prevent the vent of the substrate 13. For example, the insulating film removed part of the part 5 which is not used as the integrated circuit is arranged on the entirety of the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dielectric isolation substrate.

[0002]

2. Description of the Related Art In the conventional method for manufacturing a dielectric isolation substrate, as shown in FIG. 4, (a) isolation grooves 2 of a required number and shape are formed on one main surface of a single crystal silicon substrate 1 by etching or the like. Then, the insulating film 3 is deposited on the surface where the separation groove 2 is formed, and then (b) the polycrystalline silicon layer 6 is deposited on the insulating film 3 by vapor phase epitaxy, The surface of the crystalline silicon layer 6 is ground and polished to manufacture the separation substrate 9.

Further, (d) the polished surface of the separation substrate 9 and the other support single crystal silicon substrate 10 are bonded together, and (e) the other surface of the separation substrate 9 is ground and polished. Then, the dielectric isolation substrate 13 is manufactured.

A related manufacturing method of this kind is, for example, Japanese Patent Publication No. 58-45182.

[0005]

According to the conventional technique, only a polycrystalline silicon layer is deposited by a vapor phase epitaxy method on a separation substrate coated with an insulating film, the surface is ground and polished, and then supported. Since a single crystal silicon substrate to be a body layer is bonded and the other surface of the separation substrate is ground and polished to manufacture a dielectric separation substrate, the separation substrate is grown from high temperature to room temperature by vapor phase epitaxy. The problem that the substrate itself is curved when the temperature is lowered or during high-temperature heat treatment in the manufacturing process for forming an integrated circuit due to the difference in the coefficient of thermal expansion between single crystal silicon and polycrystalline silicon and the contraction of polycrystalline silicon. was there.

The curvature of the substrate significantly deteriorates accuracy and uniformity when forming a window of a diffusion layer in a pattern forming process of an integrated circuit, particularly when forming a contact window and an electrode wiring in which fine processing technology is essential. However, it has been a factor that reduces the product yield.

An object of the present invention is to provide a dielectric isolation substrate having a structure in which the above-mentioned substrate does not bend.

[0008]

The curvature of the dielectric isolation substrate, which occurs when the temperature is lowered from high temperature to room temperature by the vapor phase growth method and during high temperature heat treatment in the manufacturing process for forming an integrated circuit,
It is caused by a bimetal structure having different thermal expansion coefficients between single crystal silicon and polycrystalline silicon, and contraction of polycrystalline silicon. Therefore, it has been noted that the curvature of the substrate itself can be prevented by partially forming the single crystal silicon layer in the polycrystalline silicon layer and optimizing the arrangement thereof.

That is, according to the present invention, after depositing an insulating film on a single crystal silicon substrate having a groove on one main surface and then removing the insulating film in a portion which is not used as an integrated circuit, the insulating film is deposited during vapor phase growth. A polycrystalline silicon layer is deposited on the portion where the insulating film is formed, and a single crystal silicon layer similar to the underlying single crystal silicon is deposited on the portion where the insulating film is removed. Curvature can be prevented by alleviating the shrinkage of crystalline silicon and by arranging the above structure over the entire dielectric isolation substrate.

[0010]

[Function] When the temperature is lowered from a high temperature to room temperature by the vapor phase growth method and when the high temperature heat treatment is performed in the manufacturing process for forming an integrated circuit, the curvature of the dielectric isolation substrate is caused by the thermal expansion of single crystal silicon and polycrystalline silicon. It is caused by the bimetal structure with different coefficients and the shrinkage of polycrystalline silicon.

The coefficient of thermal expansion is 3.0 × for single crystal silicon.
10 ^-6 ℃ ^-1 , polycrystalline silicon is about 4.5 × 10 ^-5 ℃ ^-1
Therefore, when the temperature is lowered from the high temperature heat treatment to room temperature, the shrinkage rate of the polycrystalline silicon becomes larger than that of the single crystal silicon. That is, the presence of the single crystal silicon layer between the polycrystal silicon layers alleviates the difference in the coefficient of thermal expansion and the contraction of the polycrystal silicon to prevent the substrate itself from being curved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings.

FIG. 1 is a sectional view for explaining a method of manufacturing a dielectric isolation substrate which is an embodiment of the present invention.
(A) A required number and shape of isolation trenches 2 are formed on one main surface of the single crystal silicon substrate 1 by etching or the like, and an insulating film 3 is deposited on the surface having the isolation trenches 2 by thermal oxidation or the like. Then, (b) the insulating film of the portion 5 not used as an integrated circuit is removed by photoetching.

Next, (c) the polycrystalline silicon layer 6 is formed on the surface of the insulating film 3 by vapor phase epitaxy, and the monocrystalline silicon layer 7 is formed on the surface of the portion 5 where the insulating film 3 is removed by photoetching and is not used as an integrated circuit. Are deposited, and (d) the surfaces of the polycrystalline silicon layer 6 and the single crystal silicon layer 7 are ground and polished to manufacture the separation substrate 9.

Further, (e) the polished surface 8 of the separation substrate 9 and the other support single crystal silicon substrate 10 are bonded together, and (f) the other surface of the separation substrate 9 is ground, The dielectric isolation substrate 13 is manufactured by polishing.

FIG. 2 is a plan view showing an example of removing the insulating film of the portion 5 which is not used as an integrated circuit by photoetching. By arranging the dielectric isolation substrate 21 in a lattice pattern over the entire surface, the effect of reducing the curvature becomes uniform over the entire substrate, so that the curvature of the substrate itself can be largely prevented.

FIG. 3 is a sectional view showing another embodiment of the present invention. A support single crystal silicon substrate 10 having a ground and polished surface of a separation substrate 9 obtained by removing the insulating film of a portion 5 not used as an integrated circuit by photoetching, and a silicon thermal oxide film serving as the other adhesive layer. Also in the dielectric isolation substrate 14 in which and are bonded together, the substrate itself can be prevented from being curved.

According to a study by the present inventor, the area ratio (= single crystal silicon layer area / polycrystalline silicon layer area) between the polycrystalline silicon layer and the single crystal silicon layer in the substrate is 0.1.
When it is set to 0 to 0.30, it is possible to remarkably prevent the dielectric isolation substrate from being curved.

[0019]

According to the present invention, dielectric separation caused by a difference in thermal expansion coefficient and contraction rate between single crystal silicon and polycrystalline silicon during vapor phase growth and high temperature heat treatment in a manufacturing process for forming an integrated circuit. The curvature of the substrate is caused by arranging a single crystal silicon layer in a lattice pattern on the entire surface of the substrate in the polycrystalline silicon layer deposited by the vapor phase growth method on the insulating film on the surface of the separation substrate having the separation groove. Can be prevented, the processing accuracy in the integrated circuit pattern forming process is improved, and a stable product yield can be obtained.

[Brief description of drawings]

1A to 1F are cross-sectional views sequentially showing manufacturing steps of a dielectric isolation substrate according to the present invention.

FIG. 2 is a layout view of a dielectric isolation substrate according to the present invention.

FIG. 3 is a sectional view of a dielectric isolation substrate according to the present invention.

4A to 4E are cross-sectional views sequentially showing a manufacturing process of a conventional dielectric isolation substrate.

[Explanation of symbols]

1, 10 ... Single crystal silicon substrate, 2 ... Separation groove, 3, 4 ...
Insulating film, 5 ... Portion not used as an integrated circuit, 6, 7 ...
Polycrystalline silicon layer, 8 ... Bonding surface, 9 ... Separation substrate, 11, 12 ... Silicon thermal oxide film, 13, 14, 21
... dielectric isolation substrate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirotaka Sakaniwa 3-1-1, Saiwaicho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi factory

Claims (4)

[Claims] 1. An insulating film is formed on a main surface of a single crystal silicon substrate and a single crystal silicon substrate having a groove on the main surface, and polycrystalline silicon is formed on the main surface having the groove by a vapor phase growth method. On the main surface having a groove in a method of manufacturing a dielectric isolation substrate, which comprises laminating a surface of the deposited layer, and then performing grinding and polishing to bond the flattened and mirror-finished surface. Remove the insulating film that is not used as an integrated circuit,
A method for producing a dielectric isolation substrate, characterized in that the substrate is prevented from being curved by simultaneously depositing single crystal silicon on the portion by the vapor phase growth method. 2. The dielectric isolation according to claim 1, wherein the portion of the main surface having the groove which is not used as an integrated circuit is arranged over the entire substrate to prevent the substrate from being curved. Substrate manufacturing method. 3. The area ratio between the polycrystalline silicon layer and the single crystal silicon layer deposited by vapor phase epitaxy according to claim 1, wherein the area ratio is 0.1.
A method of manufacturing a dielectric isolation substrate, characterized in that the substrate is prevented from being curved as 0 to 0.30. 4. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein the scribe area is made of single crystal silicon to prevent the substrate from being curved.