JPH05175325A - Dielectric isolation board and manufacturing method - Google Patents

Abstract

PURPOSE:To balance the stress and prevent a warp in a board, by depositing polycrystal silicon also on the rear side of a dielectric isolation board that is made up of a bonded substrate with an insulating film in between by bonding technique. CONSTITUTION:In a dielectric isolation board, a monocrystal silicon active layer 16 is formed on a face of an oxide film 15 while a base substrate 17 is formed on the rear side of the oxide film 15. Then, a polycrystal silicon layer 18 is deposited on the rear side of the base substrate 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation substrate, and more particularly to a dielectric isolation substrate obtained by adhering two semiconductor silicon wafers and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a dielectric isolation technique using an insulator has been known as one of element isolation techniques for semiconductor devices. Compared to the pn junction isolation technology, this dielectric isolation technology has (i) less leakage current during high temperature operation,
(Ii) No latch-up due to parasitic thyristor,
(Iii) It has features that the area required for the separation is small even when the high breakdown voltage element is separated, (iv) there is no need to consider the polarity of voltage application, and (v) the parasitic capacitance is small.

SO is a practical technique for dielectric isolation.
Known methods include a method of vapor-depositing silicon on a sapphire substrate called S, a method of recrystallizing amorphous silicon deposited on an insulating film, and a method of directly bonding a silicon wafer. Also, after etching a part of the silicon wafer to form an oxide film, polycrystalline silicon is deposited thickly and polished from the back side to remove the single crystal silicon held by the thick polycrystalline silicon and separated into islands. Methods of obtaining it are also known.

Among these methods, the method utilizing direct adhesion is an excellent method having an advantage that a thick and good quality single crystal silicon layer can be obtained as a portion for forming an element separated by a dielectric. is there.

Conventionally, the production of the dielectric isolation type substrate to which this direct adhesion is applied has been performed as shown in FIG. First, as shown in FIG. 3A, thermal oxide films 2 and 3 are formed on both side surfaces of a plane-oriented (100) single crystal silicon wafer 1 whose one surface is mirror-polished. Then, the thermal oxide film 3 and the silicon wafer 4 which is to be a support substrate and one surface of which is mirror-polished are brought into contact with each other after the cleaning, and the mirror surfaces are brought into contact with each other to firmly integrate them by heat treatment at 200 ° C. or higher, preferably 1000 ° C. or higher. Turn into. Here, the thermal oxide film 2 becomes an insulating film for dielectric isolation.

Thereafter, as shown in FIG. 1B, the single crystal silicon wafer 1 is polished to a prescribed thickness. Next, as shown in FIG. 1C, thermal oxide films 5 and 6 are formed on the surface of the adhesive substrate, and the oxide film 5 is used as a mask to etch the single crystal silicon wafer 1 into a dielectric material with an alkaline etching solution. Etching (anisotropic etching) is performed to a depth reaching the isolation insulating film 2 to form a V-shaped element isolation groove 7.

Then, as shown in FIG. 3D, an element isolation oxide film 8 is formed on the side surface of the element isolation trench 7. Further, as shown in FIG. 7E, a polycrystalline silicon layer 9 is deposited until the element isolation trench 7 is filled. Then, as shown in FIG. 6F, polishing is performed until the single crystal silicon wafer 1 is exposed to obtain a dielectric isolation type substrate.

[0008]

According to the method utilizing the direct bonding technique, a thick and good-quality dielectric-isolated silicon layer can be obtained, and it is not necessary to deposit a thick polycrystalline silicon layer. There is little warpage. However, even the substrate having such a structure is not in a warp-free state at all. The warp of the adhesive substrate occurs mainly for two reasons.

One is due to the difference in thermal expansion between silicon and the oxide film. The bonded wafers are integrated by heat treatment, but after the heat treatment, stress (represented by an arrow in FIGS. 7 and 8) is generated due to the difference in coefficient of thermal expansion between silicon and the oxide film. That is, since the thermal contraction of silicon is larger than that of the oxide film, at room temperature, the silicon tries to contract under the tensile stress and the oxide film tries to expand under the compressive stress.

As shown in FIG. 7A, two wafers having the same thickness (the semiconductor layer 10 serving as an active layer and the silicon wafer 11 serving as a base substrate) are bonded to each other with an insulating film 12 interposed therebetween. However, the center of the substrate in the thickness direction is the position of the insulating film 12 located in the middle. For this reason, the stress is balanced and there is no factor causing warpage. This also applies to the dielectric substrate in which the oxide films 13 and 14 are formed on the surfaces of the active layer 10 and the base substrate 11, as shown in FIG. 7B.

However, as shown in FIG. 8 (a), when the active layer 10 side is polished to a prescribed thickness, the center O in the thickness direction of the substrate moves to the base substrate 11 side, so that the above-mentioned silicon pulling is performed. By the action of stress and compressive stress of insulating film,
A warp occurs in which the active layer 10 side is convex. Therefore, FIG.
As shown in (b), it has been found that the oxide film 14 is formed on the back surface of the base substrate 11 side to balance the stress and reduce the warpage.

However, in forming an element on a wafer, etching of an oxide film using hydrofluoric acid, ammonium fluoride or the like is an essential step, and the oxide film provided on the back surface is also removed by this etching to form an oxide film. Returning to the previous warp, it does not lead to drastic warpage countermeasures. Therefore, as the diameter of the wafer becomes larger and the element becomes finer, it interferes with the PEP process, and it becomes difficult to form a desired element pattern.

Another cause of warpage is the deposition of polycrystalline silicon. As shown in FIGS. 6A to 6F,
Polycrystalline silicon is deposited to fill the groove, but warping occurs at this time. Then, this warp hinders the polishing process. The warpage occurs because the physical properties such as the thermal expansion coefficient are different between the polycrystalline silicon and the crystalline silicon of the substrate,
This is because polycrystalline silicon contracts during deposition. The degree of warpage varies greatly depending on the deposition conditions. Therefore, it is difficult to reduce the warp by a method in which a film such as an oxide film is attached to the back surface to balance the stress.

As described above, in the dielectric isolation substrate obtained by applying the adhesion technique to the substrate adhered via the insulating film, as described above, it is effective to prevent the warpage by applying the oxide film to the back surface. Although it is a means, there is a problem that it is removed in a later step, the warp recurs, and the warp occurs at the time of depositing the polycrystalline silicon, so that accurate polishing and highly accurate patterning cannot be performed.

The present invention has been made in view of the above problems, and has solved the problem that the recurrence of the warp or the warp occurring at the time of depositing the polycrystalline silicon, which makes it impossible to perform accurate polishing or highly accurate patterning. It is an object to provide a substrate and a method for manufacturing the substrate.

[0016]

That is, according to the present invention, a first semiconductor having a predetermined thickness and a second semiconductor thicker than the first semiconductor are integrally formed via an insulating film. In the dielectric isolation substrate, polycrystalline silicon is provided on the surface of the second semiconductor.

The present invention is also directed to a first device having a predetermined thickness.
And a second semiconductor thicker than the first semiconductor are integrally formed via an insulating film, and a groove reaching from the surface of the first semiconductor to the insulating film is formed to form the first semiconductor.
In the dielectric isolation substrate in which the semiconductor of
Polycrystalline silicon is provided in the groove and on the surface of the second semiconductor.

Furthermore, the present invention provides a first device having a predetermined thickness.
And a second semiconductor thicker than the first semiconductor are integrally formed with an insulating film interposed therebetween. And a step of depositing polycrystalline silicon on the surface.

The present invention also relates to the first aspect having a predetermined thickness.
And the second semiconductor which is thicker than the first semiconductor are integrally formed with an insulating film interposed therebetween. In order to divide the first semiconductor into a plurality of semiconductors, A method of manufacturing a dielectric isolation substrate, which comprises the step of forming a groove reaching from the surface to the insulating film, the method including the step of depositing polycrystalline silicon in the groove and on the surface of the second semiconductor. It is characterized by

[0020]

In the dielectric isolation substrate and the method of manufacturing the same according to the present invention, the first semiconductor having a predetermined thickness and the second semiconductor thicker than the first semiconductor are integrated via the insulating film. In a dielectric isolation substrate having a specific structure, polycrystalline silincon is provided on the back surface of the dielectric isolation substrate. Further, an oxide film may be provided between the polycrystalline silicon and the second semiconductor.

Further, in the present invention, in the dielectric isolation substrate in which the active layer is divided into a plurality of grooves, polycrystalline silicon is provided in the grooves and on the back surface of the substrate. Then, these polycrystalline silicons are simultaneously deposited. Further, according to the present invention, the surface of the polycrystalline silicon provided on the back surface of the substrate is oxidized, and the oxide film is removed if necessary.

[0022]

Embodiments of the dielectric isolation substrate and the method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a dielectric isolation substrate according to the present invention. In the figure, an active layer (silicon) 16 is provided on the front surface of the oxide film 15, and a base substrate (silicon) 17 is provided on the back surface. The dielectric isolation substrate has a structure in which the polycrystalline silicon layer 18 is deposited on the back surface of the base substrate 17.

When the dielectric isolation substrate is constructed in this way,
Due to the difference in thermal expansion between the oxide film and the silicon, the surface of the thinner silicon 16 that contacts the surface of the substrate warps in a convex shape. on the other hand,
The degree of warpage due to the deposition of the polycrystalline silicon layer 18 changes depending on the deposition conditions. That is, if the polycrystalline silicon layer 18 is deposited on the back surface of the base substrate 17 as shown in the figure under the condition that the side of the polycrystalline silicon layer 18 is convexly warped, the warps can be canceled and reduced.

Although not shown, the polycrystalline silicon layer 1
It is also possible to further adjust the warp by providing an oxide film between the substrate 8 and the base substrate 17. In this case, since the oxide film is covered with polycrystalline silicon, it will not disappear during the subsequent process.

The method of providing the polycrystalline silicon 18 on the back surface of the base substrate 17 to reduce the warp will be described later in detail with reference to FIG.
As described above, it is particularly effective in the dielectric isolation substrate in which the polycrystalline silicon layer 28 is also provided on the surface side of the substrate to fill the groove 27 and the manufacturing process thereof. This is because there is a surface flattening step by polishing after the deposition of polycrystalline silicon, and the warp reduces the accuracy of this step. The warp due to the polycrystalline silicon layer changes depending on the deposition conditions. However, if the polycrystal silicon layers are deposited to have substantially the same thickness on both sides as shown in FIG.

The present inventor has found that when the deposited polycrystalline silicon is oxidized, the surface on the polycrystalline silicon side is warped in a convex shape. One reason for the warpage is that the volume of polycrystalline silicon increases due to oxidation. However, even if the oxide film formed on the surface of the polycrystalline silicon is removed by etching or the like, the warpage cannot be restored. It is considered that this is because interstitial silicon generated during oxidation fills a large number of silicon vacancy contained in the polycrystalline silicon, and as a result, the volume of the polycrystalline silicon increases.

In any case, by oxidizing the polycrystalline silicon, the side on which the polycrystalline silicon is deposited warps in a convex shape. Then, if the polycrystalline silicon provided on the back surface of the dielectric isolation substrate is oxidized, the back surface side warps convexly, and the warpage due to the difference in thermal expansion between the oxide film and silicon can be canceled to reduce the warpage of the substrate. Hereinafter, the same embodiment will be specifically described.

Using a silicon wafer of n type, specific resistance of 20 to 30 Ω · cm, plane orientation (100) and thickness of 500 μm, a dielectric isolation substrate was produced by direct bonding. The specific steps of direct bonding are as follows. First, the wafer to be bonded is treated with H ₂ SO ₄ -H ₂ O ₂ mixed solution, HCl-H ₂ O.
₂ mixture, choline and H ₂ O ₂ mixture, ammonia and H
After washing with a mixture of ₂ O ₂ and aqua regia, it is washed with water for about 10 minutes and dehydrated and dried with a spinner. The wafer that has been subjected to these treatments is placed in a clean atmosphere of, for example, class 100 or less, and its mirror-polished surfaces are brought into close contact with each other with substantially no foreign matter present. As a result, the two wafers are bonded together with some strength.

By heat-treating the substrates thus bonded in a diffusion furnace or the like, the bonding strength is increased and the two wafers are completely integrated. The improvement in adhesive strength is observed by heat treatment at about 200 ° C or higher. The heat treatment atmosphere is not particularly limited, and it can be performed in oxygen, nitrogen, hydrogen, an inert gas, water vapor, or a mixed atmosphere thereof. In this example, cleaning is performed with a H ₂ SO ₄ —H ₂ O ₂ mixture solution and a HCl—H ₂ O ₂ mixture solution, and the heat treatment is performed in nitrogen containing a small amount of oxygen.
It was carried out at 0 ° C. for 2 hours. Next, a method for manufacturing the dielectric isolation substrate of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2A, an oxide film 21 is formed on each of the front and back surfaces of the first single crystal silicon which becomes the active layer 19 of the wafer and the second silicon which becomes the base substrate 20. 22 and 23 and 24 are formed to 1 μm. And
After performing the above-described cleaning, drying is performed in a clean atmosphere, the mirror surfaces are brought into contact with each other, and then heat treatment is performed at 1100 ° C. for 2 hours in nitrogen containing a small amount of oxygen to form a strongly integrated substrate. obtain. Here, the oxide films 21 and 23 serve as dielectric isolation insulating films. Next, as shown in FIG. 3B, the active layer 19 to be a semiconductor layer is polished to have a thickness of 50 μm.

Then, as shown in FIG. 3C, an oxide film 25 is formed on the semiconductor layer 19 adjusted to have a specified thickness. Next, using the oxide film 25 as a mask, etching (anisotropic etching) is performed with an alkaline etching solution until the dielectric insulating film interposed at the adhesive interface is reached to form a separation groove, and a V-shaped element is formed. The separation groove 26 is formed. Next, as shown in FIG. 3D, an element isolation insulating film 27 is formed on the side surface of the V-shaped element isolation groove 26.

Further, as shown in FIG. 3E, a polycrystalline silicon layer 28 is formed until the element isolation trench 26 is filled, and a polycrystalline silicon layer 29 is formed on the back surface of the base substrate 20.
Are simultaneously deposited. This step results in the bonded substrate being completely encapsulated by the polycrystalline silicon layer.

Then, as shown in FIG. 3F, polishing is performed in the final step until the semiconductor layer (single crystal silicon) 19 is exposed. This makes it possible to obtain a dielectric isolation substrate in which a single crystal island region surrounded by a dielectric insulating film is formed.

For comparison with the present invention, the same silicon wafer was used to form an adhesive substrate by the conventional method of FIG. 6, and the warpage of both substrates was compared. As a result, the substrate of the embodiment of the present invention was obtained. There was almost no warp, demonstrating the effect of the present invention.
Further, in order to examine the influence of the process for producing a semiconductor, the substrate manufactured by the same example was immersed in 10% hydrofluoric acid for 1 hour, but there was no influence on the warpage.

Although the dielectric isolation substrate by direct adhesion has been described above, the present invention is similarly applied to a dielectric isolation substrate using another adhesion method such as an electrostatic adhesion method or a spin-on-glass adhesion method. It is possible.

For example, in FIG. 3, the oxide film 30 is provided on the surface side.
The polycrystalline silicon layer 33 is provided on the back surface of the base substrate 32 provided with the active layer 31. Then, the back surface of the polycrystalline silicon layer 33 is further oxidized to deposit an oxide film 34.
As described above, if the polycrystalline silicon layer 33 is oxidized, the back surface warps in a convex shape, and the warp due to the difference in thermal expansion between the oxide film and silicon can be canceled to reduce the warp of the substrate.

FIGS. 4A to 4D show an example of a method of manufacturing a dielectric isolation substrate in which polycrystalline silicon on the back surface is oxidized. FIG. 4A is the same as FIG. 2E, and the steps up to this point are as shown in FIGS. At this point, the surface of the dielectric isolation substrate (upper side in the figure) is convexly warped due to the influence of the oxide films 21 and 23. Since the polycrystalline silicon layers 28 and 29 have almost the same thickness on the front and back sides, they cancel each other out and have no effect. FIG. 4B shows a state in which thermal oxide films 35 and 36 are provided on this dielectric isolation substrate. The warp in this case is the same as in FIG.

FIG. 6C shows a state after the polycrystalline silicon layer other than the grooves on the surface side is removed by polishing. In this substrate, the warpage due to the oxide films 21 and 23 and the warpage due to the polycrystalline silicon layer 29 on the back surface cancel each other, so that the warpage of the substrate is small. The warp due to polycrystalline silicon changes depending on the deposition conditions, but it can be made a constant warp amount by oxidation. As a result, it becomes easier to control the warp of the substrate, and the degree of freedom in the polycrystalline silicon deposition conditions increases.

FIG. 6D shows a dielectric isolation substrate from which the oxide film 36 on the polycrystalline silicon layer on the back surface is removed. Even if the oxide film 36 is removed, the warp of the polycrystalline silicon layer is maintained, so that the warp of the substrate remains small.

Generally, the oxide film deposited on the back surface of the dielectric isolation substrate is etched and disappears during the process of manufacturing a semiconductor element on the substrate. By removing the oxide film in advance as in the present invention, the change in the warp of the substrate during the element manufacturing process becomes small.

The order of removing the polycrystalline silicon layer 28 on the front surface, the oxide film 35 on the polycrystalline silicon layer 28, and the oxide film 36 on the rear surface does not affect the final warp of the substrate. It can be changed according to the convenience of the substrate manufacturing process.

Further, FIGS. 5A and 5B show an example in which the element isolation trench 37 for isolating the semiconductor layer 19 is a trench-like narrow trench. Polycrystalline silicon layers 28 and 29 are deposited by low pressure CVD. Reference numeral 38 is an element isolation insulating film. The same effect can be obtained with the dielectric isolation substrate having such a configuration.

[0044]

As described above, according to the present invention, it is possible to solve the problems that the recurrence of the warp or the warp occurs at the time of depositing the polycrystalline silicon, and the accurate polishing and the highly accurate patterning cannot be performed. It is also possible to provide a method for manufacturing the same, and to increase the diameter of the dielectric isolation substrate, increase the accuracy of patterning, and improve the fine performance of the dielectric isolation element, which have been impossible due to warpage in the related art. ..

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a dielectric isolation substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing steps of a method for manufacturing a dielectric isolation substrate according to the present invention.

FIG. 3 is a sectional view showing a structure of a dielectric isolation substrate according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view showing steps of another example of the method for manufacturing a dielectric isolation substrate according to the present invention.

FIG. 5 is a cross-sectional view showing a structure of a dielectric isolation substrate according to still another embodiment of the present invention.

FIG. 6 is a cross-sectional view showing steps of a conventional method for manufacturing a dielectric isolation substrate.

FIG. 7 is a cross-sectional view for explaining warpage of the substrate due to stress.

FIG. 8 is a cross-sectional view for explaining warpage of the substrate due to stress.

[Explanation of symbols]

15, 21, 22, 23, 24, 25 ... Oxide film, 16,
19 ... Active layer, 17, 20 ... Stand substrate, 18, 28, 29
... Polycrystalline silicon layer, 26 ... Element isolation trench, 27 ... Element isolation insulating film.

Front page continuation (72) Inventor Kazuhiro Tanaka 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Co., Ltd.

Claims (8)

[Claims] 1. A dielectric isolation substrate in which a first semiconductor having a predetermined thickness and a second semiconductor thicker than the first semiconductor are integrally formed with an insulating film interposed therebetween, A dielectric isolation substrate, characterized in that polycrystalline silicon is provided on the surface of a second semiconductor. 2. A first semiconductor having a predetermined thickness and a second semiconductor thicker than the first semiconductor are integrally formed through an insulating film, and are insulated from the surface of the first semiconductor. In a dielectric isolation substrate in which a groove reaching a film is formed and the first semiconductor is separated into a plurality of pieces, polycrystalline silicon is provided in the groove and on the surface of the second semiconductor. A dielectric isolation substrate characterized by. 3. An oxide film provided on the surface of polycrystalline silicon on the surface of the second semiconductor.
The dielectric isolation substrate according to. 4. A dielectric isolation substrate comprising a step of integrally forming a first semiconductor having a predetermined thickness and a second semiconductor thicker than the first semiconductor via an insulating film. 2. The method for manufacturing a dielectric isolation substrate according to claim 1, further comprising the step of depositing polycrystalline silicon on the surface of the second semiconductor. 5. A step of integrally forming a first semiconductor having a predetermined thickness and a second semiconductor thicker than the first semiconductor via an insulating film, the first semiconductor A step of forming a groove reaching the insulating film from the surface of the first semiconductor in order to divide the first semiconductor into a plurality of layers. A method of manufacturing a dielectric isolation substrate, comprising a step of depositing polycrystalline silicon on a surface. 6. The method of manufacturing a dielectric isolation substrate according to claim 5, wherein the step of depositing the polycrystalline silicon is simultaneously performed in the groove and on the surface of the second semiconductor. 7. The method for manufacturing a dielectric isolation substrate according to claim 4, further comprising a step of thermally oxidizing the surface of the second semiconductor after the step of depositing the polycrystalline silicon. 8. The method according to claim 7, further comprising a step of removing the oxide film after the step of thermally oxidizing the surface of the second semiconductor.
A method for manufacturing a dielectric isolation substrate as described in.