JPH0324719A - Forming method of single crystal film and crystal products - Google Patents

Forming method of single crystal film and crystal products

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Publication number
JPH0324719A
JPH0324719A JP15834989A JP15834989A JPH0324719A JP H0324719 A JPH0324719 A JP H0324719A JP 15834989 A JP15834989 A JP 15834989A JP 15834989 A JP15834989 A JP 15834989A JP H0324719 A JPH0324719 A JP H0324719A
Authority
JP
Japan
Prior art keywords
single crystal
mask
crystal
wafer
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15834989A
Other languages
Japanese (ja)
Inventor
Kenji Yamagata
憲二 山方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15834989A priority Critical patent/JPH0324719A/en
Publication of JPH0324719A publication Critical patent/JPH0324719A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily form a single crystal Si film whose orientation is arranged in order, by utilizing selective epitaxial growth of an Si wafer, setting the window size, the mask thickness, and the pitch between windows, etc., at suitable values, eliminating a mask, oxidizing the whole part, and polishing the adequate amount of crystal. CONSTITUTION:Crystal growth processing is performed on a silicon substrate wherein a silicon wafer 1 surface is exposed from a minute aperture part of a mask 2 formed on the silicon wafer 1 surface, and single crystal 3 is grown in the mask 2 surface, from a minute exposed surface. The mask 2 is eliminated, a substratum is subjected to oxidizing process, and polishing is performed from the edge of the grown single crystal side. That is, by a series of the above treatments, the grown part by selective epitaxial growth and lateral direction growth can be electrically isolated from the initial Si wafer 1. Further, by performing polishing from above so as to slightly leave the grown part, an Si single crystal film 3 having the same face orientation as the original Si wafer 1 can be formed. Thereby an Si single crystal film wherein not only the face orientation of each region but also the orientation in a face are arranged in order can be easily obtained.

Description

【発明の詳細な説明】 【産業上の利用分野] 本発明は酸化物上の単結晶膜の形成方法に関し、詳しく
は、半導体集積回路等の電子素子、表面音響素子等に使
用される単結晶膜に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a single crystal film on an oxide, and specifically relates to a method for forming a single crystal film on an oxide, and more specifically, a single crystal film used in electronic devices such as semiconductor integrated circuits, surface acoustic devices, etc. Regarding membranes.

[従来の技術] 一般に、SiOg等の非品質絶縁物基板上に薄膜を堆積
させると、基板材料の長距離秩序の欠如によって、堆積
物の結晶構造は非晶質又は多結晶となる。ここで非晶質
膜とは、最近接原子程度の近距離秩序は保存されている
が、それ以上の長距離秩序は無い状態の膜であり、多結
晶膜とは、特定の結晶方位を持たない単結晶粒が粒界で
隔離されて集合した膜である. 例えば、SiOi上にSt多結晶をCVD法によって形
成する場合、堆積温度が約580℃以下であれば非品質
シリコンとなり、それ以上の温度であれば粒径が数百〜
数千入の間で分布した多結晶シリコンとなる。ただし、
多結晶シリコンの粒径およびその分布は形成方法によっ
て大きく変化する。
BACKGROUND OF THE INVENTION Generally, when thin films are deposited on non-quality insulating substrates such as SiOg, the crystal structure of the deposit is amorphous or polycrystalline due to the lack of long-range order in the substrate material. Here, an amorphous film is a film in which short-range order at the level of the nearest neighbor atoms is preserved, but no longer-range order, and a polycrystalline film is a film that has a specific crystal orientation. It is a film made up of single crystal grains that are isolated and aggregated by grain boundaries. For example, when forming St polycrystals on SiOi by the CVD method, if the deposition temperature is below about 580°C, it will result in poor quality silicon, and if the temperature is higher than that, the grain size will be several hundred to
It becomes polycrystalline silicon distributed between several thousand pieces. however,
The grain size and distribution of polycrystalline silicon vary greatly depending on the formation method.

さらに、非品質または多結晶膜をレーザや棒状ヒータ等
の熱エネルギーによって溶融固化させることによって、
ミクロンあるいはミリメートル程度の大粒径の多結晶薄
膜が得られている(SingleCrystal Si
licon on Non−single−cryst
alInsulators,Journal of C
rystal Growth vol.63.No.3
,October 1983 edited by G
J.Cullen) .このようにして形成された各結
晶構造の薄膜にトランジスタを形成し、その特性から電
子易動度を測定し、単結晶シリコンにおける電子易動度
を比較すると、溶融固化による数μ鵬〜数amの粒径を
有する多結晶シリコンでは、単結晶シリコンの場合と同
程度であり、数百〜数千人の粒径分布を有する多結晶シ
リコンでは単結晶シリコンの場合の10−”程度であり
、また非品質シリコンでは単結晶シリコンの2X10”
’程度の電子易動度が得られている. この結果から、結晶粒内の単結晶領域に形成された素子
と、粒界にまたがって形成された素子とは、その電気的
特性に大きな差異のあることが分る.すなわち、従来法
で得られていた非品質上の堆積膜は非晶質又は粒径分布
をもった多結晶構造となり、そこに作製された素子は、
単結晶層に作製された素子に比べて、その性能が大きく
劣るものとなる.そのために、用途としては簡単なスイ
ッチング素子、太陽電池、光電変換素子等に限られる. 従って、高性能な電子素子を形成するためには、粒界が
無いか、もしくは粒界の位置の制御された半導体単結晶
薄膜が必要となる. 粒界が無い非品質上のSL単結晶薄膜の例としてS O
 S (Silicon on Sapphire)や
SIMOX(Separation by Impla
ntation of Oxygen)、貼り合わせ、
酸化分離(USP 4,361,600)等が報告され
ており、粒界の位置の制御された半導体薄膜の形成方法
として、特開昭63−107016号が報告されている
. SOSは基板にサファイヤ《単結晶AI!Os)を使用
し、その表面にSLをヘテロエビタキシャル成長させる
ものである。この技術は、サファイヤ基板が非常に高価
であることと、Si膜中に基板の構成成分であるAlが
拡散してしまうという問題点を有している. SIMOXは、SiウエハにO”(酸素イオン)ヲ高エ
ネルギー注入し、アニールすることによって表面のSL
の単結晶構造を保ったまま、ウエハ内にSin.の中間
層を形成する技術である。この技術は非常に高エネルギ
ーで、しかも高濃度な酸素イオンを注入するためスルー
ブットが悪く、また高温?アニールが必要なために基板
への応力が心配されている. また、貼り合わせ技術とは、表面が酸化された2枚のS
iウエハ、もしくは1枚は酸化されもう1枚は酸化され
ていない組み合わせの2枚のSiウエハを、貼り合わせ
てアニールすることにより、原子レベルで密着させ、片
方側から研磨してSi層が薄膜として残るところで研磨
を止める単結晶Si薄膜の形成方法である.この方法は
、片方のウエハの殆どを研磨してしまうために、コスト
が高くなることと、もともと厚さにバラッキのあるウエ
ハを研磨し、僅かにSi層を残す位置で研磨を止めなけ
ればならないので、その制御が非常に困難である. 酸化分離は、Stウエハの表面に凹凸を形成し、凸部の
上面と側面にマスクを施してから全体を酸化するもので
ある。これによりマスクの施されていない部分から酸化
が進み、凸部全体がSiO■によって基板側と絶縁分離
されるものである.しかし、この方法ではSOIの構造
は得られるが、St層が薄膜でなくバルク(塊状)に分
離される。これを研磨したとしてもSiOiとSiの界
面が平坦でないため、St単結晶薄膜は得られない。
Furthermore, by melting and solidifying non-quality or polycrystalline films using thermal energy such as a laser or a rod-shaped heater,
Polycrystalline thin films with large grain sizes on the order of microns or millimeters have been obtained (Single Crystal Si
licon on non-single-cryst
alInsulators, Journal of C
crystal growth vol. 63. No. 3
, October 1983 edited by G
J. Cullen). A transistor was formed in the thin film of each crystal structure formed in this way, and the electron mobility was measured from its characteristics, and when compared with the electron mobility in single crystal silicon, it was found that the electron mobility due to melting and solidification ranges from several micrometers to several am. For polycrystalline silicon with a grain size distribution of , it is about the same as that for single-crystal silicon, and for polycrystalline silicon with a grain size distribution of several hundred to several thousand, it is about 10-'' of single-crystal silicon, In addition, non-quality silicon is 2x10” of single crystal silicon.
An electron mobility of about ' is obtained. These results show that there is a large difference in electrical properties between devices formed in single crystal regions within crystal grains and devices formed across grain boundaries. In other words, the deposited film of poor quality obtained by the conventional method has an amorphous or polycrystalline structure with a grain size distribution, and the device fabricated there has a
Its performance is significantly inferior to devices fabricated using single crystal layers. Therefore, its applications are limited to simple switching elements, solar cells, photoelectric conversion elements, etc. Therefore, in order to form high-performance electronic devices, semiconductor single-crystal thin films with no grain boundaries or with controlled grain boundary positions are required. As an example of a non-quality SL single crystal thin film without grain boundaries, SO
S (Silicon on Sapphire) and SIMOX (Separation by Impla)
ntation of Oxygen), lamination,
Oxidation separation (USP 4,361,600) has been reported, and JP-A-63-107016 has been reported as a method for forming semiconductor thin films with controlled grain boundary positions. SOS uses sapphire (single crystal AI!) on the substrate. (Os), and SL is heteroebitaxially grown on its surface. This technique has the problems that the sapphire substrate is very expensive and that Al, which is a component of the substrate, diffuses into the Si film. SIMOX implants high-energy O'' (oxygen ions) into a Si wafer and anneales it to reduce the SL on the surface.
While maintaining the single crystal structure of Sin. This is a technology for forming the intermediate layer of This technology uses very high energy and implants highly concentrated oxygen ions, resulting in poor throughput and high temperatures. Because annealing is required, stress on the substrate is a concern. In addition, the bonding technology consists of two sheets of S with oxidized surfaces.
I-wafers, or two Si wafers, one oxidized and the other not, are bonded together and annealed to make them adhere at the atomic level, and polished from one side to form a thin Si layer. This is a method of forming a single-crystal Si thin film in which polishing is stopped when a . This method is expensive because it polishes most of one wafer, and it also requires polishing a wafer that originally has uneven thickness and stopping polishing at a position where only a small amount of the Si layer remains. Therefore, it is extremely difficult to control. Oxidation separation involves forming irregularities on the surface of the St wafer, applying a mask to the top and side surfaces of the convex parts, and then oxidizing the entire wafer. As a result, oxidation progresses from the unmasked portion, and the entire convex portion is insulated from the substrate side by SiO2. However, although this method provides an SOI structure, the St layer is separated into a bulk instead of a thin film. Even if this is polished, an St single crystal thin film cannot be obtained because the interface between SiOi and Si is not flat.

また、以上の様な基板により限定される方式に対して、
特開昭63−107016号のように基板により限定さ
れず、粒界位置の制御された半導体単結晶薄膜を得る方
法もある.これは核形成密度の異なる2種類の非品質材
料を用いて、任意の点に半導体単結晶の核を形成し、選
択成長を行なって、成長した結晶同志を任意の位置で衝
突させ、粒界を形成し得るものである。
In addition, for the method limited by the board as described above,
There is also a method of obtaining a semiconductor single crystal thin film with controlled grain boundary positions, which is not limited by the substrate, as disclosed in JP-A-63-107016. This method uses two types of non-quality materials with different nucleation densities to form semiconductor single crystal nuclei at arbitrary points, performs selective growth, causes the grown crystals to collide with each other at arbitrary positions, and forms grain boundaries. can be formed.

[発明が解決しようとする課題] 以上の様に、上記従来例はそれぞれが優れた特徴を有し
ている反面、多くの問題点をかかえていた. 従って、本発明の目的は、■比較的安価なS1ウエハを
使用し、■一般的な装置と一般的なプロセスを使用し、
■面内の任意の面積で絶縁分離され、しかもそれぞれの
領域の面方位はもちろん面内方位まで揃ったSi単結晶
膜を提供することにある. [課題を解決するための手段及び作用]本発明に従って
、シリコンウェハ表面に形成されたマスクの微小な開口
部より、下地材料のシリコンウェハ表面を露出させた基
体に結晶或長処理を施し、前記微小な露出面より前記マ
スク面上に単結晶を成長せしめ、 マスクを除去し、該基体に酸化処理を施し、前記酸化処
理を施した基体を、成長した単結晶側から研磨を行なう
ことを特徴とする単結晶膜の形成方法、及び、前記方法
により得られた結晶物品、 並びに、微小な開口部を有するマスクと、単結晶性材料
からなる下地材料と、を有する基体に結晶成長処理を施
し、前記開口部より単結晶を成長せしめ、 前記マスクを前記基体より除去し、 酸化処理を前記基体に施し、 前記下地材料側とは反対の成長した単結晶側より研磨す
ることを特徴とする単結晶膜の形成方法が提供される. 本発明は、例えば酸化珪素をマスクとした微小面積の開
口部からの例えばSL単結晶の選択エビタキシャル成長
( S E G : Selective Epita
xialGrowth)及び横方向成長( E L O
 : EpitaxialLateral Overg
rowth)を行ない、成長後にマスクを除去し、さら
に全面酸化することにより、SEG−ELOによる成長
部分を元のStウエハから電気的に分離し得、更に成長
部分を僅かに残すように上面から研磨することによって
、元のSiウエハと同一の面方位を有するSL単結晶膜
を酸化珪素上に形成するのである. [実施態様例] 次に、第1図を用いて本発明の実施態様例を説明する. 第1図(a)において例えば下地材料としてのSiウエ
ハ1の表面を熱酸化し酸化珪素(SiO*)をマスク2
とする.マスクの厚さは第1図(b)に後述するように
、結晶がELOLた際にも成長結晶とStウエハ面の隙
間にエッチャントが入って行?る厚さ、即ち0.1 u
m以上が好ましく、より好ましくは0.5μ層以上であ
る.また、マスク厚の上限としてはマスク材をStウエ
ハの熱酸化によって得る場合、生産性を考慮すると2μ
m程度が適当である.但し、マスク材をStの熱酸化で
なく、CVD法等による堆積によって形成するならばこ
の限りではない。しかし、後に酸化することにより、或
長した結晶とSiウェハの隙間を埋めることを考えるな
らば、上限は4μ一程度である。
[Problems to be Solved by the Invention] As described above, while each of the above conventional examples has excellent features, they also have many problems. Therefore, the purpose of the present invention is to (1) use relatively inexpensive S1 wafers, (2) use common equipment and common processes, and
(2) To provide a Si single-crystal film that is insulated and isolated at any in-plane area, and in which not only the plane orientation but also the in-plane orientation of each region is aligned. [Means and effects for solving the problem] According to the present invention, a substrate in which the surface of a silicon wafer as a base material is exposed through a minute opening of a mask formed on the surface of a silicon wafer is subjected to crystallization or lengthening treatment, and A single crystal is grown on the mask surface from a minute exposed surface, the mask is removed, the substrate is subjected to oxidation treatment, and the substrate subjected to the oxidation treatment is polished from the side of the grown single crystal. A method for forming a single crystal film, a crystalline article obtained by the method, and a substrate having a mask having minute openings and a base material made of a single crystalline material subjected to a crystal growth treatment. , growing a single crystal through the opening, removing the mask from the base, subjecting the base to oxidation treatment, and polishing from the side of the grown single crystal opposite to the base material side. A method for forming a crystalline film is provided. The present invention is directed to selective epitaxial growth (SEG) of, for example, an SL single crystal from an opening with a minute area using, for example, silicon oxide as a mask.
xialGrowth) and lateral growth (E L O
:EpitaxialLateral Overg
After growth, the mask is removed and the entire surface is oxidized to electrically separate the SEG-ELO grown portion from the original St wafer, and the top surface is polished to leave a small portion of the grown portion. By doing this, an SL single crystal film having the same plane orientation as the original Si wafer is formed on the silicon oxide. [Embodiment Example] Next, an embodiment example of the present invention will be explained using FIG. In FIG. 1(a), for example, the surface of a Si wafer 1 as a base material is thermally oxidized and silicon oxide (SiO*) is applied to a mask 2.
Suppose that As will be described later in FIG. 1(b), the thickness of the mask is determined by the fact that etchant may enter the gap between the growing crystal and the St wafer surface even when the crystal is ELOLed. thickness, i.e. 0.1 u
The thickness is preferably 0.5μ or more, more preferably 0.5μ or more. In addition, when the mask material is obtained by thermal oxidation of St wafer, the upper limit of the mask thickness is 2 μm considering productivity.
A value of about m is appropriate. However, this is not the case if the mask material is formed not by thermal oxidation of St but by deposition by CVD or the like. However, if we consider filling the gap between the elongated crystal and the Si wafer by oxidizing it later, the upper limit is about 4μ.

マスク材はフッ酸(HF)溶液のような液体のエッチャ
ントまたはフッ酸ガス等のエッチングガスで容易にエッ
チングできるものであればSiO■でなくてもさしつか
えない。但し成長を行なう際に選択成長が可能なもので
なければならない.例えば、窒化珪素膜は、エッチング
や選択成長に関して、Sin.マスクに比べて不利であ
るが,使用可能である マスク2の一部を開口してウェハ1の微細な表面を露出
するが、開口部の大きさは、直径にして1μm以上4μ
m以下が好ましい。これは開口部がlumφ未満である
と、成長処理を施す際にくずれた結晶が多くなったり、
もしくは成長しない点があったりする傾向があり、4μ
mφを越えると、マスクを除去し全体を酸化して、元の
ウエハ部と新たに成長させたウエハ部を絶縁分離する際
に、完全に分離できなくなることがあるからである。従
ってより好ましくは2μ煙φ±0.5μm程度である.
開口部と開口部の間隔(ピッチ)は、用途に応じて自由
に決定すればよい.即ち、得られる単結晶膜上に素子を
形成するときの素子サイズに合わせて決めれば良い.通
常20μmから100μ閣程度であり、200μ鵬を越
えると結晶成長に多大な時間を要する. Stウエハは(100) , (110) , (11
1)等用途に合わせて決定すればよい.結晶はエビタキ
シャル成長するのでウエハの方位と同じものとなる.第
l図(b)例えばCVD,PVD等の気相法により結晶
成長処理を施しSL結晶3を得る。一般に、?択成長を
行なえるガス系としては、H2をキャリアガスとしてS
iC14,SiHClx,SiH*Clz等のクロロシ
ラン系SiH4,SitHa等のシラン系があり、これ
らにHCI等のエッチングガスを添加してもよい.例え
ば熱CVD法の場合には、圧力は好ましくは数Torr
から250Torr .より好ましくは50Torrか
ら170Torr 、最適には100Torr程度の減
圧下で、また温度は好ましくは850〜1200℃、よ
り好ましくは900〜1050℃程度の範囲の中で行な
われることが多い(最適温度は使用するガスの種類によ
って大きく異なる). 第1図(C)マスク材をウエット法でエッチングする.
例えばマスク材がSiO■であるならエツチャントはフ
ッ酸(HF)溶液とすれば容易に除去できる.第1図(
c)においてマスクを除去して得られた基体4の、その
中で元のウエハそのものをウエハ部分5、ウエハ部分の
上面より更に上方向に形成された部分を成長部分6とす
る。
The mask material does not need to be SiO2 as long as it can be easily etched with a liquid etchant such as a hydrofluoric acid (HF) solution or an etching gas such as a hydrofluoric acid gas. However, when growing, selective growth must be possible. For example, a silicon nitride film has a problem with respect to etching and selective growth. The fine surface of the wafer 1 is exposed by opening a part of the mask 2, which is disadvantageous compared to a mask but can be used, but the size of the opening is 1 μm or more and 4 μm in diameter.
m or less is preferable. This is because if the opening is less than lumφ, many crystals will be broken during the growth process,
Otherwise, there is a tendency for there to be points where it does not grow, and 4μ
This is because if mφ is exceeded, complete separation may not be possible when the mask is removed and the entire wafer is oxidized to insulate and separate the original wafer portion from the newly grown wafer portion. Therefore, it is more preferable that the smoke diameter is about 2μ±0.5μm.
The spacing (pitch) between the openings can be determined freely depending on the application. That is, it can be determined according to the element size when forming an element on the obtained single crystal film. Normally, the crystal size is between 20 μm and 100 μm, and if it exceeds 200 μm, it takes a long time for crystal growth. St wafers are (100), (110), (11
1), etc., should be determined according to the purpose. Since the crystal grows epitaxially, it has the same orientation as the wafer. FIG. 1(b) A crystal growth process is performed by a vapor phase method such as CVD or PVD to obtain an SL crystal 3. in general,? A gas system that allows selective growth is S using H2 as a carrier gas.
There are chlorosilanes such as iC14, SiHClx, and SiH*Clz, and silanes such as SiH4 and SitHa, to which an etching gas such as HCI may be added. For example, in the case of a thermal CVD method, the pressure is preferably several Torr.
From 250 Torr. It is often carried out under reduced pressure, more preferably from 50 Torr to 170 Torr, optimally about 100 Torr, and at a temperature preferably in the range of 850 to 1200°C, more preferably in the range of 900 to 1050°C (the optimum temperature depends on the temperature used). (Varies greatly depending on the type of gas used.) Figure 1 (C) The mask material is etched using the wet method.
For example, if the mask material is SiO2, the etchant can be easily removed using a hydrofluoric acid (HF) solution. Figure 1 (
In the base body 4 obtained by removing the mask in c), the original wafer itself is referred to as a wafer portion 5, and the portion formed further above the upper surface of the wafer portion is referred to as a growth portion 6.

第1図(d)基体4を熱酸化処理し、S1酸化物7を得
る.この酸化処理は成長部分6のうち、元のマスク開口
部分に相当する部分が全て酸化され、ウエハ部分と成長
部分が完全に絶縁分離されるところまで行なうのが望ま
しい. 第1図(e)成長部分6の上方側から研磨を行なう。こ
の研磨は通常のウエハ研磨プロセスと同様に行なえばよ
い。研磨は戊長部分のSL結晶3の層が露出した後、S
L層が消失するまでの所望のSi膜厚を残して止めれば
よい。
FIG. 1(d) The substrate 4 is thermally oxidized to obtain an S1 oxide 7. It is desirable that this oxidation treatment be carried out until all portions of the growth portion 6 corresponding to the original mask openings are oxidized and the wafer portion and the growth portion are completely insulated and isolated. FIG. 1(e) Polishing is performed from the upper side of the growth portion 6. This polishing may be performed in the same manner as a normal wafer polishing process. Polishing is carried out after the layer of SL crystal 3 in the long part is exposed.
It is only necessary to leave a desired Si film thickness until the L layer disappears.

[実施例] 以下、本発明を図面を用いて実施例により説明する。[Example] Hereinafter, the present invention will be explained by examples using the drawings.

実施例1 本実施例では第1図乃至第3図を用いる。Example 1 In this embodiment, FIGS. 1 to 3 are used.

1.まず(100)方位の4インチSiウエハを用意し
た.このSiウエハをos+oa雰囲気中において、そ
の表面を1.2μm酸化した。
1. First, a 4-inch Si wafer with a (100) orientation was prepared. The surface of this Si wafer was oxidized to a thickness of 1.2 μm in an OS+OA atmosphere.

次に第2図に示すように開口部として微小な正方形の領
域(以後「窓」と呼ぶ)を格子点上にパターニングした
.このとき正方形の一辺の大きさ(第2図のaの値)を
2.0μmとし、窓と窓の間?(同bの値)が縦横それ
ぞれ50μmになるようにした.そしてこの窓の部分の
SiO■を稀フッ酸溶液でエッチングし、第1図(a)
に示すようなマスク付Siウエハを形成した. 2.次に前記マスク付Siウエハに選択エビタキシャル
成長(SEG)処理を施した.このときの条件は次のと
おりである. ガス種 SiHa(:1g/HCI/H.ガス流量  
0.53/1.9/100 (J2/min)温   
度   1030℃ 圧   力   100 Torr 成長時間  80分 その結果、第1図(b)のような結晶が成長した。これ
をウエハ上方から見ると、第3図のようになる。第3図
はbの大きさが窓と窓の間隔と同じ50μmであり、上
部には(311)面に囲まれた特徴的な正四角錐の構造
が観察された。また上記条件で成長を行なうと、隣り同
士の成長結晶は底辺でぶつかり合っているのだが、結晶
の四すみには「ボイド」と呼ばれる、対角線長約20L
LLIlの?し形の空隙が残った。即ちこの部分には成
長したSi結晶が無く、マスクであるSiO■表面が露
出している。
Next, as shown in Figure 2, tiny square areas (hereinafter referred to as ``windows'') as openings were patterned on the lattice points. At this time, the size of one side of the square (the value of a in Figure 2) is 2.0 μm, and the space between the windows? (The value of b) was set to 50 μm in both the vertical and horizontal directions. Then, the SiO■ in this window area was etched with a dilute hydrofluoric acid solution, as shown in Figure 1(a).
A Si wafer with a mask was formed as shown in the figure. 2. Next, the masked Si wafer was subjected to selective epitaxial growth (SEG) treatment. The conditions at this time are as follows. Gas type SiHa (: 1g/HCI/H. Gas flow rate
0.53/1.9/100 (J2/min) temperature
Temperature: 1030° C. Pressure: 100 Torr Growth time: 80 minutes As a result, crystals as shown in FIG. 1(b) were grown. When viewed from above the wafer, it looks like FIG. 3. In FIG. 3, the size of b is 50 μm, which is the same as the interval between windows, and a characteristic square pyramid structure surrounded by (311) planes was observed at the top. Furthermore, when growing under the above conditions, adjacent growing crystals collide with each other at the bottom, but there are "voids" in the four corners of the crystals with a diagonal length of approximately 20 L.
LLIl's? A square-shaped void remained. That is, there is no grown Si crystal in this part, and the surface of the SiO2 mask is exposed.

3.次に前記結晶成長処理を施したウエハを濃フッ酸溶
液に20時間浸してマスクをエッチングし、第1図(c
)のような基体を得た。
3. Next, the wafer subjected to the crystal growth process was immersed in a concentrated hydrofluoric acid solution for 20 hours to etch the mask.
) was obtained.

4.この基板をH2+0■雰囲気中に置き、最初にマス
クを形成したときと同じ条件にて酸化したところ、第1
図(d)のように、成長部分のSLがウエハ部分のSL
と完全にSiO■によって分離されたS1島が形成され
た.尚、隣同士の結晶は、その底辺でぶつかり合ってい
たが、その接触面積が小さいことと、接触面が他よりも
多く(速く)酸化されたことにより、第1図(d)のよ
うに、成長結晶同士も完全に絶縁分離されていた. 5.次に前記酸化処理を施した基体を成長結晶の上面か
ら、通常のウエハ研磨工程、即ち、砥粒を用いたメカニ
カルボリシング(ラツピング)で、研磨し、更にケミカ
ルボリシングで鏡面仕上げを行ない、第1図(e)のよ
うな縦横約50X50μ1、厚さ0.5μmの単結晶S
L薄膜を得た。
4. This substrate was placed in an H2+0■ atmosphere and oxidized under the same conditions as when the mask was first formed.
As shown in figure (d), the SL of the growth part is the SL of the wafer part.
An S1 island completely separated by SiO■ was formed. Incidentally, adjacent crystals collided with each other at their bases, but because the contact area was small and the contact surface was oxidized more (faster) than the others, the crystals were oxidized as shown in Figure 1 (d). , the grown crystals were completely isolated from each other. 5. Next, the substrate subjected to the oxidation treatment is polished from the top surface of the grown crystal using a normal wafer polishing process, that is, mechanical boring (lapping) using abrasive grains, and then mirror-finished using chemical boring. A single crystal S with a length and width of about 50×50μ1 and a thickness of 0.5μm as shown in Figure 1(e)
An L thin film was obtained.

実施例2 本実施例では第1図乃至第5図を用いる。Example 2 In this embodiment, FIGS. 1 to 5 are used.

1.まず(ill)方位の5インチウエハを用意し、そ
の表面を1.5μm酸化した。第2図に示すように、酸
化膜に窓となる部分をパターニングする。
1. First, a 5-inch wafer with the (ill) orientation was prepared, and its surface was oxidized to a thickness of 1.5 μm. As shown in FIG. 2, the oxide film is patterned to form a window.

但し、窓の形は円形とし、その直径は2μmとした。ま
た窓と窓の間隔を30ufl+とした。バターニング後
に実施例1と同様に稀フッ酸で窓の部分をエッチングし
・、第1図(a)のようなマスク付きウエハを得た. 2.次に前記ウエハに選択エビタキシャル成長処理を施
した.条件は次のとおりである.ガス種 SiH*(:
lx/HCI/Haガス流量  0.53/2.5/1
00 (I2/min)温   度   990℃ 圧   力   100 Torr 成長時間  90分 この成長の初期を観察すると、(111)ウエハのSE
Gは、第4図の様な表面の平坦な六角形の結晶が成長し
た.同図において21はSiウエハ、22はマスク(S
ins)である。そのまま成長を続けると、第5図の様
に表面が平坦のまま結晶同士が衝突した.このとき上面
から観察してみたところ、第3図と同じ様なひし形のボ
イドがやはり形成されていた.このボイドの大きさは対
角線長で約10μmだった。
However, the shape of the window was circular, and its diameter was 2 μm. In addition, the interval between windows was set to 30ufl+. After patterning, the window portion was etched with dilute hydrofluoric acid in the same manner as in Example 1 to obtain a wafer with a mask as shown in Figure 1(a). 2. Next, the wafer was subjected to selective epitaxial growth treatment. The conditions are as follows. Gas type SiH*(:
lx/HCI/Ha gas flow rate 0.53/2.5/1
00 (I2/min) Temperature: 990°C Pressure: 100 Torr Growth time: 90 minutes Observing the initial stage of this growth, the SE of the (111) wafer
G grew a hexagonal crystal with a flat surface as shown in Figure 4. In the figure, 21 is a Si wafer, 22 is a mask (S
ins). As the growth continued, the crystals collided with each other while the surface remained flat, as shown in Figure 5. At this time, when I observed it from the top, I found that a diamond-shaped void similar to that shown in Figure 3 had also been formed. The size of this void was about 10 μm in diagonal length.

3.次に前記結晶成長処理を施したウエハを濃フッ酸に
20時間浸し、酸化膜のマスクを全て除去した。
3. Next, the wafer subjected to the crystal growth process was immersed in concentrated hydrofluoric acid for 20 hours to completely remove the oxide film mask.

4.次にこの基体をH.:0.=3:2の酸化雰囲気中
に置き、1000℃で8時間酸化処理し(111)面を
1.2μm酸化した。
4. Next, this substrate was :0. It was placed in an oxidizing atmosphere of 3:2 and oxidized at 1000° C. for 8 hours to oxidize the (111) plane by 1.2 μm.

5.次に前記酸化処理を施した基体を、成長結晶の上面
から研磨し、(Ill)面に揃った膜厚0.5μmの単
結晶Si薄膜を得た。
5. Next, the substrate subjected to the oxidation treatment was polished from the top surface of the grown crystal to obtain a single crystal Si thin film with a thickness of 0.5 μm and aligned with the (Ill) plane.

[発明の効果] 以上説明したように、SiウエハのSEGを利用し、そ
の窓の大きさ、マスクの厚さ、窓と窓のピッチ等を適切
な値にすることと、マスクを完全に除去することと、全
体を適切な量だけ酸化することと、結晶を適切な量だけ
研磨するという一連の工程を行なうことによって、比較
的大面積に分離され方位が完全に揃った単結晶Si膜を
得ることができるようになった.しかも本発明の方法を
用いるならば、同じ様にStow上又は他の非品質絶縁
物上に単結晶SL膜を形成するSOSやSIMOXより
もはるかに安価で容易に単結晶膜が得られ、しかも素子
形成時に必ず必要となる素子分離を本発明の工程上自動
的に行ない、しかも、素子分離幅が小さくてすむので、
電子素子等の高集積化に有利であるという、多くのメリ
ットをもたらしている. また、膜の結晶性も極めて良好であり、SOS%SIM
OX、レーザー溶融結晶と比べて同等以上である.
[Effects of the invention] As explained above, by using SEG of Si wafer, it is possible to set the window size, mask thickness, pitch between windows, etc. to appropriate values, and to completely remove the mask. By performing a series of steps including oxidizing the whole by an appropriate amount, and polishing the crystal by an appropriate amount, a single crystal Si film separated into a relatively large area and with perfectly aligned orientations can be created. Now you can get it. Moreover, if the method of the present invention is used, a single crystal SL film can be obtained easily and at a much lower cost than SOS or SIMOX, which similarly form a single crystal SL film on Stow or other non-quality insulators. Since element isolation, which is always necessary during element formation, is automatically performed in the process of the present invention, and the element isolation width can be small,
It has many advantages, including the ability to increase the degree of integration of electronic devices. In addition, the crystallinity of the film is extremely good, and SOS%SIM
OX, it is equivalent or better than laser melted crystal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の単結晶膜の形成方法を示す工程図、 第2図はマスクの開口部のパターン例、第3図は(10
0)結晶のSEGを実行したときの成長結晶を示す図、 第4図及び第5図は(111)結晶のSEGを実行した
ときの結晶成長を示す図であり、第4図は初期の結晶で
あり、第5図は成長結晶である。
Fig. 1 is a process diagram showing the method of forming a single crystal film of the present invention, Fig. 2 is an example of a pattern of a mask opening, and Fig. 3 is a (10
0) A diagram showing a grown crystal when performing SEG of a crystal. Figures 4 and 5 are diagrams showing crystal growth when performing SEG of a (111) crystal. Figure 4 shows an initial crystal. FIG. 5 shows a grown crystal.

Claims (1)

【特許請求の範囲】 1、シリコンウェハ表面に形成されたマスクの微小な開
口部より、下地材料のシリコンウェハ表面を露出させた
基体に結晶成長処理を施し、前記微小な露出面より前記
マスク面上に単結晶を成長せしめ、 マスクを除去し、該基体に酸化処理を施し、前記酸化処
理を施した基体を、成長した単結晶側から研磨を行なう
ことを特徴とする単結晶膜の形成方法。 2、請求項1の方法により得られた結晶物品。 3、微小な開口部を有するマスクと、単結晶性材料から
なる下地材料と、を有する基体に結晶成長処理を施し、
前記開口部より単結晶を成長せしめ、 前記マスクを前記基体より除去し、 酸化処理を前記基体に施し、 前記下地材料側とは反対の成長した単結晶側より研磨す
ることを特徴とする単結晶膜の形成方法。 4、前記結晶成長処理は気相法である請求項1及び3の
単結晶膜の形成方法。 5、前記マスクは酸化珪素膜である請求項1及び3の単
結晶膜の形成方法。 6、前記マスクの厚さは0.1μm以上4μm以下であ
る請求項1及び3の単結晶膜の形成方法。
[Claims] 1. A crystal growth process is performed on a substrate in which the surface of the silicon wafer as a base material is exposed through a minute opening of a mask formed on the surface of the silicon wafer, and the mask surface is grown from the minute exposed surface. A method for forming a single crystal film, which comprises growing a single crystal thereon, removing the mask, subjecting the substrate to oxidation treatment, and polishing the oxidized substrate from the side of the grown single crystal. . 2. A crystal article obtained by the method of claim 1. 3. Performing crystal growth treatment on a substrate having a mask having minute openings and a base material made of a single crystalline material,
A single crystal characterized in that: a single crystal is grown through the opening, the mask is removed from the base, oxidation treatment is performed on the base, and the grown single crystal is polished from the side opposite to the base material side. How to form a film. 4. The method for forming a single crystal film according to claims 1 and 3, wherein the crystal growth treatment is a vapor phase method. 5. The method of forming a single crystal film according to claims 1 and 3, wherein the mask is a silicon oxide film. 6. The method of forming a single crystal film according to claims 1 and 3, wherein the thickness of the mask is 0.1 μm or more and 4 μm or less.
JP15834989A 1989-06-22 1989-06-22 Forming method of single crystal film and crystal products Pending JPH0324719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15834989A JPH0324719A (en) 1989-06-22 1989-06-22 Forming method of single crystal film and crystal products

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15834989A JPH0324719A (en) 1989-06-22 1989-06-22 Forming method of single crystal film and crystal products

Publications (1)

Publication Number Publication Date
JPH0324719A true JPH0324719A (en) 1991-02-01

Family

ID=15669707

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5686343A (en) * 1992-12-22 1997-11-11 Goldstar Electron Co. Ltd. Process for isolating a semiconductor layer on an insulator
US6121121A (en) * 1997-11-07 2000-09-19 Toyoda Gosei Co., Ltd Method for manufacturing gallium nitride compound semiconductor
US6580098B1 (en) 1999-07-27 2003-06-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US7619261B2 (en) 2000-08-07 2009-11-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5686343A (en) * 1992-12-22 1997-11-11 Goldstar Electron Co. Ltd. Process for isolating a semiconductor layer on an insulator
DE4341180B4 (en) * 1992-12-22 2006-07-27 Lg Semicon Co. Ltd., Cheongju Method of insulating a semiconductor layer on an insulator to define an active region
US6121121A (en) * 1997-11-07 2000-09-19 Toyoda Gosei Co., Ltd Method for manufacturing gallium nitride compound semiconductor
US6580098B1 (en) 1999-07-27 2003-06-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US6818926B2 (en) 1999-07-27 2004-11-16 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US6835966B2 (en) 1999-07-27 2004-12-28 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US6893945B2 (en) 1999-07-27 2005-05-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride group compound semiconductor
US6930329B2 (en) 1999-07-27 2005-08-16 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US7176497B2 (en) 1999-07-27 2007-02-13 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor
US7619261B2 (en) 2000-08-07 2009-11-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor

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