JPS61144037A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS61144037A
JPS61144037A JP26675784A JP26675784A JPS61144037A JP S61144037 A JPS61144037 A JP S61144037A JP 26675784 A JP26675784 A JP 26675784A JP 26675784 A JP26675784 A JP 26675784A JP S61144037 A JPS61144037 A JP S61144037A
Authority
JP
Japan
Prior art keywords
layer
adhesive
semiconductor device
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26675784A
Other languages
Japanese (ja)
Inventor
Tsuneo Hamaguchi
恒夫 濱口
Masakazu Kimura
正和 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26675784A priority Critical patent/JPS61144037A/en
Publication of JPS61144037A publication Critical patent/JPS61144037A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a device having good heat conductivity and crystallinity uniformly over a large area with a desirable yield, by providing a three-layer insulation film consisting of an insulation layer having a lower heat conductivity, a diamond layer and an adhesive layer while depositing these layers in that order from an element forming layer toward a substrate. CONSTITUTION:An insulation layer 14 of silicon dioxide for example is provided on the polished surface of an element forming layer by the CVD or spattering process at a temperature lower than the melting point of an adhesive 13. Further, a diamond layer 15 is formed thereon to 2mum thick by the glow discharge process for example. The diamond layer 15 is then bonded to a support substrate 17 of ceramics such as alumina nitride with an adhesive 16 of a epoxy or polyimide resin for example. The support substrate 17 is the removed by grinding or etching. Finally, the adhesive 16 is removed with an appropriate solvent. Thus, the diamond layer 15 provides good heat dissipating properties and the insulation film 14 assures that no impurity is included in the element forming layer 12.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は訪電体で分離された集積回路の構造を有する半
導体装置およびその製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having an integrated circuit structure separated by a current-visitor, and a method for manufacturing the same.

−(従来技術) 従来この種の半導体装よびその製造方法としてサファイ
ア(A40s)またはスピネル(MgAJt Oa)等
の絶縁物上に単結晶シリコンをエピタキシャル成長させ
、そのエピタキシャル層に素子を形成する製造方法で形
成された半導体装置がある。しかし、サファイアまたは
スピネル上にエピタキシャル成長されたシリコン単結晶
の単結晶性が悪いためサファイアまたはスピネルとシリ
コンとの界面に大きなリーク電流が流れて、消費電力が
予想外に大きくなったり、移動度が半導体単結晶のそれ
より低いため、予想はどには高速にならない、あるいは
へテロエピタキシャル成長をさせるため歩留りが悪いと
いう欠点がありしかも大面積に高品質な結晶が得られな
い欠点がある。
- (Prior art) Conventionally, as this type of semiconductor device and its manufacturing method, single crystal silicon is epitaxially grown on an insulator such as sapphire (A40s) or spinel (MgAJt Oa), and elements are formed in the epitaxial layer. There is a semiconductor device formed therein. However, due to the poor single crystallinity of the silicon single crystal epitaxially grown on sapphire or spinel, a large leakage current flows at the interface between sapphire or spinel and silicon, resulting in unexpectedly high power consumption and the mobility of semiconductors. Since it is lower than that of a single crystal, it has the disadvantage that it does not reach the expected high speed, or that the yield is low because it uses heteroepitaxial growth, and it also has the disadvantage that high quality crystals cannot be obtained over a large area.

(発明の目的) 本発明はこれらの欠点を除去せしめ、さらに熱伝導の良
好にして絶縁体上に結晶性の良好なデバイスを大面積に
わたって均一に歩留り良く得ることを目的としている。
(Objectives of the Invention) The present invention aims to eliminate these drawbacks, and to obtain devices with good heat conduction and good crystallinity on an insulator uniformly over a large area with a high yield.

(発明の構成) 本発明によれば支持基板上に絶縁層を介して半導体素子
形成層が設けられた半導体装置において、前記絶縁層と
して前記素子形成層から前記基板へ向かって熱伝導度の
低い絶縁層ダイアモンド層、接着剤層の順に111t、
rrI4された3層を備えていることを特徴とする半導
体装置が得られる。
(Structure of the Invention) According to the present invention, in a semiconductor device in which a semiconductor element forming layer is provided on a supporting substrate via an insulating layer, the insulating layer has low thermal conductivity from the element forming layer toward the substrate. 111t in the order of the insulating layer diamond layer and the adhesive layer,
A semiconductor device characterized in that it includes three rrI4 layers is obtained.

更に本発明によれば半導体単結晶基板上に素子分離領域
を設け、半導体部分に素子を形成した後、前記半導体装
置形成面を接着剤で保持基板に接着し、前記半導体単結
晶基板を裏面から研磨しながら除去して前記半導体装置
が形成された層を残し、次いで除去した面に前記接着剤
の融点より低い温度で熱伝導度の低い絶縁膜を堆積した
後、ダイアモンド層を形成し、この面を接着剤を介して
支持基板に固定し、次いで前記保持基板を除去すること
を特徴とする半導体装置の製造方法が得られる。
Further, according to the present invention, after providing an element isolation region on a semiconductor single crystal substrate and forming an element in the semiconductor portion, the semiconductor device forming surface is adhered to a holding substrate with an adhesive, and the semiconductor single crystal substrate is attached from the back side. The layer on which the semiconductor device is formed is removed while being polished, and then an insulating film with low thermal conductivity is deposited on the removed surface at a temperature lower than the melting point of the adhesive, and then a diamond layer is formed on this layer. A method for manufacturing a semiconductor device is obtained, which comprises fixing the surface to a support substrate via an adhesive, and then removing the holding substrate.

ダイアモンドの熱彰張係数は8iに近いためデバイス層
の変形が少なく熱伝導率はSiより約4倍良好なため、
ダイアモンド層をデバイス下面に用いることはデバイス
層で発生する熱の放散が良好になる効果を有し、ダイア
モンド層とデバイス層間の絶縁層はダイアモンド層に含
まれる不純物がデバイス層に導入されるのを防ぐ効果を
有する。
Since the thermal tensile coefficient of diamond is close to 8i, there is little deformation of the device layer, and the thermal conductivity is about 4 times better than that of Si.
Using a diamond layer on the bottom surface of the device has the effect of improving the dissipation of heat generated in the device layer, and the insulating layer between the diamond layer and the device layer prevents impurities contained in the diamond layer from being introduced into the device layer. It has a preventive effect.

(実施例) 次に図面lこ基づき本発明の半導体装置およびその製造
方法の一実施例について説明する。
(Example) Next, an example of a semiconductor device and a method for manufacturing the same according to the present invention will be described based on drawings.

半導体としてシリコンを用いた場合について述べる。The case where silicon is used as the semiconductor will be described.

第1図は本発明によって得られた半導体装置を示し、第
2図は、その製造方法を示す。
FIG. 1 shows a semiconductor device obtained by the present invention, and FIG. 2 shows a manufacturing method thereof.

第2図(a)から1!帽こ、第1図に示す半導体装置を
得る方法を説明する。単結晶シリコン基板1の表面に二
酸化シリコン(SfO,)膜2を形成し、次に写真食刻
法特にドライエツチング等の微細加工技術を用いて、上
記8 ion膜2の所望の領域を除去し、残りの部分の
8i01膜2をマスクとして、第1図に示すごとく基板
に所望の深さと垂直形状を有する溝3をドライエツチン
グ法により形成する。
From Figure 2(a) 1! Now, a method for obtaining the semiconductor device shown in FIG. 1 will be explained. A silicon dioxide (SfO,) film 2 is formed on the surface of a single-crystal silicon substrate 1, and then a desired region of the 8 ion film 2 is removed using a microfabrication technique such as photolithography, particularly dry etching. Using the remaining 8i01 film 2 as a mask, a groove 3 having a desired depth and vertical shape is formed in the substrate by dry etching as shown in FIG.

この溝は素子の分離領域となるため分離溝幅を微細にす
るほど、素子の集積度は向上する。
Since this groove becomes an isolation region for the elements, the finer the width of the isolation groove, the higher the degree of integration of the elements.

次に、上記マスクとして用いた8i02膜2を除去して
、再度二酸化シリコン2aとシリコレ窒化膜2bを基板
全面に形成する。かかる図を第2図(b)に示す。
Next, the 8i02 film 2 used as the mask is removed, and silicon dioxide 2a and silicon nitride film 2b are again formed over the entire surface of the substrate. Such a diagram is shown in FIG. 2(b).

次に多結晶シリコン4を気相成長法により、分離溝3の
深さ以上の厚みに成長させて、分離溝3を埋め、通常の
ポリシング法等により表面を平担にし、その後シリコン
窒化膜2bをマスクとして、熱酸化を施すことにより、
分離溝内に埋めこまれた多結晶シリコン4の表面のみに
酸化膜2cが形成される。
Next, polycrystalline silicon 4 is grown to a thickness equal to or greater than the depth of the isolation trench 3 using a vapor phase growth method, filling the isolation trench 3, and making the surface flat by a normal polishing method, etc., followed by silicon nitride film 2b. By using thermal oxidation as a mask,
Oxide film 2c is formed only on the surface of polycrystalline silicon 4 buried in the isolation trench.

次に素子形成工程に入る。第2図(C)に続いて、溝3
の中に埋め込まれた部分以外のシリコン窒化膜2bと酸
化膜2aを除去した丸改めて所望の厚さのゲート酸化膜
5を熱酸化法で形成し、次に多結晶シリコンでゲート電
極6を形成する。
Next, the device formation process begins. Following Fig. 2(C), groove 3
After removing the silicon nitride film 2b and oxide film 2a other than the part buried in the gate oxide film 5, a new gate oxide film 5 of a desired thickness is formed by thermal oxidation, and then a gate electrode 6 is formed using polycrystalline silicon. do.

ゲート電極6をマスクにして、イオン注入法により、ソ
ース領域7およびドレイン領域8を形成し、その後例え
ばリンガラスのような層間絶縁膜9をCVD法で堆積し
た後、”コンタクトホールを形成し、アルミ配線】0を
形成すると第2図(d)が得られ、MO8集積回路の素
子が形成できる。次に素子形成面とシリコンウェハ等の
保持基板12を接着剤13例えばポリイミド等の樹脂で
接着し、素子形成面を除く単結晶シリコン基板1をメカ
ノケミカルボリジングで除去する。前記メカノケミカル
ボリジングでは砥粒としてコロイダルシリカ化学液とし
て有機アンモニアを用いているため分離溝3を被覆して
いる二酸化シリコン2aは単結晶シリコンよりも加工速
度が1150以下とかなり小さいため、ボリシング加工
を溝の深さで止めることができ、素子形成面を容易に残
すことができる。かかる図を第2図(e)に示す。
Using the gate electrode 6 as a mask, a source region 7 and a drain region 8 are formed by ion implantation, and then an interlayer insulating film 9 such as phosphorus glass is deposited by CVD, and then a contact hole is formed. 2(d) is obtained, and an element of an MO8 integrated circuit can be formed. Next, the element forming surface and a holding substrate 12 such as a silicon wafer are bonded together with an adhesive 13 such as a resin such as polyimide. Then, the single-crystal silicon substrate 1 excluding the element forming surface is removed by mechanochemical boring.In the mechanochemical boring, organic ammonia is used as a colloidal silica chemical solution as abrasive grains, so that the separation groove 3 is covered. Since the processing speed of silicon dioxide 2a is considerably lower than that of single-crystal silicon at 1150 Hz or less, the boring process can be stopped at the depth of the groove, and the element forming surface can be easily left.Such a diagram is shown in FIG. Shown in e).

次に素子形成層のポリシング面に接着剤13の融点より
低い温度でCVD法またはスパッター法で絶縁膜14例
えば二酸化シリコン等を形成し、次に前記ダイアモンド
層15を接着剤16たとえばエポキシ系またはポリイミ
ド系樹脂で支持基板17例えば窒化アルミナなどのセラ
ミックス基板に接着固定し、次に保持基板12を研磨も
しくはエツチングによって除去する。最後に適切な溶剤
たとえば塩化メチレンやトリクロルエチレンを用いて接
着剤16を除去する。このようにして第1図に示す半導
体装置が得られる。
Next, an insulating film 14 such as silicon dioxide is formed on the polished surface of the element forming layer by CVD or sputtering at a temperature lower than the melting point of the adhesive 13, and then the diamond layer 15 is coated with an adhesive 16 such as epoxy or polyimide. The supporting substrate 17 is adhesively fixed to a ceramic substrate such as alumina nitride using resin, and then the holding substrate 12 is removed by polishing or etching. Finally, adhesive 16 is removed using a suitable solvent such as methylene chloride or trichloroethylene. In this way, the semiconductor device shown in FIG. 1 is obtained.

以上説明したように、本発明によれば良好な結晶性を有
する半導体層を容易に絶縁体上に形成することができる
とともに、ダイアモンド層15により熱発散が良好であ
り、絶縁膜14により素子形成層12は不純物の混入が
ない。
As explained above, according to the present invention, a semiconductor layer having good crystallinity can be easily formed on an insulator, heat dissipation is good due to the diamond layer 15, and elements are formed using the insulating film 14. Layer 12 is free of impurities.

また素子形成層の厚みは分離溝の深さにより自在に変え
ることができる。
Further, the thickness of the element forming layer can be freely changed by changing the depth of the separation groove.

実施例において、MO8集積回路の形成を例にあげたが
バイポーラ型集積回路等の他の種類の素子についても同
様に作ることができる。さらに実施例ではシリコン基板
について述べたが、他の半導体単結晶基板たとえば砒化
ガリウムやインジウムリンについても本発明を用いるこ
とができる。
In the embodiments, the formation of an MO8 integrated circuit is taken as an example, but other types of devices such as bipolar integrated circuits can be formed in the same manner. Furthermore, although a silicon substrate has been described in the embodiment, the present invention can also be applied to other semiconductor single crystal substrates such as gallium arsenide and indium phosphide.

また素子分離法としてはLOCO8法やその変形など絶
縁物で素子分離する方法であれば用いることができる。
Further, as the element isolation method, any method that isolates elements using an insulator, such as the LOCO8 method or a modification thereof, can be used.

(発明の効果) 本発明によれば害虫容量が非常に小さいという80 I
 (5ilicon  on  In5ulator)
構造の利点をそのまま維持しながら、さらにダイアモン
ド層による熱放散特に多層の80Iにしたときの熱伝導
性を向上させ、また絶縁膜により素子層への不純物の混
入等を阻止するもので、しかも従来のSOI構造のリー
ク電流、移動度等の結晶性の悪さからくる欠点を改善す
ることができ、素子の低消費電力化、高速動作集積度の
向上環と、そのような素子を大面積に歩留り良く得るこ
とができる。
(Effect of the invention) According to the present invention, the pest capacity is extremely small.
(5ilicon on In5ulator)
While maintaining the advantages of the structure, the diamond layer improves heat dissipation, especially the thermal conductivity when using a multilayer 80I, and the insulating film prevents impurities from entering the element layer. It is possible to improve the defects caused by poor crystallinity such as leakage current and mobility of the SOI structure of the SOI structure, reduce power consumption of the device, improve high-speed operation, and increase the yield of such devices in a large area. You can get a good deal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体装置の一実施例の模式第2図(
a)〜(f)は本発明の製造方法を説明するための断面
図である。 1・・・単結晶シリコン基板、 2.2a、2c・・・二酸化シリコン膜、2b・・・シ
リコン窒化膜、 3・・溝、      4・・・多結晶シリコン、5・
・・ゲート酸化膜、 6・・・ゲート電極、7・・・y
−ス、8・・・ドレイン、9・・・層間絶縁膜、10・
・・アルミ配線、12・・・保持基板、13・・・接着
剤、   14・・・絶縁膜、15・・・ダイアモンド
層、16・・・接着剤、17・・・支持基板、
FIG. 1 is a schematic diagram of an embodiment of the semiconductor device of the present invention (
a) to (f) are cross-sectional views for explaining the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... Single crystal silicon substrate, 2.2a, 2c... Silicon dioxide film, 2b... Silicon nitride film, 3... Groove, 4... Polycrystalline silicon, 5...
...Gate oxide film, 6...Gate electrode, 7...y
- source, 8... drain, 9... interlayer insulating film, 10...
... Aluminum wiring, 12... Holding substrate, 13... Adhesive, 14... Insulating film, 15... Diamond layer, 16... Adhesive, 17... Supporting substrate,

Claims (1)

【特許請求の範囲】 1、支持基板上に絶縁層を介して半導体素子形成層が設
けられた半導体装置において、前記絶縁層として前記素
子形成層から前記基板へ向かって熱伝導度の低い絶縁層
ダイアモンド層、接着剤層の順に積層された3層を備え
ていることを特徴とする半導体装置。 2、半導体単結晶基板上に素子分離領域を設け、半導体
部分に素子を形成した後、前記半導体装置形成面を接着
剤で保持基板に接着し、前記半導体単結晶基板を裏面か
ら研磨しながら除去して前記半導体装置が形成された層
を残し、次いで除去した面に前記接着剤の融点より低い
温度で熱伝導度の低い絶縁膜を堆積した後、ダイアモン
ド層を形成し、この面を接着剤を介して支持基板に固定
し、次いで前記保持基板を除去することを特徴とする半
導体装置の製造方法。
[Claims] 1. In a semiconductor device in which a semiconductor element formation layer is provided on a supporting substrate via an insulating layer, an insulating layer having low thermal conductivity from the element formation layer toward the substrate as the insulating layer. A semiconductor device comprising three layers stacked in this order: a diamond layer and an adhesive layer. 2. After providing an element isolation region on a semiconductor single crystal substrate and forming an element in the semiconductor portion, the semiconductor device forming surface is bonded to a holding substrate with an adhesive, and the semiconductor single crystal substrate is removed while being polished from the back side. to leave the layer on which the semiconductor device was formed, and then deposit an insulating film with low thermal conductivity on the removed surface at a temperature lower than the melting point of the adhesive, form a diamond layer, and cover this surface with the adhesive. 1. A method of manufacturing a semiconductor device, which comprises fixing the semiconductor device to a support substrate via a support substrate, and then removing the holding substrate.
JP26675784A 1984-12-18 1984-12-18 Semiconductor device and manufacture thereof Pending JPS61144037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26675784A JPS61144037A (en) 1984-12-18 1984-12-18 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26675784A JPS61144037A (en) 1984-12-18 1984-12-18 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61144037A true JPS61144037A (en) 1986-07-01

Family

ID=17435282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26675784A Pending JPS61144037A (en) 1984-12-18 1984-12-18 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61144037A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242711A (en) * 1991-08-16 1993-09-07 Rockwell International Corp. Nucleation control of diamond films by microlithographic patterning
WO2013067572A1 (en) * 2011-11-07 2013-05-16 The Silanna Group Pty Ltd A semiconductor-on-insulator structure and process for producing same
EP3203507A1 (en) * 2016-02-04 2017-08-09 Semiconductor Manufacturing International Corporation (Shanghai) Semiconductor structure and fabrication method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242711A (en) * 1991-08-16 1993-09-07 Rockwell International Corp. Nucleation control of diamond films by microlithographic patterning
US5334342A (en) * 1991-08-16 1994-08-02 Rockwell International Corporation Method of fabricating of diamond moth-eye surface
WO2013067572A1 (en) * 2011-11-07 2013-05-16 The Silanna Group Pty Ltd A semiconductor-on-insulator structure and process for producing same
EP3203507A1 (en) * 2016-02-04 2017-08-09 Semiconductor Manufacturing International Corporation (Shanghai) Semiconductor structure and fabrication method thereof
US9917030B2 (en) 2016-02-04 2018-03-13 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof

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