JPH10223870A - Wafer for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To do away with problems of heating resulting from realizing a high integration degree and high speed and signal propagation delay by forming a semiconductor Si layer on a high electric resistance substrate having a higher thermal conductivity than that of the semiconductor Si. SOLUTION: A base wafer having a higher thermal conductivity than that of Si and high electric resistance is used, instead of a Si wafer. In the case an Si wafer 21 is adhered to e.g. a SiC wafer 20, SiC is deposited on a graphite substrate formed like a wafer by the CVD method and separated to obtain a wafer-shaped SiC substrate. It may be directly polished in the next step to form a mirror surface. After cleaning the mirror-surface finished SiC substrate and Si wafer, the mirror surfaces are bonded and heat treated in an oxidative atmosphere to raise the bond strength. The Si wafer is ground and polished to obtain an Si thin film in the last step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wafer for manufacturing a semiconductor device. More particularly, the present invention relates to a semiconductor device manufacturing wafer capable of high integration and high speed.

[0002]

2. Description of the Related Art As one of semiconductor device manufacturing wafers, SOI (Silicon On Insulato) is used.
r) There is a wafer. An SOI wafer is one in which a semiconductor silicon layer is formed on a substrate or a layer made of an electrical insulator (electrical resistivity is, for example, 10 ¹⁰ Ω · cm or more). Together with its importance. The SOI structure has almost all electrical characteristics superior to those of a bulk wafer that is currently used, except for a negative effect such as a substrate floating effect. As a result, low voltage, low power consumption,
High speed, high integration and simplification of the process can be achieved.

FIG. 5 shows an SO that is currently generally used.
1 shows an example of an I wafer. This SOI wafer has a structure in which a silicon oxide film (SiO ₂ ) 51 is formed on a silicon wafer (bond wafer) 52 to be insulated, and a silicon wafer (base wafer) 50 is attached below the silicon oxide film (SiO ₂ ). Elements such as transistors are formed on the silicon wafer (silicon layer) 52.

[0004]

However, as the degree of integration increases, the following two obstacles become apparent in the conventional SOI structure as described above. One is an increase in the temperature of the silicon layer on which the element is formed, and the other is saturation of high-speed operation.

First, the rise in the temperature of the silicon layer is caused by heat generated from elements such as transistors formed in the silicon layer. Since the silicon that constitutes the base wafer is a good conductor of heat, any heat can be released to the base wafer, but the silicon oxide film interposed between the silicon layer and the base wafer is only an electrical insulator. In addition, it is an extreme insulator against heat. Therefore, if the silicon oxide film is made thinner, the heat generated in the silicon layer can be released to the base wafer, but in that case, there is a problem in electrical insulation.

On the other hand, in order to increase the speed, it is sufficient to increase the current in order to increase the speed of the electronic device. However, when the current increases, heat is generated, which hinders the increase in speed. Further, as the degree of integration increases, the amount of heat generated per area also increases, which is an obstacle to improving characteristics. In addition, the speed of the electrons moving through the fine element is reduced with the increase in the frequency and the charge state of the base wafer. This is the reason why semi-insulating GaAs is promising.

[0007] Higher speed can be obtained by increasing the frequency. At this time, if there is an electric charge in the base wafer, the base wafer is induced by the high frequency, and the energy of the high frequency signal is consumed correspondingly. That is, a delay in the signal propagation speed occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and solves the problem of heat generation and delay in signal propagation speed accompanying high integration and high speed. An object of the present invention is to provide a semiconductor device manufacturing wafer that can be achieved.

[0009]

According to the first aspect of the present invention, there is provided a semiconductor device manufacturing wafer in which a semiconductor silicon layer is formed on a high electrical resistivity substrate having higher thermal conductivity than semiconductor silicon. Here, "high electrical resistivity substrate"
Is a concept including an insulating substrate.

The invention described in claim 2 of the present application provides a semiconductor device manufacturing wafer in which a semiconductor silicon layer is formed on a high electrical resistivity substrate having a higher thermal conductivity than semiconductor silicon via an oxide film.

According to a third aspect of the present invention, there is provided the semiconductor device manufacturing wafer according to the first or second aspect, wherein the high electrical resistivity substrate is a substrate containing SiC or AlN as a main component. Here, the term “having SiC or AlN as a main component” is a concept including both the case of non-doping containing no dopant other than SiC or AlN, and the case of containing a dopant for changing the resistivity in addition. .

[0012] The invention described in claim 4 of the present application is the above-mentioned SiC.
4. The semiconductor device manufacturing wafer according to claim 3, wherein the substrate mainly composed of AlN is a substrate formed by CVD.

Hereinafter, the present invention will be described in detail.

(Selection of Base Wafer) As described above,
In SOI wafers, two obstacles, ie, a heat generation problem and a delay in signal propagation speed, occur with high integration and high speed operation. To solve these two obstacles simultaneously, a silicon wafer is used as a base wafer. Instead, it is conceivable to use an alternative wafer having a higher thermal conductivity than silicon and an electrically high resistance. In addition, the shape must be made of a material that can be substituted for a silicon wafer.

As described above, a substance that can be replaced with a silicon wafer as a base wafer and that can simultaneously solve two obstacles such as heat generation and a delay in signal propagation speed is a substance having an electric resistivity of at least 10 ⁴ Ω · cm or more. Specifically, SiC and AlN are selected. SiC
And AlN have a thermal conductivity more than twice as high as silicon,
It has sufficiently good physical properties as a candidate for a substitute substance. Moreover, SiC has recently been used as a susceptor for 300 mm wafers by chemical vapor deposition (Chemical Vapor).
Deposition: Hereinafter, referred to as “CVD method”. )
As a result, SiC wafers are being mass-produced, and the problems of practical purity and cost can be solved. Since AlN can be manufactured by a sintering method, the manufactured sintered body may be processed into a wafer shape.

(Surface Treatment of Base Wafer) Next, a surface treatment as a process prior to bonding will be described. CV
Since D-SiC is grown on a graphite substrate,
Since there is no step of cutting or lapping or etching silicon wafers into silicon wafers as in silicon, mirror processing can be performed directly. However, since the hardness is high, polishing with diamond abrasive grains is preferable. In the case of silicon, processing damage causes slip dislocations in the heat treatment process and causes deformation of the wafer.
In C, no deformation of the wafer occurs. Therefore, the surface roughness Ra <0.3n required for bonding to the silicon wafer
m is obtained. In addition, in order to obtain a sufficient bond even by heat treatment at a lower temperature (1000 ° C.>), smoothing can be achieved by chemical mechanical polishing (CMP) in order to eliminate scratches caused by diamond abrasive grains. AlN
Similar smoothing is possible for the sintered body.

Even if silicon and SiC or AlN are both sufficiently rough, an OH group is required on the surface of SiC or AlN in order to bond them at room temperature. When the present inventor investigated, as shown in FIG.
When bonding the Si substrate 11 to the SiC substrate 10, S
Since the OH group density on the iC surface is lower than that of silicon but sufficient, it was found that the iC surface can be bonded to silicon or silicon with an oxide film. It was also confirmed that the OH group density was sufficient for the AlN surface. When the SiC or AlN wafer is made into an insulator, silicon with an oxide film is not necessary, but silicon with an oxide film can be used for the purpose of protecting the silicon layer from impurities on the bonding surface. In order to give a sufficient bonding force to this, for example, wet O _{2 for} 2 hours at 1100 ° C.
Heat treatment inside. This heat treatment is possible because the thermal expansion coefficients of silicon and SiC or AlN are very close. If the wafer has a thermal expansion coefficient different from that of silicon such as synthetic quartz or sapphire, the next thinning process becomes complicated as described in, for example, Japanese Patent Application Laid-Open No. Hei 7-130590.

(Thinning of Silicon Layer) In the step of thinning the silicon layer, the following two methods are used. One is to remove silicon by surface grinding to a thickness of about 10 μm with respect to the target thickness of the silicon layer, and finish the remaining 10 μm by polishing. When an ultra-thin silicon layer of about 0.1 μm is obtained, PACE (Plasma A
ssisted Chemical Etching)
Method. This method is a method of thinning by vapor phase etching. For example, as described in JP-A-5-160074, the thickness distribution of a silicon layer to be thinned is measured in advance and the thickness distribution is measured. A map is created, the thick portion is locally thinned by a vapor phase etching method by numerical control, and this operation is repeated as necessary. In the second method, as described in Japanese Patent Application Laid-Open No. 5-211128, hydrogen ions are implanted into a bond wafer to be a silicon layer in advance to a predetermined depth, bonded to a base wafer, and then heat-treated at several hundred degrees Celsius. Peeling occurs and a silicon layer is formed. The remaining bond wafer is polished again and implanted with hydrogen ions, so that it can be repeatedly used for the silicon layer. The heat treatment for increasing the bonding strength in the second method is performed, for example, at 1100 ° C. for about 2 hours after the separation.

[0019]

Next, embodiments of the present invention will be described, but the present invention is not limited to these embodiments.

FIG. 2 shows a first embodiment of the present invention.
In this example, a SiC wafer 2 formed by a CVD method
In this example, the silicon wafer 21 is bonded to the substrate 0.
Specifically, it was manufactured by the following steps.

(Manufacturing process of base wafer) Diameter 100
mm on a graphite substrate in the form of a wafer
A 400 μm-thick SiC was deposited by Method D, and the SiC was separated from the graphite substrate to obtain a wafer-shaped SiC substrate. At this time, the resistivity of the SiC substrate was 10 ⁴ Ω · cm.

(Surface processing step) One surface of the SiC substrate is bonded to a glass plate with wax, and an abrasive containing silica abrasive grains having a particle size of 0.02 μm is used on a polishing table on which a polishing cloth made of urethane is stuck. By polishing the surface by about 2 μm, a mirror surface was produced.

(Laminating Step) After the mirror-polished SiC substrate and a silicon mirror wafer having a diameter of 100 mm and a thickness of 400 μm are washed, the mirror surfaces are bonded together in a clean atmosphere at room temperature to further increase the bonding strength. Therefore, heat treatment was performed at 1100 ° C. for 2 hours in an oxidizing atmosphere. As a result, the resistivity of the SiC substrate increased from the initial value.

(Silicon Layer Thinning Step) The silicon wafer side of the bonded wafer was ground to a thickness of 20 μm by surface grinding, and the surface was further polished by mechanochemical polishing until the silicon layer became about 4 μm thick. . Thereafter, by further processing by the PACE method, a silicon thin film having a thickness of about 0.1 ± 0.01 μm was obtained.

FIG. 3 shows a second embodiment of the present invention.
In this example, a SiC wafer 3 formed by a CVD method is used.
The silicon wafer 31 is bonded after forming a silicon oxide film 32 on the entire surface of the wafer 0. Specifically, it was manufactured by the following steps.

(Base Wafer Manufacturing Process) Diameter 100
mm on a graphite substrate in the form of a wafer
A 400 μm-thick SiC was deposited by Method D, and the SiC was separated from the graphite substrate to obtain a wafer-shaped SiC substrate. At this time, the resistivity of the SiC substrate was 10 ⁴ Ω · cm.

(Surface processing step) One surface of the SiC substrate is bonded to a glass plate with wax, and an abrasive containing silica abrasive grains having a particle size of 0.02 μm is used on a polishing table on which a polishing cloth made of urethane is stuck. By polishing the surface by about 2 μm, a mirror surface was produced. Further, an oxidizing heat treatment at 1000 ° C. for 1 hour was applied to the SiC substrate to form an oxide film on the surface.

(Laminating Step) After the mirror-polished SiC substrate and the silicon mirror wafer having a diameter of 100 mm and a thickness of 400 μm are washed, the mirror surfaces are bonded together in a clean atmosphere at room temperature to further increase the bonding strength. Therefore, heat treatment was performed at 1100 ° C. for 2 hours in an oxidizing atmosphere. As a result, the resistivity of the SiC substrate increased from the initial value.

(Silicon Layer Thinning Step) The silicon wafer side of the bonded wafer was ground to a thickness of 20 μm by surface grinding, and the surface was further polished by mechanochemical polishing until the silicon layer became about 4 μm thick. . Thereafter, by further processing by the PACE method, a silicon thin film having a thickness of about 0.1 ± 0.01 μm was obtained.

FIG. 4 shows a third embodiment of the present invention.
In this example, a SiC wafer 4 formed by a CVD method is used.
In FIG. 2, a silicon wafer 41 having a silicon oxide film 42 formed on the entire surface is bonded. Specifically, it was manufactured by the following steps.

(Manufacturing process of base wafer) diameter 100
mm on a graphite substrate in the form of a wafer
A 400 μm-thick SiC was deposited by Method D, and the SiC was separated from the graphite substrate to obtain a wafer-shaped SiC substrate. At this time, the resistivity of the SiC substrate was 10 ⁴ Ω · cm.

(Surface processing step) One surface of the SiC substrate is bonded to a glass plate with wax, and a polishing agent containing silica abrasive grains having a particle size of 0.02 μm is used on a polishing table on which a polishing cloth made of urethane is stuck. By polishing the surface by about 2 μm, a mirror surface was produced.

(Lamination process) After an oxide film is formed on the surface of a mirror-polished silicon wafer having a diameter of 100 mm and a thickness of 400 μm, it is washed together with a mirror-polished SiC substrate, and the mirror surfaces are bonded together at room temperature under a clean atmosphere. In order to further increase the bonding strength, heat treatment was performed at 1100 ° C. for 2 hours in an oxidizing atmosphere. As a result, the resistivity of the SiC substrate increased from the initial value.

(Silicon Layer Thinning Step) The silicon wafer side of the bonded wafer was ground to a thickness of 20 μm by surface grinding, and the surface was further polished by mechanochemical polishing until the silicon layer became about 4 μm thick. . Thereafter, by further processing by the PACE method, a silicon thin film having a thickness of about 0.1 ± 0.01 μm was obtained.

In the above-described embodiment of the present invention, an example in which CVD-SiC is used for the base wafer has been described. However, even when a base wafer manufactured from a SiC sintered body or an AlN sintered body is used, the same process is performed. Needless to say, the semiconductor device manufacturing wafer of the present invention can be obtained.

[0036]

As described above, according to the present invention, it is possible to provide a wafer for manufacturing a semiconductor device which can solve the problem of heat generation and the delay in signal propagation speed, and can achieve both high speed and high integration at the same time. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing surface states of a base wafer and a bond wafer in the present invention.

FIG. 2 is a schematic sectional view showing a first embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a second embodiment of the present invention.

FIG. 4 is a schematic sectional view showing a third embodiment of the present invention.

FIG. 5 is a schematic sectional view showing an example of a conventional SOI wafer.

[Description of sign]

 10, 30, 40 SiC wafer 11, 31, 41 Silicon wafer 32, 42 Silicon oxide film

Claims (4)

[Claims] 1. A semiconductor device manufacturing wafer in which a semiconductor silicon layer is formed on a high electrical resistivity substrate having higher thermal conductivity than semiconductor silicon. 2. A semiconductor device manufacturing wafer in which a semiconductor silicon layer is formed on a high electrical resistivity substrate having a higher thermal conductivity than semiconductor silicon via an oxide film. 3. The high electric resistivity substrate is made of SiC or Al.
3. The wafer for manufacturing a semiconductor device according to claim 1, which is a substrate containing N as a main component. 4. The semiconductor device manufacturing wafer according to claim 3, wherein the substrate containing SiC or AlN as a main component is a substrate formed by a chemical vapor deposition method.