JPH11145437A - Manufacture of soi wafer and soi wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a SOI wafer having a SOI layer (active silicon layer), which does not generate thermal strain, peel off, cracks or the like due to the difference between the thermal expansion coefficients of a single-crystal silicon wafer and an insulating board, when the wafer and the board are bonded together, has the uniformity of a thin and good film thickness which is useful for the production of various devices, is superior in crystallinity and high in carrier mobility, and a method of manufacturing the SOI wafer. SOLUTION: A multi-staged heat treatment, a thinner filming treatment and a vapor phase etching treatment are successively performed in the following processes. A process (1): a single-crystal Si wafer is closely adhered to the upper part of an insulating board at room temperatures. A process (2): the wafer and the board are subjected to heat treatment at 100 to 300 deg.C to temporarily bond together the wafer and the board. A process (3): A single- crystal Si layer is formed into a thickness of 100 to 250 μm through alkaline etching. A process (4): the wafer and the board are subjected to heat treatment at 350 to 500 deg.C to finally bond together the wafer and the board. A process (5): the silicon layer is ground and polished to form the silicon layer in a thickness of 2 to 20 μm. A process (6): the silicon layer is formed into a SOI layer of a thickness of 0.5 μm or thinner by a vapor phase etching. A process (7): a heat treatment of 800 deg.C or higher is applied to the finally bond the wafer and board for enhancing the bonding strength of the wafer to the board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method of manufacturing an SOI wafer by a wafer bonding method, and more particularly to an SOI wafer manufactured by bonding an insulating substrate and a silicon substrate, not by bonding silicon substrates through an oxide film. The present invention relates to a manufacturing method and an SOI wafer manufactured by the method.

[0002]

2. Description of the Related Art Conventionally, as a method of fabricating a wafer having an SOI structure, a SIM is formed by implanting oxygen ions at a high concentration into a silicon single crystal and then performing a heat treatment at a high temperature to form an oxide film.
A technique that has attracted attention is a method using an OX (separation by implanted oxygen) method and a method of bonding two mirror-polished silicon wafers without using an adhesive, and thinning one of the wafers.

In the SIMOX method, the thickness of an SOI layer serving as a device active region can be determined and controlled by an acceleration voltage at the time of implanting oxygen ions. Therefore, a thin SOI layer having a high thickness uniformity can be easily obtained. However, there are many problems such as the reliability of the buried oxide film, the crystallinity of the SOI layer, and the need for heat treatment at a temperature of 1300 ° C. or higher.

[0004] In the wafer bonding method, an oxide film is formed on at least one of two single-crystal mirror-finished silicon wafers, bonded together without using an adhesive, and then subjected to a heat treatment (usually at 1000 to 1200 ° C). The bonding is strengthened by the addition, and then one of the wafers is thinned by grinding or wet etching, and then the surface of the thin film is mirror-polished to form an SOI layer. Although there is an advantage that the crystallinity of the layer is good, the thickness of the obtained SOI layer and its uniformity are limited because the layer is thinned by mechanical processing.

On the other hand, SOI wafers are advantageous in forming integrated circuits with higher densities, and in recent years, TFT-LCDs (Thin Film Transistor-Liquid
d Crystal Display, a thin-layer transistor liquid crystal display), and is beginning to be used in ultra-high frequency mobile phone devices. However, conventionally, this type of liquid crystal screen has been formed by forming an amorphous silicon film on a glass substrate by vapor deposition or by forming a thin film of polycrystalline silicon on a synthetic quartz substrate by a CVD method or the like. The mobility of electrons, which is an index of the change to amorphous, is 50 cm ² / V · sec in the amorphous state,
In the case of polycrystal, the maximum value is 200 cm ² / V · sec.
Further, since a driving circuit cannot be formed on the same screen as the TFT, there is a problem that wiring is limited and high-density driving cannot be performed.

Therefore, when a single crystal silicon wafer is bonded to an insulating substrate instead of the amorphous silicon film or the polycrystalline silicon film, the carrier mobility is reduced because the substrate is a perfect insulator. It is extremely high without being affected by the substrate, and the effect is particularly significant when driven at a high frequency. Moreover, in this case, a driving circuit can be integrally formed around the TFT region, and the mounting problem can be solved. However, as a substrate for a TFT-LCD, the thickness of the SOI layer must be reduced to, for example, about 0.5 μm or less, so that it can withstand grinding and polishing for thinning to such a thickness. A high-temperature heat treatment must be performed, and the synthetic quartz substrate and the silicon substrate having different coefficients of thermal expansion must be strongly bonded. Further, since the semiconductor device is further subjected to heat or mechanical stress in the semiconductor device manufacturing process, it is desired that the bonding force between the two substrates is sufficiently high.

[0007] When joining different types of substrates, one of the wafers is cracked or peeled during heat treatment for joining, or during cooling after joining, or during grinding or polishing, because the two substrates have different coefficients of thermal expansion. May occur and cause damage. This problem arises not only in the case of the single crystal silicon wafer / synthetic quartz substrate, but also in the case of bonding the silicon wafer to a substrate having a different thermal expansion coefficient, depending on the purpose of the semiconductor device. If the buried oxide film joining the silicon wafers is required to have an insulation property, transparency or the like higher than the dielectric strength, a single crystal silicon wafer and Al ₂ O ₃ (sapphire), aluminum nitride, silicon carbide, In some cases, an SOI layer is formed by directly bonding to an insulating wafer such as silicon nitride, and a solution is desired.

[0008]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has been made in view of the above circumstances. When a single crystal silicon wafer is bonded to an insulating substrate, a thermal strain caused by a difference in thermal expansion coefficient is caused. No peeling, cracking, etc.
Various integrated circuits and TFT-
To provide an SOI wafer having an SOI layer (active silicon layer) which is thin and has good film thickness uniformity, is excellent in crystallinity, and has high carrier mobility so that an LCD or the like can be formed, and a method of manufacturing the same. With the goal.

[0009]

According to a first aspect of the present invention, a single crystal silicon wafer is brought into close contact with an insulating substrate, and the silicon layer is ground and polished to form an SOI layer. In the method for manufacturing an SOI wafer, a multi-step heat treatment, a thinning treatment, and a vapor phase etching treatment are performed in the following order. (1) A single crystal silicon wafer is brought into close contact with an insulating substrate at room temperature. (2) Temporarily bond by heat treatment at 100 to 300 ° C. (3) The single-crystal silicon layer has a thickness of 1 by alkali etching.
It is set to 00 to 250 μm. (4) Heat treatment is performed at 350 to 500 ° C. to perform final bonding. (5) The single crystal silicon layer is ground and polished to 2 to 20 μm.
Make it thick. (6) The thickness of the single crystal silicon layer is reduced to 0 by vapor phase etching.
The SOI layer has a thickness of 5 μm or less. (7) The bonding strength is increased by applying a heat treatment at 800 ° C. or higher.

In this manner, the steps of raising the temperature from room temperature to a specific temperature range in a state where both substrates having different coefficients of thermal expansion are in close contact with each other, applying a heat treatment, and then forming a thin film are repeated stepwise. As a result, the thermal stress is relieved, and the joint is sufficiently joined in a slightly elastically deformed state. After the main bonding process, the bonding force is strengthened, so that the surface can be ground and the film can be thinned. Finally, the thickness of the SOI layer can be reduced to 0.5 μm or less by a vapor phase etching process, and a high-temperature heat treatment is performed in this state. It is possible to secure a bonding strength that can withstand the above. Also, the fabricated SOI
The wafer also has excellent uniformity of film thickness, crystallinity of the SOI layer, and carrier mobility.

In this case, it is preferable that the surface of the SOI layer of the SOI wafer obtained in the step (7) is mirror-polished in the manufacturing step. Thus, by performing mirror polishing on the surface of the SOI layer, it is possible to remove the surface roughness called haze that is generated by the vapor phase etching.

According to a third aspect of the present invention, the insulating substrate is made of a quartz substrate, a sapphire (alumina) substrate, a glass substrate, a silicon nitride substrate, an aluminum nitride substrate or a quartz substrate having a thermal expansion coefficient different from that of the single crystal silicon wafer. It was decided to be a silicon carbide substrate. These substrates have a different thermal expansion coefficient from that of the single crystal silicon wafer, but the bonding strength reaches a practical level or more due to the bonding heat treatment and thinning, and an SOI wafer having excellent dielectric strength can be obtained.

Further, the invention described in claim 4 of the present invention is an SOI wafer manufactured by the manufacturing method according to any one of claims 1 to 3,
This is an SOI wafer having a thin SOI layer having extremely low defects and good film thickness uniformity on a bulk insulating substrate having high insulating properties, and has excellent carrier mobility. Particularly, when the thickness formed on the insulating substrate is 0.5 μm or less, and the mobility of the carrier is 25
0 cm ² / V · sec or more, 150 cm ² / V · P type
With an SOI wafer having an SOI layer for more than
A thin film transistor (TFT) having excellent performance can be manufactured.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to these embodiments. Here, FIG. 1 is a flowchart showing an example of a manufacturing process of an SOI wafer by a method of manufacturing an SOI wafer by bonding a single crystal silicon wafer and an insulating substrate. FIG. 2 shows the PACE method (plasma assisted ch).
3A and 3B are conceptual diagrams schematically showing vapor phase etching by emical etching, wherein FIG. 3A is a perspective view and FIG.

Hereinafter, the present invention will be described focusing on the case where one silicon wafer is bonded to one synthetic quartz glass substrate as an insulating substrate. FIG. 1 shows an SOI including a multi-stage heat treatment, a thinning process, a vapor phase etching process, and a mirror polishing process.
FIG. 4 is a process chart showing steps of a method for manufacturing a wafer.

In step 1, one single-crystal silicon mirror wafer is brought into close contact with one synthetic quartz glass substrate at room temperature. In step 2, the two substrates that are in close contact with each other are
Heat treatment (low temperature heat treatment) is performed at 0 ° C. to perform temporary bonding. In this case, the thermal expansion coefficient of the synthetic quartz glass is smaller than that of silicon (Si: 2.33 × 10 ⁻⁶ , quartz: 0.6 ×
10 ^-6 ), when bonded to a silicon wafer of the same thickness and heated, the silicon wafer breaks at around 300 ° C. Therefore, the silicon wafer may be thinned to about 300 μm and heat-treated at 300 ° C., or the silicon wafer may be temporarily heat-treated at less than 300 ° C., for example, about 200 ° C. for temporary bonding.
If the heat treatment is lower than 100 ° C., the erosion resistance of the temporary bonding interface in the subsequent alkaline etching is insufficient. In step 3, the thickness of the single crystal silicon layer of the wafer temporarily bonded by the low-temperature heat treatment is reduced to 100 to 250 μm by alkali etching. If the wafers are temporarily bonded as described above, it becomes possible to make the silicon wafer thinner by etching. In this case, 100
When the etching is performed to less than μm, the etching time becomes longer, so that the amount of the etching solution eroded to the temporary bonding interface in the peripheral portion of the wafer is increased, and the area in which the element can be formed is reduced. On the other hand, if the silicon layer of 250 μm or more is left, cracks are likely to occur in the next heat treatment. In step 4,
Heat treatment (intermediate temperature heat treatment) is performed at 350 to 500 ° C., so that the two substrates are fully bonded. Thus, in step 3, the silicon layer is
Since the thickness is reduced to 0 to 250 μm, the intermediate temperature heat treatment can be performed without generating cracks, and the bonding strength can be increased. Then, through Steps 3 and 4, the bonding strength between the two substrates becomes sufficient to be ground, and becomes a strength that can withstand subsequent thinning by plane grinding or mirror polishing.

Next, in step 5, the single crystal silicon layer is ground and polished to a thickness of 2 to 20 μm. The grinding in this case is preferably surface grinding, and the polishing is preferably mirror polishing similar to the usual mirror polishing wafer manufacturing process. 2 silicon layers
If 0 μm or more is left, the vapor phase etching in the next step will be inefficient, and if it is less than 2 μm, there is a risk that the silicon layer will be partially lost depending on the polishing accuracy. Step 6 is a gas phase etching process called a PACE method, in which the thickness of the single crystal silicon layer is reduced to 0.
This is a step of reducing the thickness to 5 μm or less, making the thickness of the thin film uniform, and finishing the SOI layer.

The PACE method is one of the so-called dry etching methods, in which a high-frequency plasma 16 is localized in the cavity 12 and a gas phase etching is performed as shown in FIGS. 2 (a) and 2 (b). is there. First, the SOI on SOI wafer 11
After measuring the thickness distribution of the layer, the SOI
By controlling the traveling speed of the cavity 12 on the wafer 11 in accordance with the film thickness distribution, the time of exposure to the plasma 16 is controlled, and as a result, the amount of etching removal on the surface is controlled, so that the surface of the SOI wafer is controlled. This is for making the thickness uniform while removing the SOI layer by etching. The plasma 16 is localized and generated in the cavity 12 by applying a high frequency from a high frequency power supply 15 to the electrodes 13 and 14 arranged above and below the SOI wafer 11. The cavity can freely travel on the SOI wafer 11.

Step 7 is performed at a temperature of 800 ° C. or more,
By applying a heat treatment at a temperature of not less than ° C. (high-temperature heat treatment), the bonding strength between the two substrates can be further enhanced, whereby a bonding strength usable in the device process can be obtained. This high-temperature heat treatment can be performed by reducing the thickness of the single crystal silicon layer to 0.5 μm or less in step 6, and the silicon layer is elastically deformed in accordance with the shrinkage of the synthetic quartz glass. It is thought to be following, crack,
The occurrence of cracks, peeling, etc. was almost eliminated. This 0.
By applying a high-temperature heat treatment of 800 ° C. or more, particularly 1000 ° C. to a thinned SOI layer having a thickness of 5 μm or less, crystal defects caused by the single crystal silicon wafer used can be removed, and the quality of the SOI layer can be further improved. It became possible.

Step 8 is a mirror polishing step called touch polishing, which has a very small polishing allowance, and is intended to remove the surface roughness called haze of the surface formed by the gas phase etching in step 6, and is necessary. It is desirable to perform this mirror polishing step so that the removal amount of the polishing on the gas phase etched surface is 5 nm to 15 nm, preferably about 10 nm. Through the above steps, a high-quality SOI wafer having an SOI layer having high crystallinity, a thin film, high film thickness uniformity, and high carrier mobility can be manufactured.

The insulating substrate used in the present invention is a quartz substrate, a sapphire (alumina) substrate, a glass substrate, a silicon nitride substrate, an aluminum nitride substrate having a different coefficient of thermal expansion from a single crystal silicon wafer to be an SOI layer. Alternatively, it is selected from a silicon carbide substrate or the like according to the purpose of the semiconductor device. Particularly, in the case of a TFT-LCD, a quartz substrate is used because transparency is required.

A thin film transistor (TFT) was formed using an SOI wafer having a single crystal SOI layer having a thickness of 0.5 μm or less formed on a quartz insulating substrate among the SOI wafers manufactured by the above manufacturing method. In this case, an N-type carrier having a mobility of 250 cm ² / V · sec or more and a P-type carrier having a mobility of 150 cm ² / V · sec or more were obtained. As a result, it is possible to cope with higher speed and higher definition of the TFT-LCD in the future. Furthermore, it is compatible with high-speed personal computers, and the driving circuit is integrated, providing intelligent performance. In addition, S formed on an insulating substrate
Because of the OI structure, even when used at higher frequencies than normal,
Since a problem such as a delay in signal propagation speed does not occur and an ultra-high frequency device, for example, 5 GHz can be satisfied, the use as an ultra-high frequency mobile telephone device is opened. Further, there is an advantage that the device process of ULSI can be used as it is.

[0023]

EXAMPLES The present invention will now be described specifically with reference to examples of the present invention, but the present invention is not limited to these examples. EXAMPLE A silicon mirror wafer having a P-type conductivity, a resistivity of 10 Ω · cm, a diameter of 100 mm, a thickness of 300 μm, and a synthetic quartz glass having a diameter of 100 mm and a thickness of 550 μm was used. If the layer thickness is 0.
An SOI wafer having a thickness of 1 μm and a thickness variation of ± 0.01 μm or less in a plane was manufactured. Separately, SOI with N-type conductivity
Wafers (the specifications other than the conductivity type were the same as the P type) were similarly prepared.

The main processing conditions in the method of manufacturing an SOI wafer by performing a multi-step heat treatment, a thinning treatment and a vapor phase etching treatment are as follows. a) Temporary bonding conditions in step 2: heat treatment at 300 ° C. for 120 minutes. b) Alkaline etching in step 3: 50% KOH aqueous solution, single-crystal Si layer thickness: 135 μm. c) Main bonding condition of step 4: heat treatment at 450 ° C. for 120 minutes. d) Thickness of single crystal Si layer after grinding and polishing in step 5: 3 μm. e) Thickness of single crystal Si layer after vapor phase etching in step 6: 0.
11 μm. f) Heat treatment conditions in step 7: heat treatment at 1100 ° C. for 120 minutes. g) Thickness of single crystal Si layer after mirror polishing in step 8: 0.10 μm
m.

(Fabrication and Performance Evaluation of TFT-LCD) The two types of SOQ (Silicone On
Using a wafer, a gate oxide film was formed, a source / drain region was diffused, and the like, and a TFT-LCD was fabricated. The performance of the TFT-LCD was evaluated.

[0026]

[Table 1]

As is apparent from Table 1, P-type carrier mobility is a ^{_{μ FE = 277cm 2 / V ·}} sec, the carrier mobility of the ^{_{N-type, μ FE = 600cm 2 / V}} · sec and a very High values were obtained. Conventionally, 100 cm ² /
Since V · sec and N-type were about 200 cm ² / V · sec which were the highest on a practical level, remarkable progress could be achieved.

The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the scope of the claims of the present invention. It is included in the technical scope of the invention.

For example, the insulating substrate to be joined in the present invention is not limited to those listed in claim 3, but may be any insulating substrate as long as it does not cause a problem of impurities in a semiconductor process. In principle, any material may be used. For example, a substrate of another material or a substrate in which the above listed substrates are coated with an insulating film such as an oxide film may be used.

The specification of the single crystal silicon wafer bonded to the insulating substrate in the present invention is not particularly limited, and the presence or absence of an oxide film on the surface does not matter. The reason is that the silicon wafer surface is insulative because it is bonded to the insulating substrate, and if the silicon wafer surface has an oxide film (natural oxide film, thermal oxide film), the SOI layer This is because contamination from impurities (especially boron in the atmosphere) existing at the bonding interface is prevented, and the adhesion to the insulating substrate may be improved.

[0031]

As described above, according to the present invention,
Single-crystal silicon wafers with different coefficients of thermal expansion can be bonded to insulating substrates without defects such as cracks, cracks, and peeling. Ultra-thin film with good uniformity of film thickness. Ultra-low defect with excellent crystallinity and carrier mobility. An SOI wafer having an SOI layer can be manufactured relatively easily and at low cost. In particular, the carrier mobility of SOQ wafers is high, and future TFT-LCD
It is important to contribute to higher speed and higher definition. further,
Since it has a complete SOI structure, it is expected to be used for ultra-high frequency (5 GHz) mobile telephone devices.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an example of a manufacturing process of an SOI wafer of the present invention.

FIG. 2 is a conceptual diagram showing an outline of vapor phase etching by a PACE method. (A) A perspective view, (b) Sectional drawing.

[Explanation of symbols]

DESCRIPTION OF REFERENCE NUMERALS 1: a step of bringing a single crystal silicon wafer into close contact with an insulating substrate, 2: a step of temporary bonding by heat treatment, 3: a step of alkali etching of a Si layer, 4: a step of permanent bonding by heat treatment, 5: grinding and polishing of the Si layer 6 PACE vapor phase etching step 7 Bond strengthening step by heat treatment 8 Mirror polishing step 11 SOI wafer 12 Hollow 13, 14 Electrode 15 High frequency power supply 16 …plasma.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Atsuo Uchiyama Nagano Pref.

Claims (5)

[Claims] 1. A method for manufacturing an SOI wafer by forming a SOI layer by bringing a single-crystal silicon wafer into close contact with an insulating substrate and grinding and polishing the silicon layer to form an SOI wafer. A method for manufacturing an SOI wafer, comprising: performing a treatment. (1) A single crystal silicon wafer is brought into close contact with an insulating substrate at room temperature. (2) Temporarily bond by heat treatment at 100 to 300 ° C. (3) The single-crystal silicon layer has a thickness of 1 by alkali etching.
It is set to 00 to 250 μm. (4) Heat treatment is performed at 350 to 500 ° C. to perform final bonding. (5) The single crystal silicon layer is ground and polished to 2 to 20 μm.
Make it thick. (6) The thickness of the single crystal silicon layer is reduced to 0 by vapor phase etching.
The SOI layer has a thickness of 5 μm or less. (7) The bonding strength is increased by applying a heat treatment at 800 ° C. or higher. 2. The method for manufacturing an SOI wafer according to claim 1, wherein in the manufacturing step, the surface of the SOI layer of the SOI wafer obtained in the step (7) is mirror-polished. 3. The method according to claim 1, wherein the insulating substrate is a quartz substrate, a sapphire (alumina) substrate, a glass substrate, a silicon nitride substrate, an aluminum nitride substrate, or a silicon carbide substrate having a thermal expansion coefficient different from that of the single crystal silicon wafer. The method for manufacturing an SOI wafer according to claim 1 or 2, wherein 4. An SOI wafer manufactured by the manufacturing method according to any one of claims 1 to 3. 5. The thickness formed on an insulating substrate is 0.5 μm.
An SOI wafer having an SOI layer of not more than m, wherein the mobility of carriers is at least 250 cm ² / V · sec for N-type and at least 150 cm ² / V · sec for P-type. Weeha.