JP3488927B2 - Dielectric separation substrate and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation substrate for forming a semiconductor integrated circuit device, and more particularly to a dielectric isolation substrate having a structure in which a support is directly bonded to a semiconductor wafer, and a method for manufacturing the same. Regarding

[0002]

2. Description of the Related Art Withstand voltage between elements is several tens of volts to several hundreds.
V and a large high voltage integrated circuit device (power IC),
A method of completely separating each element to be integrated with an insulating film such as a dielectric film (for example, a silicon oxide film: SiO ₂ film) is adopted, and a normal semiconductor single crystal wafer is processed to manufacture it. The dielectric isolation substrate is used.

FIG. 2 is a sectional view for explaining the manufacturing process of the dielectric isolation substrate. First, a single crystal silicon wafer 301
The main surface having a diameter of 5 inches and a thickness of 600 μm, for example, is oxidized to form a SiO ₂ film 15 on the entire surface, patterning is performed by a photolithography method, and then a predetermined portion of SiO 2 is etched by a method such as etching. ₂ Open the film 15. Next, using the remaining SiO ₂ film as a mask, the isolation groove 6 having a depth of about 60 μm is formed by anisotropic etching using, for example, a mixed solution of potassium hydroxide and isopropyl alcohol [FIG. . Next, the SiO ₂ film 15 used as the mask is removed, the main surface of the single crystal silicon wafer 301 is oxidized again, and the entire surface has a thickness of about 1.2 μm.
The SiO ₂ film 2 for insulation is formed [(b) in the figure]. Polycrystalline silicon 602 is formed on the surface by high temperature vapor phase epitaxy (C
VD: forming temperature is about 1200 ° C., forming rate is about 5 μm /
(min) to fill the separation groove 6 with the silicon wafer 3
The same thickness as that of No. 01 (about 600 μm) is deposited [FIG. Large irregularities on the surface of the deposited polycrystalline silicon 602 (about several tens of μm: formed because the separation groove 6 is deep)
Is smoothed with the lower surface of the single crystal wafer 1 as a reference [FIG. Next, conversely, the polycrystalline silicon 6 with no irregularities
02 with reference to the front surface side of the single crystal silicon wafer 301
Unnecessary parts of the SiO ₂ film 2 by grinding or polishing.
Thus, the single crystal islands 3 separated by each are formed to complete the dielectric isolation substrate 1 [FIG.

Dielectric isolation substrate 1 produced in this way
Are treated in the same manner as a silicon single crystal wafer used for manufacturing an ordinary LSI, and a desired semiconductor element is formed on the single crystal isolation island 3 by a semiconductor element manufacturing process, and wiring between each element is performed by a metal thin film. A device is manufactured (not shown).

As is well known, in the conventional dielectric isolation substrate, a plurality of single crystal silicon islands for forming a semiconductor element are formed on the surface of a support made of polycrystalline silicon via a dielectric film. Many have a composite structure [see FIG. 2 (e)]. In such a composite structure dielectric isolation substrate,
The substrate is warped (curved) or distorted due to the difference in thermal expansion coefficient between the single-crystal silicon of the isolation island 3 and the polycrystal silicon of the support member. There are drawbacks such as changes in layers and large changes in curvature. Therefore, there is a problem in that the alignment accuracy of the photolithography process for patterning the device is lowered and the product yield is deteriorated.

Therefore, as a dielectric isolation substrate that solves these problems, it is described in, for example, Japanese Patent Laid-Open No. 3-265153, and its basic sectional structure is shown in FIG.
A structure in which a support is composed of a single crystal silicon wafer and a single crystal silicon wafer that becomes a single crystal island is bonded to the support wafer (hereinafter referred to as a bonding structure) has been used. In FIG. 3, a semiconductor element 4 is formed in an island-shaped single crystal silicon region 3, and the single crystal island 3 is formed on a surface of a support 5 made of a single crystal silicon wafer.
Are insulated from each other. Polycrystalline silicon 601 is formed in the isolation trench 6 in the adjacent portion of each single crystal silicon island region 3 insulated by the dielectric film 2.
Are connected to each other. The thickness of polycrystalline silicon 601 may be set to the minimum thickness at which isolation trench 6 is filled. The single crystal islands 3 connected by the polycrystalline silicon 601 are polycrystalline silicon 60.
1) It is bonded to a support 5 of single crystal silicon through a second thin layer of polycrystalline silicon 7 separately deposited for smoothing the surface.

A method of manufacturing a dielectric isolation substrate having such a junction structure will be described below with reference to the sectional view shown in FIG. First, the separation groove 6 of about 60 μm is formed on the main surface of a single crystal silicon wafer 301 (for example, diameter 5 inches, thickness 600 μm).
After the formation, the insulating SiO ₂ film 2 having a thickness of about 1.2 μm is formed on the entire surface, and polycrystalline silicon 601 is deposited to a thickness of about 100 μm until the isolation trench 6 is completely filled [(a) in the figure]. . The steps up to this point are the same as the steps shown in FIG. 2 except that the amount of polycrystalline silicon deposited is smaller than in the conventional method. Next, the large depressions of the deposited polycrystalline silicon 601 formed directly above the separation groove 6 are removed by mechanical cutting (grinding) or the like, and then finely divided by a mechanochemical polishing method that combines physical polishing and chemical etching. The rough surface is removed to form a smooth surface [FIG. In this case, as shown in FIG. 5 (a), there is an interface 16 where crystal grains collide in the separation groove 6 region. The plane orientation of the crystal tends to be the same in the plane orthogonal to the crystal growth direction (orientation). Therefore, the separation groove 6 and the bottom of the single crystal island 3 have different surface orientations, and the chemical etching rate in the separation groove 6 region is higher than that in the other portions. The 6 regions have irregularities that are about 20 nm lower than the island bottom [FIG. 5 (b)].

Next, although the formation rate is slow (about 1 μm / min or less), it is possible to process a large number of wafers at a time and the mass productivity is good, and the hot-wall CVD method is used to form polycrystalline silicon 601.
A second thin layer of polycrystalline silicon 7 is further applied to the polished surface of
m form. After that, the surface of the formed polycrystalline silicon thin layer 7 is mechanochemically polished to obtain a highly smooth surface capable of wafer bonding. In this case, since the surface before deposition has no extremely large irregularities and is deposited at a low temperature to form fine crystal grains, the crystal grains of the second thin polycrystalline silicon layer 7 are homogeneous and wafer bonding is performed by mechanochemical polishing. It is possible to easily obtain a surface having high smoothness (surface roughness of 20 nm or less).

A single crystal silicon wafer to be used as the support wafer 5 is prepared, the surface and the polished surface are bonded together by an appropriate method, and further heat treatment at high temperature is applied to bond the two wafers [FIG. )]. A method for joining the two semiconductor wafers described above is disclosed in, for example, Japanese Patent Laid-Open No. 62-62.
No. 27040, for example. Finally, as in the case of FIG. 2, the unnecessary portion of the single crystal silicon wafer 301 is removed by polishing to form the single crystal isolation island 3 to complete the dielectric isolation substrate 1 (FIG. 2 (d)).

[0010]

In the above-mentioned conventional example, since the consideration of the alteration of the second thin polycrystalline silicon layer 7 formed at the bonding interface during the bonding heat treatment is insufficient, the support wafer 5 is bonded. However, there was a problem that it was likely to be incomplete. Although details are unknown, the inventors of the present invention have experimentally estimated that defective bonding of the support wafer 5 is caused as follows. The second thin polycrystalline silicon layer 7 formed by the low temperature CVD method has a small grain size and contains a large amount of gas. Regrows and shrinks in volume,
It is considered that the gas in the crystal is desorbed and agglomerated in the created void to form a minute void. As a gas generation source, a gas such as moisture adsorbed on the two surfaces to be bonded can be considered. Such microvoids are usually 10-30
It was found that the recess was formed with a recess of about nm, and this portion remained as an unbonded region.

An object of the present invention is to solve the above-mentioned problems and to provide a dielectric isolation substrate in which complete support wafer bonding is achieved and a manufacturing method thereof.

[0012]

SUMMARY OF THE INVENTION In order to solve the above problems and realize perfect wafer bonding, the present invention forms a device on one surface of a junction type dielectric isolation substrate. The other surface of the plurality of semiconductor single crystal isolation islands electrically insulated from each other and having the semiconductor polycrystal layer buried in the isolation trench and connected to each other, and the support wafer are provided with the polycrystalline silicon thin layer interposed therebetween. In the case of direct bonding, an oxide film was formed on the surface of the support wafer and bonded.

That is, according to the present invention, a plurality of silicon single crystal island regions electrically insulated from each other for forming an electric element such as a semiconductor element on one side and the single crystal island region on the other side. a first polycrystalline silicon layer for connecting the side, adjacent to the other side of the first polycrystalline silicon layer
The crystal grains formed by the low temperature CVD method of 1000 ° C or less
A second silicon polycrystalline thin layer having finer crystal grains than the first silicon polycrystalline thin layer, and a support adjacent to the other side of the second silicon polycrystalline thin layer. In a dielectric isolation substrate, a silicon oxide film with a thickness of 35 nm or more is formed on the surface.
The support on which the silicon film is formed, the second silicon polycrystal
By bonding to the other side of the thin layer by heat treatment , oxidation between the second silicon polycrystalline thin layer and the support is carried out.
A silicon film is formed.

Further, according to the present invention, a step of forming an isolation groove on one side of a silicon single crystal wafer, a step of forming an insulating film on the surface of the single crystal wafer on which the isolation groove is formed, and a step of forming an insulating film on the insulating film surface. Forming a first silicon polycrystal layer and flattening it, and forming a second silicon polycrystal thin layer in the second silicon polycrystal layer .
The crystal grains of the polycrystalline thin layer are made into the first silicon polycrystalline layer.
CV of 1000 ° C or less to make finer than the crystal grains of
Forming a smooth surface on the first polycrystalline silicon surface by the D method, and smoothing the second polycrystalline silicon surface ,
A step of joining a support having a silicon oxide film having a film thickness of 35 nm or more formed on the surface by heat treatment, and a step of polishing the other side of the single crystal wafer to one end of the separation groove to form a silicon single crystal island region A method of manufacturing a dielectric isolation substrate, comprising:

[0015]

[Effect] Even if the crystal grains of the second polycrystalline silicon thin layer are altered by the bonding heat treatment and minute voids are formed, the oxide film formed on the surface of the support wafer flows during the high temperature bonding heat treatment. The microvoids are filled up, so that a complete bond of the carrier wafer is achieved.

[0016]

EXAMPLE An example of the present invention will be described below with reference to FIG. 1 (cross-sectional view). In this case, silicon (Si) was used as the semiconductor material, and a single crystal silicon wafer was used as the support wafer.

First, a silicon single crystal wafer 301 having a diameter of 5 inches and a thickness of 600 μm is prepared. This wafer is oxidized, and the formed SiO ₂ film is used as a mask to perform anisotropic etching using, for example, a mixed solution of potassium hydroxide and isopropyl alcohol to form a single crystal island by digging a separation groove 6 of about 60 μm. 3 is formed. Then, after removing the SiO ₂ film, the film is oxidized again to obtain about 1.2 μm of insulating Si.
The O ₂ film 2 is formed. Then, by a high temperature CVD method (formation temperature: about 1200 ° C., formation rate: about 5 μm / min), the polycrystalline silicon 601 is filled with about 100 μ until the separation groove 6 is filled.
m is formed [(a) in the figure].

After that, the polycrystalline Si 601 is polished to flatten it by eliminating large irregularities of several tens of μm due to the separation groove 6 [FIG. Further, unevenness of several tens of nm may occur in the mechanochemical polishing of the final polishing. In this case, in the subsequent heat treatment for forming the semiconductor element 4 in the single crystal 3 region, the polycrystalline silicon layer 601 is formed of the single crystal silicon layer in order to reduce the curvature of the wafer caused by the contraction and expansion of the polycrystalline silicon layer. Polish until just before 301. In order to further improve the flatness of the polished surface and shorten the polishing time, a mechanical polishing method such as a grinding method that is not affected by the difference in growth morphology due to crystal grains or separation grooves is preferable.
In this case, the roughness of the ground surface may be so large that the second thin polycrystalline silicon layer can be polished later.

Then, the polycrystalline silicon thin layer 7 is formed again on the surface of the polycrystalline silicon layer 601 by the low temperature CVD method at a forming temperature of 1000 ° C. or less by about 5 μm. Then, the surface of the polycrystalline silicon thin layer 7 is polished to about 3 μm by a mechanochemical method, and the surface of the polycrystalline silicon 601 is polished to several tens of nanometers.
It eliminates that the unevenness of m remains on the growth surface as it is.
In this case, since the polycrystalline silicon thin layer 7 is a homogeneous layer, it is possible to easily obtain a smooth polished surface of 20 nm or less [FIG. The above steps are the same as those of the conventional method.

Next, a single crystal wafer having a diameter of 5 inches and a SiO ₂ film 8 formed on the surface thereof and having a thickness of about 600 μm is prepared as a support 5, and a polycrystalline silicon layer is formed by the wafer bonding method similar to the conventional method described above. Bonded to the 7th surface [(d) of the same figure].
FIG. 6 is a result of examining the relationship between the area ratio in the wafer of the unbonded portion (void) generated in the wafer bonded by the above-mentioned high temperature heat treatment and the film thickness of the SiO ₂ film 8 formed on the support wafer. is there. In order to eliminate the generation of voids, it is necessary to form the SiO ₂ film 8 having a thickness of at least 20 nm on the support wafer. This is necessary and sufficient amount to fill the concave portion of about 30 nm formed by the crystal grains of the second polycrystalline silicon layer formed at low temperature by volumetric shrinkage by the high temperature heat treatment with the flow of the SiO ₂ layer 8. It indicates that SiO ₂ is required.

Finally, an unnecessary portion of the single crystal silicon 301 of the wafer to which the single crystal silicon wafer 5 serving as the support is bonded is removed by polishing to form the single crystal separation island 3 as shown in FIG. 1 (e). The dielectric isolation substrate 1 is completed [(e) in the figure].

According to the embodiment [0022] The above-mentioned, unevenness formed on the second polycrystalline silicon layer 7 by Si0 ₂ layers 8 are substantially eliminated, the support wafer is firmly bonded dielectric separation The substrate can be easily obtained.

Although a single crystal silicon wafer is used as the support in this embodiment, polycrystalline silicon or silicon carbide (SiC), which has been previously heat-treated at a higher temperature so that the alteration can be ignored by heat treatment, Even if a support made of other material such as quartz glass that does not become a pollution source in the semiconductor process is used, the same effect can be obtained by forming an oxide film and joining the support.

The same effect can be obtained by further depositing a SiO ₂ layer on the surface of the second polycrystalline silicon layer, and smoothing this surface to join a support wafer on which the SiO ₂ layer is not formed.

[0025]

According to the present invention, since the bonding of the support wafer in the dielectric isolation substrate having the bonding structure is completely achieved, it is possible to provide a highly reliable dielectric isolation substrate.

[Brief description of drawings]

1A to 1E are cross-sectional views of respective steps for explaining a method for manufacturing a dielectric isolation substrate which is an embodiment of the present invention. ,

2 (a) to 2 (e) are cross-sectional views of respective manufacturing steps for explaining a conventional dielectric isolation substrate.

FIG. 3 is a cross-sectional view illustrating a conventional dielectric isolation substrate having a junction structure.

4A to 4D are cross-sectional views of respective steps for explaining a method for manufacturing a conventional dielectric isolation substrate having a junction structure.

5A and 5B are cross-sectional views for explaining a crystal structure of a polycrystalline layer in an isolation groove of a dielectric isolation substrate.

FIG. 6 shows an area of an unbonded portion in a wafer and an oxide film (Si0
It is a figure for explaining the relation with the thickness of ( ₂ layers).

[Explanation of symbols]

1 Dielectric Isolation Substrate 2 Dielectric Film 3 Semiconductor Single Crystal Isolation Island 4 Semiconductor Element 5 Semiconductor Single Crystal Support 6 Isolation Groove 601 Polycrystalline Semiconductor Layer 7 Second Polycrystalline Semiconductor Layer 8 Oxide Film (SiO ₂ Layer)

Continued front page    (72) Inventor Yoshitaka Sugawara               1-1-1 Omika-cho, Hitachi-shi, Ibaraki               Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Shinichi Kurita               1-1-1 Omika-cho, Hitachi-shi, Ibaraki               Hitachi, Ltd. Hitachi factory (72) Inventor Yuichi Saito               314 Mitsubishi Ma, Nishimigaokinai, Noda City, Chiba Prefecture               Inside Terial Silicon Co., Ltd.                (56) Reference JP-A-3-265153 (JP, A)                 JP-A-63-62252 (JP, A)

Claims (2)

(57) [Claims] 1. A plurality of siliaries electrically insulated from each other for forming an electric device such as a semiconductor device on one side.
And the island region con single crystal, a first polycrystalline silicon layer for connecting said single crystal island regions on the other side, the first silicon
Adjacent to the other side of the emission polycrystalline layer 1000 ° C. or less of the cold
Is formed by the CVD method described above and the crystal grains are
A second polycrystalline silicon thin layer than the crystal grains of the crystal layer are fine, the dielectric isolation substrate having a support adjacent the other side of the second polycrystalline silicon thin layer, on the surface
The support in which a silicon oxide film having a film thickness of 35 nm or more is formed.
The carrier is heat treated on the other side of the second thin polycrystalline silicon layer.
A dielectric isolation substrate, characterized in that a silicon oxide film is formed between the second silicon polycrystal thin layer and the support by bonding them by reason . 2. A step of forming an isolation groove on one side of a silicon single crystal wafer, a step of forming an insulating film on the surface of the single crystal wafer on which the isolation groove is formed, and a first step on the surface of the insulating film. A step of forming and flattening a silicon polycrystalline layer, and a second step
The polycrystalline silicon thin layer, the silicon of the second polycrystalline thin layer
Than the crystal grains of the first silicon polycrystalline layer
A step of forming fine particles on the first silicon polycrystalline surface by a low temperature CVD method of 1000 ° C. or less and smooth polishing , and a film thickness of 3 on the surface of the second silicon polycrystalline smooth surface.
And a step of bonding a support having a silicon oxide film of 5 nm or more formed thereon by heat treatment, and a step of polishing the other side of the single crystal wafer to one end of a separation groove to form a silicon single crystal island region. A method for manufacturing a dielectric isolation substrate, comprising: