JP2552936B2 - Dielectric isolation substrate and semiconductor integrated circuit device using the same - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation substrate, and more particularly to a dielectric isolation substrate having a support made of single crystal silicon and a semiconductor using the dielectric isolation substrate. The present invention relates to an integrated circuit device.

(Prior art) High withstand voltage L such that the withstand voltage between elements is several 10V to several 100V.
In SI, it is necessary to completely separate each element with a dielectric film such as an oxide film (SiO ₂ ), and so-called dielectric isolation substrates are widely used in such a technical field.

As is well known, the conventional dielectric isolation substrate is
In many cases, a composite structure in which a plurality of single crystal Si islands were formed on the surface of a support made of polycrystalline Si via a dielectric film was used.
There is a problem that the substrate is warped or distorted due to the difference in thermal expansion coefficient between Si and polycrystalline Si.

Therefore, in recent years, as a dielectric isolation substrate that solves these problems, as shown in FIG.
A structure (hereinafter referred to as a bonding structure) which is made of Si and in which the support 5 and a single crystal wafer to be a single crystal island are bonded via a dielectric film has been used.

In FIG. 2, a semiconductor element 4 is formed in an island-shaped single crystal Si region 3, and the single crystal Si region 3 is insulated from each other by a dielectric film 2 on the surface of a support 5 made of single crystal Si. It is formed in the open state. Polycrystalline Si 601 is formed in the isolation groove 6 in the adjacent portion of each single crystal Si region 3 insulated by the dielectric film 2.

Hereinafter, a method for manufacturing a dielectric isolation substrate having such a junction structure will be described with reference to FIG.

First, the main surface of the single crystal Si wafer 301 is oxidized to form SiO ₂ 15 on the entire surface thereof, then a predetermined portion of the SiO ₂ is opened, and the SiO ₂ 15 is used as a mask, for example, potassium hydroxide. Isolation groove 6 having a depth of about 60 μm is formed by anisotropic etching using a mixed solution of isopropyl alcohol and isopropyl alcohol [FIG.

Then, the SiO ₂ 15 used as the mask is removed,
The main surface of the wafer 301 is oxidized again, and the entire surface of the wafer 301 has a thickness of 1.2.
After forming the insulating oxide film 2 having a thickness of [μm] [(b) in the figure], at least the separation groove 6 is formed on the surface by vapor phase growth (CVD; formation temperature: up to 1200 ° C., formation rate: up to 5 μm / min).
Polycrystalline Si601 is deposited to a thickness of about 100 μm until it is completely filled [Fig. (C)].

Then, the polycrystalline Si 601 in the unnecessary portion is removed by mechanical cutting and etching by the mechanochemical polishing method, and the height of the polycrystalline Si 601 deposited in the separation groove 6 portion is almost matched with the surface of the oxide film 2 [FIG. (D)].

Then, a single crystal Si wafer 5 to be a support is prepared, the surface and the polished surface are bonded together by an appropriate method, and further high temperature heat treatment is applied to bond the two wafers [(e) in the figure].

For the method of manufacturing the dielectric isolation substrate by bonding the two semiconductor wafers described above, see, for example, Japanese Patent Publication No.
It is described in Japanese Patent No. 27040.

Finally, the unnecessary portion of the single crystal wafer 301 is removed by polishing to form the single crystal Si separation island 3 to complete the dielectric separation substrate [FIG. After that, after forming a desired semiconductor element on the surface of the isolation island 3, wiring is provided between the elements to complete a semiconductor integrated circuit device [not shown].

(Problems to be Solved by the Invention) In the above-described conventional technology, since the consideration of the smoothing technology in the polishing step of unnecessary polycrystalline Si601 is insufficient, about 100Å required when bonding wafers is required.
It is difficult to obtain a polished surface having the following smoothness,
There has been a problem that poor bonding is likely to occur.

Then, the inventors investigated the cause of the defective bonding, and found that the cause was the growth direction of the polycrystalline Si 601 in the separation groove 6.

The main reasons why a smooth polished surface cannot be obtained will be described in detail below while showing a conventional method for polishing polycrystalline Si601.

When polishing the polycrystalline Si601, first, a mechanical polishing method (physical polishing method is used to remove irregularities due to uneven deposition of the polycrystalline Si601 and irregularities of about 10 μm generated in the separation groove 6 portion). The polycrystalline Si601 is cut to about 5 μm just above the bottom of the separation island 3 by polishing), and then the minute irregularities of several hundred Å to several thousand Å left for mechanical polishing are polished by the mechanochemical polishing method to complete About 100 required for proper wafer bonding
Å Make the following mirror surface.

However, since the crystal growth occurs in the direction perpendicular to the plane, the interface 16 where the polycrystalline Si601 grown in two directions collides with the polycrystalline Si601 in the separation groove 6 as shown in FIG. It is formed.

Since the mechanochemical polishing rate is very high at the portion where the interface 16 is formed, the polishing proceeds faster in the region of the separation groove 6 than at the bottom of the separation island 3, and the polycrystalline Si at the bottom of the separation island 3 is formed.
When polishing progresses until 601 disappears, the separation groove 6 area has a concave shape that is several hundred Å lower than the bottom of the separation island 3 and forms a smooth surface with 100 Å or less unevenness required for complete wafer bonding. Can't get

The polishing rate of a polishing method having a chemical polishing action, such as mechanochemical polishing, is usually easily affected by the crystal grain size, plane orientation, growth direction, etc., and the entire polished surface is a single crystal. Except when the case is amorphous, or when the crystal grain size is very small and the crystal plane orientation and growth direction can be ignored, and the case is a polycrystalline layer equivalent to the amorphous layer.
It is well known that it is very difficult to obtain a smoothness of 100Å or less by polishing.

In addition, if perfect wafer bonding is not achieved due to the above-mentioned bonding failure, the bonding force becomes weak,
When a semiconductor element is formed on each of the isolation islands 3 to form a semiconductor integrated circuit device, the isolation islands 3 will be distorted by heat treatment during the formation of the semiconductor elements or distortion due to heat generated during the operation of the formed semiconductor elements. It peels off or moves from the support 5.

As a result, there is a problem in that the wiring connecting the respective elements is broken and the reliability of the semiconductor integrated circuit device is lowered.

An object of the present invention is to solve the above-mentioned problems and to provide a dielectric isolation substrate that enables complete wafer bonding and a semiconductor integrated circuit device using the dielectric isolation substrate.

(Means for Solving the Problems) In order to solve the above problems and realize complete wafer bonding, the present invention provides a dielectric isolation substrate having a junction structure, in which one main surface has an isolation groove. A dielectric film is formed on the one main surface of the crystalline semiconductor wafer, and a polycrystalline film is formed on the dielectric film.
After forming Si, the polycrystalline Si is polished to be substantially smooth,
A buffer layer is formed on it. Then, the buffer layer was polished and smoothed, and the single crystal support was bonded thereto.

Then, a semiconductor element is formed on each isolation island of the dielectric isolation substrate thus formed to form a semiconductor integrated circuit device.

(Operation) According to the above-described configuration, the deep recess formed by the separation groove becomes a relatively shallow recess formed by the polycrystalline Si, and therefore the interface due to the separation groove does not occur in the buffer layer. Therefore, if the buffer layer is polished, an extremely smooth bonding surface can be obtained, and perfect wafer bonding can be achieved.

Further, since the bonding force becomes sufficiently strong when complete wafer bonding becomes possible, even if a heat treatment for forming a semiconductor element is applied to each isolation island, the isolation island may peel off or move from the support. It will not be lost.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view for explaining a method of manufacturing a dielectric isolation substrate which is an embodiment of the present invention.

In the figure, first, the separation groove 6 and the dielectric film 2 are formed on the main surface of a single crystal Si wafer 301 having a diameter of 4 inches and a thickness of 500 μm by the same method as the above-mentioned conventional technique, and then the polycrystalline Si is formed.
601 is formed with a film thickness of 100 μm [FIG.

Then, the surface of the polycrystalline Si601 was mechanically cut in the same manner as described above to remove large irregularities of about several tens of μm due to the separation groove 6, and then mechanochemical polishing was performed to perform polycrystalline cutting.
The surface of Si601 is smoothed [(b) in the figure].

In the heat treatment for forming a semiconductor element in the single crystal region 3 later, in order to reduce the curvature of the wafer caused by the contraction or expansion of the polycrystalline Si 601 as much as possible, the polycrystalline Si 601 is formed just before the single crystal 3 (up to 10 μm). It is desirable to polish.

In this example, since polycrystalline Si is further formed on the surface of the polished polycrystalline Si601 later, the polycrystalline Si601
There is no problem even if there are irregularities of several hundred Å on the surface of. Therefore, if the manufacturing process is simplified and the required time is shortened, only mechanical cutting may be performed and the subsequent mechanochemical polishing may be omitted.

Next, the polycrystalline Si layer 7 serving as a buffer film for absorbing the minute unevenness remaining on the surface of the polycrystalline Si601 is formed by the polycrystalline silicon.
Approximately 5 by the normal CVD method so that it adheres to the surface of 601.
It is formed with a film thickness of μm [(c) in the same figure]. In this case, the film thickness to be formed is several tenths of the film thickness of the polycrystalline Si601. Therefore, although the film formation rate is slow, many wafers can be processed at one time, which reduces the manufacturing cost. It is also possible to adopt a hot wall type CVD which can be performed.

The polycrystalline Si layer 7 grows on the surface of the polycrystalline Si 601 having a relatively smooth surface without the deep recesses such as the separation groove 6, and therefore the growth direction is constant. Therefore, the interface shown in FIG. 4 does not occur in the polycrystalline Si layer 7.

Next, the surface of the polycrystalline Si layer 7 is polished by about 3 μm and smoothed by a mechanochemical method. At this time, since the polycrystalline Si layer 7 has no interface, a smooth polished surface of 100 Å or less can be easily obtained.

Then, a single crystal wafer 5 having a diameter of 3 inches and a thickness of 500 μm to be a support is bonded by the same bonding method as described above (FIG. 7 (d)), and unnecessary portions of the single crystal 301 are removed by polishing to remove the dielectric material. The separation substrate 1 is completed [(e) in the figure].

Finally, a semiconductor element is formed on each single crystal island 3 by a normal LSI process and wiring is provided between the elements to complete a semiconductor integrated circuit device.

According to the present embodiment, the deep recess formed by the isolation trench 6 is polycrystalline.
Since Si601 forms a relatively shallow recess, no interface is formed in the polycrystalline Si layer 7, which is the buffer layer, by the separation groove 6.

As a result, the surface of the polycrystalline Si layer 7, which is the bonding surface with the support 5, can be polished extremely smoothly, so that perfect wafer bonding is possible and a highly reliable dielectric isolation substrate is provided. become able to.

Since the hot wall type CVD enables film formation at a low temperature, the crystal grains can be made smaller than in the case of the ordinary CVD. That is, when the polycrystalline Si layer 7 is formed by adopting the CVD of the hot wall method, the size of the crystal grain diameter of the polycrystalline Si layer 601 which is in contact with the polycrystalline Si layer 601 is It can be made smaller than the crystal grain size in the vicinity of the contact portion.

As a result, the smoothness obtained by the mechanochemical polishing can be made equal to that of the amorphous case. Therefore, if the polycrystalline Si layer 7 is formed by adopting the CVD of the hot wall method, the joint surface becomes smoother. And more complete bonding is possible.

FIG. 5 is a cross-sectional view for explaining a manufacturing method of another embodiment of the present invention, and the same or equivalent parts as in FIG. 1 are designated by the same reference numerals.

In the figure, after the separation groove 6 and the dielectric film 2 are formed on the surface of the single crystal 301, polycrystalline Si601 is formed with a film thickness of 100 μm, and the surface is polished and smoothed [see the same figure (a )], The description is omitted because it is similar to the above.

After smoothing the polycrystalline Si601, an amorphous Si layer 8 having an amorphous thickness of about 3 .mu.m is formed on the surface thereof by the CVD method [FIG.

Then, the amorphous is subjected to mechanochemical polishing.
The Si layer 8 is polished by about 1 μm to smooth its surface. At this time, since there is no large concave portion on the surface of the polycrystalline Si601 and the amorphous Si layer is a homogeneous amorphous material having no crystal grain boundaries, the amorphous Si layer 8 has a structure as shown in FIG. There is no interface. Therefore, a smooth surface of 100 Å or less can be obtained very easily by mechanochemical polishing.

Then, in the same manner as above, the support 5 is bonded [(c) in the figure], and unnecessary portions of the single crystal 301 are removed by polishing to complete the dielectric isolation substrate 1 [(d) in the figure].

Finally, a semiconductor element is formed on each single crystal island 3 by a normal LSI process and wiring is provided between the elements to complete a semiconductor integrated circuit device.

According to the present embodiment, since the buffer layer becomes amorphous, the smoothness by mechanochemical polishing is further improved as compared with the case of the above embodiments, and more complete bonding is possible.

Although the buffer layer is a semiconductor layer such as polycrystalline Si or amorphous Si in each of the above-described embodiments, it may be an insulating film such as a SiO2 film. Such SiO2 film is
It can be easily formed by oxidizing the surface of polycrystalline Si601.

In addition, in the above-mentioned examples, the buffer layer is described as a Si-containing material, but the present invention is not limited to this, and any other substance such as germanium is a main substance. The same effect can be obtained with a layer or a film.

(Effects of the Invention) As is apparent from the above description, according to the present invention, since the bonding surface with the support can be polished extremely smoothly, perfect wafer bonding is possible and reliability is improved. It becomes possible to provide a high dielectric isolation substrate.

By forming a semiconductor element on the single crystal island of the dielectric isolation substrate having such a structure, it becomes possible to provide a highly reliable semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a method of manufacturing a dielectric isolation substrate according to an embodiment of the present invention, FIG. 2 is a sectional view of a dielectric isolation substrate having a junction structure, and FIG. 3 is a conventional junction structure. 4 is a cross-sectional view for explaining a method for manufacturing the dielectric isolation substrate of FIG. 4, FIG. 4 is a cross-sectional view for a separation groove having an interface formed therein, and FIG. 5 is a view for explaining a manufacturing method according to another embodiment of the present invention. FIG. 2 ... Dielectric film, 3 ... Single crystal Si region, 4 ... Semiconductor element, 5 ... Support, 6 ... Separation groove, 7 ... Polycrystalline Si layer,
8 …… Amorphous Si layer, 15 …… SiO ₂ , 301 …… Single crystal S
i-wafer, 601 ... Polycrystalline Si

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoshi Tsukuda 3-1-1 Sachimachi, Hitachi City, Ibaraki Prefecture Hitachi Ltd. Hitachi Factory (56) References JP-A-63-205926 (JP, A) Special Features Kai Sho 53-33590 (JP, A) JP-A 63-62252 (JP, A)

Claims (2)

(57) [Claims] 1. A single crystal support, a polycrystalline semiconductor buffer layer bonded to the main surface of the single crystal support, a polycrystalline semiconductor layer laminated on the polycrystalline semiconductor buffer layer, and A plurality of single crystal semiconductor islands are formed on the surface of the crystalline semiconductor layer and are mutually insulated by a dielectric film and insulated from the polycrystalline semiconductor, and the crystal grain size of the polycrystalline semiconductor buffer layer is A dielectric isolation substrate having a diameter smaller than that of a crystal grain in the vicinity of the contact portion of the polycrystalline semiconductor layer in contact with the crystalline semiconductor buffer layer. 2. A semiconductor integrated circuit device having a semiconductor element formed on each of the single crystal semiconductor islands of the dielectric isolation substrate according to claim 1.