JPS61144036A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS61144036A JPS61144036A JP26675684A JP26675684A JPS61144036A JP S61144036 A JPS61144036 A JP S61144036A JP 26675684 A JP26675684 A JP 26675684A JP 26675684 A JP26675684 A JP 26675684A JP S61144036 A JPS61144036 A JP S61144036A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- substrate
- diamond
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010432 diamond Substances 0.000 claims abstract description 11
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 239000012790 adhesive layer Substances 0.000 claims abstract description 5
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 2
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000000919 ceramic Substances 0.000 abstract description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 abstract description 2
- 229910002804 graphite Inorganic materials 0.000 abstract description 2
- 239000010439 graphite Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052596 spinel Inorganic materials 0.000 description 2
- 239000011029 spinel Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- UBOXGVDOUJQMTN-UHFFFAOYSA-N trichloroethylene Natural products ClCC(Cl)Cl UBOXGVDOUJQMTN-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は誘電体で分離された集積回路の構造を有する半
導体装置およびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having an integrated circuit structure separated by a dielectric, and a method for manufacturing the same.
（従来技術とその問題点）
従来この種の半導体およびその製造方法としてす７７４
７ （Ａｌ＊Ｏｓ） マタＧｔスヒネｔｖ （ＭｇＡｇ
１０４ ）等の絶縁物上に単結晶シリコンをエピタキシ
ャル成長させ、そのエピタキシャル層に素子を形成する
製造方法で形成された半導体装置がある。しかし、サフ
ァイアまたはスピネル上にエピタキシャル成長されたシ
リコン単結晶の結晶性が悪いため、サファイアまたはス
ピネルとシリコンとの界面に大きなリーク電流が流れて
、消費電力が予想外に大きくなったり、移動度が半導体
単結晶基板のそれより低いため、予想はどには高速にな
らない、あるいはへテロエピタキシャル成長をさせるた
め歩留りが悪いという欠点が西すしかも大面積に高品質
な結晶が得られない欠点がある。また半導体素子を絶縁
物上に形成すると熱伝導が悪くなるという欠点も生じる
。(Prior art and its problems) Conventionally, there are 774 semiconductors of this type and their manufacturing methods.
7 (Al*Os) Mata Gt Suhine tv (MgAg
There is a semiconductor device manufactured by a manufacturing method in which single crystal silicon is epitaxially grown on an insulator such as No. 104), and elements are formed in the epitaxial layer. However, due to the poor crystallinity of the silicon single crystal epitaxially grown on sapphire or spinel, a large leakage current flows at the interface between sapphire or spinel and silicon, resulting in unexpectedly high power consumption and the mobility of semiconductors. Since it is lower than that of a single-crystal substrate, it has disadvantages such as not being able to achieve high speeds as expected, and poor yields due to heteroepitaxial growth.In addition, high-quality crystals cannot be obtained over a large area. Furthermore, when a semiconductor element is formed on an insulator, heat conduction becomes poor.
（発明の目的）
本発明はこれらの欠点を除去せしめ絶縁体上に結晶性の
良好な半導体装置を熱伝導の良い状態で大面積にわたっ
て均一に歩留り良く得ることを目的としている。更に本
発明はこのような半導体装置の製造方法を提供すること
を目的とする。(Objective of the Invention) The object of the present invention is to eliminate these drawbacks and obtain a semiconductor device with good crystallinity on an insulator with good thermal conductivity and uniformly over a large area with a high yield. A further object of the present invention is to provide a method for manufacturing such a semiconductor device.
（発明の構成）
本発明によれば支持基板上に絶縁層を介して半導体素子
形成層が設けられた半導体装置において、前記絶線層が
前記素子形成層から前記基板へ向かってダイアモンド層
、接着剤層の順に積層された２層からなることを特徴と
する半導体装置が得られる。(Structure of the Invention) According to the present invention, in a semiconductor device in which a semiconductor element formation layer is provided on a support substrate via an insulating layer, the disconnection layer extends from the element formation layer toward the substrate, including a diamond layer and an adhesive layer. A semiconductor device characterized in that it consists of two layers laminated in the order of the agent layer is obtained.
更に本発明によれば半導体単結晶基板上に素子分離領域
を設け、半導体部分に素子を形成した後、前記半導体装
置形成面を接着剤で保持基板に接着し、前記半導体基板
を裏面から研磨しながら除去して前記半導体装置が形成
された層を残し、除去した面にダイアモンド層を形成し
接着剤を介して、この面を支持基板に固定した後、前記
保持基板を除去することを特徴とする半導体装置の製造
方法が得られる。Further, according to the present invention, after providing an element isolation region on a semiconductor single crystal substrate and forming an element in the semiconductor portion, the semiconductor device forming surface is bonded to a holding substrate with an adhesive, and the semiconductor substrate is polished from the back side. a diamond layer is formed on the removed surface, and this surface is fixed to a support substrate via an adhesive, and then the holding substrate is removed. A method for manufacturing a semiconductor device is obtained.
ダイアモンドΦ熱膨張係数は８ｉに近いため、デバイス
層の変形が少なく、電気抵抗率は高いためデバイスを完
全に絶縁することができる効果を有するだけでなく熱伝
導率は８ｉに比べ４倍大きい利点を有するため、デバイ
ス層下面にダイアモンド層を用いることにより、デバイ
ス層で発生する熱の伝導が良く、デバイスの冷却効果を
良くすることができる。Diamond's Φ thermal expansion coefficient is close to 8i, so there is little deformation of the device layer, and its electrical resistivity is high, so it not only has the effect of completely insulating the device, but also has the advantage of thermal conductivity that is 4 times higher than 8i. Therefore, by using a diamond layer on the lower surface of the device layer, heat generated in the device layer can be well conducted, and the cooling effect of the device can be improved.
（実施例）
次に図面に基づき本発明の半導体装置およびその製造方
法の一実施例について説明する。半導体としてシリコン
を用いた場合について述べる。(Example) Next, an example of a semiconductor device and a method for manufacturing the same according to the present invention will be described based on the drawings. The case where silicon is used as the semiconductor will be described.
第１図は本発明によって得られた半導体装置を示し、第
２図（、）〜（ｆ）はその製造方法を示す。FIG. 1 shows a semiconductor device obtained by the present invention, and FIGS. 2(a) to (f) show a method of manufacturing the same.
第２図（ａｔから順に、第１図に示す半導体装置を得る
方法を説明する。単結晶シリコン基板１の表面に二酸化
シリコン（８ｉ０．）膜２を形成し、次に写真食刻法特
にドライエツチング等の微細加工技術を用いて、上記５
ｉＯ１膜２の所望の領域を除去し、残りの部分のｓ ｉ
Ｏ，ＩＱｔ ２をマスクとして第２図（、）に示すごと
く基板に所望の深さと垂直形状を有する溝３をドライエ
ツチング法により形成する。A method for obtaining the semiconductor device shown in FIG. 1 will be explained in order from FIG. Using microfabrication technology such as etching, the above 5
A desired region of the iO1 film 2 is removed, and the remaining portion s i
Using O, IQt 2 as a mask, a groove 3 having a desired depth and vertical shape is formed in the substrate by dry etching as shown in FIG.
この溝は素子の分離領域となるため、分離溝幅を微細に
するほど、素子の集積度は向上する。次に、上記マスク
として用いた８ｉ０＠膜２を除去して、再度二酸化シリ
コン２ｍとシリコン窒化膜２ｂを基板全面に形成する。Since this groove becomes an isolation region for the elements, the finer the width of the isolation groove, the higher the degree of integration of the elements. Next, the 8i0@ film 2 used as the mask is removed, and silicon dioxide 2m and silicon nitride film 2b are again formed over the entire surface of the substrate.
かかる図を第２図（ｂ）に示す。Such a diagram is shown in FIG. 2(b).
次に多結晶シリコン４を気相成長法により、分離溝３の
深さ以上の厚みに成長させて、分離溝３を埋め、通常の
ポリシング法等により表面を平担にし、その後シリコン
窒化膜２ｂをマスクとして、熱酸化を施すことにより、
分離溝内に埋めこまれた多結晶シリコン４の表面のみに
酸化膜２ｃが形成される。Next, polycrystalline silicon 4 is grown to a thickness equal to or greater than the depth of the isolation trench 3 using a vapor phase growth method, filling the isolation trench 3, and making the surface flat by a normal polishing method, etc., followed by silicon nitride film 2b. By using thermal oxidation as a mask,
Oxide film 2c is formed only on the surface of polycrystalline silicon 4 buried in the isolation trench.
次に、素子形成工程に入る。第２図（Ｃ）に続いて溝３
の中に埋め込まれた部分以外のシリコン窒化膜２ｂと酸
化膜２ａを除去した後、改めて、所望の厚さのゲート酸
化膜５を熱酸化法で形成し、次に多結晶シリコンでゲー
ト電極６を形成する。ゲート酸化膜６をマスクにして、
イオン注入法により、ソース領域７およびドレイン８を
形成し、その後例えばリンガラスのような層間絶縁膜９
をＣＶＤ法で埋積した後、コンタクトホールを形成し、
アルミ配線１０を形成すると第２図（ｄ）が得られ、Ｍ
Ｏ８集積回路の素子が形成できる。Next, an element forming process begins. Continuing from Figure 2 (C), groove 3
After removing the silicon nitride film 2b and oxide film 2a other than the part buried in the silicon nitride film 2a, a gate oxide film 5 of a desired thickness is formed again by thermal oxidation method, and then a gate electrode 6 is formed using polycrystalline silicon. form. Using the gate oxide film 6 as a mask,
A source region 7 and a drain 8 are formed by ion implantation, and then an interlayer insulating film 9 such as phosphor glass is formed.
After filling with the CVD method, a contact hole is formed,
When the aluminum wiring 10 is formed, FIG. 2(d) is obtained, and M
O8 integrated circuit elements can be formed.
次に素子形成面とシリコンウェハ等の保持基板１２を例
えばエポキシ樹脂等の接着剤１４で接着し、素子形成層
を除く単結晶シリコン基板１をメカノケミカルボリジン
グで除去する。前記メカノケミカルボリジングでは砥粒
としてコロイダルシリカを用い、化学液として有機アン
モニアを用いているため分＃ｇ３を被覆している二酸化
シリコン２ａは単結晶シリコン基板よりも加工速度が１
１５０以下とかなり小さいためポリシング加工を溝の深
さで止めることができ、素子形成層を容易に残すことが
できる。かかる図を第２図（ｅ）に示す。Next, the element forming surface and a holding substrate 12 such as a silicon wafer are bonded together with an adhesive 14 such as an epoxy resin, and the single crystal silicon substrate 1 excluding the element forming layer is removed by mechanochemical boring. In the mechanochemical boring, colloidal silica is used as the abrasive grains and organic ammonia is used as the chemical liquid, so the processing speed of the silicon dioxide 2a covering the portion #g3 is 11 faster than that of the single crystal silicon substrate.
Since it is quite small at 150 or less, polishing can be stopped at the depth of the groove, and the element forming layer can be easily left. Such a diagram is shown in FIG. 2(e).
る。かかる図を第２図（ｒ）に示す。Ru. Such a diagram is shown in FIG. 2(r).
次に、グラファイト層１５を例えばエポキシまたはポリ
イミドからなる接着層１６で窒化アルミニウム等のセラ
ミックスや単結晶シリコンなどの支持基板１７に接着固
定し、次に保持基板１２を研磨もしくはエツチングによ
って除去する。最後に適切な溶剤たとえば塩化メチレン
やトリクロルエチレンを用いて接着剤１４を除去する。Next, the graphite layer 15 is adhesively fixed to a support substrate 17 made of ceramic such as aluminum nitride or single crystal silicon using an adhesive layer 16 made of, for example, epoxy or polyimide, and then the holding substrate 12 is removed by polishing or etching. Finally, adhesive 14 is removed using a suitable solvent such as methylene chloride or trichloroethylene.
このようにして第１図に示す半導体装置が得られる。In this way, the semiconductor device shown in FIG. 1 is obtained.
以上詳細に説明したように、本発明によれば、良好な結
晶性を有する半導体層を容易に絶縁体上に形成すること
ができるとともに熱伝導率がシリコンの４倍というダイ
アモンドをデバイス層の下面に設けたことにより熱放射
がかなり良好な半導体装置を得ることができる。また素
子形成層の厚みは分離溝の深さにより自在に変えること
ができるＯ
また、実施例において、接着剤１４にエポキシ系を用い
たが熱可塑性の接着剤例えば、ポリアミド系を用いれば
、加熱するだけで保持基板１２を除去することができ、
実施例におけるように研磨による除去をしなくてもよく
１石英ガラス基板なども保持基板として使える。As described in detail above, according to the present invention, a semiconductor layer having good crystallinity can be easily formed on an insulator, and diamond, which has a thermal conductivity four times that of silicon, can be formed on the bottom surface of a device layer. By providing a semiconductor device with very good heat radiation, it is possible to obtain a semiconductor device with very good heat radiation. In addition, the thickness of the element forming layer can be freely changed depending on the depth of the separation groove. In addition, in the embodiment, an epoxy adhesive was used as the adhesive 14, but if a thermoplastic adhesive such as a polyamide adhesive is used, it is possible to The holding substrate 12 can be removed by simply
It is not necessary to remove by polishing as in the embodiment, and a quartz glass substrate or the like can also be used as the holding substrate.
また、実施例において、ＭＯ８集積回路の形成を例にあ
げたがバイポーラ型集積回路等の他の種類の素子につい
ても同様に作ることができる。さらに、実施例ではシリ
コン基板について述べたが、他の半導体単結晶基板、例
えば砒化ガリウムやインジウムリンについても本発明を
用いることができる。また素子分離法としてはＬＯＣＯ
ａ法やその変形など絶縁物で素子分離する方法であれば
用いることができる。また、本実施例では１層のデバイ
ス構造について示したが多層デバイス構造でも有効であ
る。Further, in the embodiments, the formation of an MO8 integrated circuit is taken as an example, but other types of elements such as bipolar integrated circuits can be formed in the same manner. Furthermore, although a silicon substrate has been described in the embodiment, the present invention can also be applied to other semiconductor single crystal substrates, such as gallium arsenide and indium phosphide. Also, as an element isolation method, LOCO
Any method that isolates elements using an insulator, such as the a-method or a modification thereof, can be used. Further, although the present embodiment shows a one-layer device structure, it is also effective for a multi-layer device structure.
（発明の効果）
本発明によれば従来の８０Ｉ構造の熱伝導性の悪さ、特
に多層の８０Ｉにしたときの熱伝導性の悪さ、リーク電
流、移動度等の結晶性の悪さを改善することができ、素
子の低消費電力化、高速化、集積度の向上等と、そのよ
うな素子を大面積に歩留り良く得ることができる。(Effects of the Invention) According to the present invention, it is possible to improve the poor thermal conductivity of the conventional 80I structure, especially the poor thermal conductivity when using a multilayer 80I structure, and the poor crystallinity such as leakage current and mobility. This makes it possible to reduce the power consumption, increase speed, and improve the degree of integration of the device, and to obtain such a device in a large area with high yield.
第１図は本発明の半導体装置の一実施例の断面図、第２
図（、）〜（ｆ）は本発明の方法による半導体装置の製
造方法を示す断面図である。
１・・・単結晶シリコン基板、
２、２ａ、 ２ｃ ・二酸化シリコン膜、２ｂ・・・
シリコン窒化膜、
３・・・溝１． ４・・・多績晶シリコン、５・
・・ゲート酸化膜、 ６・・・ゲート電極、７・・・リ
ース、 ８・・・ドレイン、９・・・層間絶縁
膜、 １０・・・アルミ配線、１２・・・保持基板、
１４・・・接着剤、１５・・・ダイアモンド、１６
・・・接着剤、１７・・・支持基板。
−”１
廖堰人ｌＦ垣士 円涼 晋 −、）
χ゛′
和
因 国
Ｃ％Ｊ へ
和 和
国 因
Ｃ％Ｊ 〜−ｆ１＋
−和FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIG.
Figures (,) to (f) are cross-sectional views showing a method for manufacturing a semiconductor device according to the method of the present invention. 1... Single crystal silicon substrate, 2, 2a, 2c - Silicon dioxide film, 2b...
Silicon nitride film, 3...groove 1. 4... polycrystalline silicon, 5.
... Gate oxide film, 6... Gate electrode, 7... Lease, 8... Drain, 9... Interlayer insulating film, 10... Aluminum wiring, 12... Holding substrate,
14...Adhesive, 15...Diamond, 16
... Adhesive, 17... Support substrate. −”1 Liaoyan IF Kakeru Susumu Enryo −,)
-sum
Claims (1)
けられた半導体装置において、前記絶縁層が前記素子形
成層から前記基板へ向かってダイアモンド層、接着剤層
の順に積層された２層からなることを特徴とする半導体
装置。 ２、半導体単結晶基板上に素子分離領域を設け、半導体
部分に素子を形成した後、前記半導体装置形成面を接着
剤で保持基板に接着し、前記半導体基板を裏面から研磨
しながら除去して前記半導体装置が形成された層を残し
、除去した面にダイアモンド層を形成し接着剤を介して
、この面を支持基板に固定した後、前記保持基板を除去
することを特徴とする半導体装置の製造方法。[Claims] 1. In a semiconductor device in which a semiconductor element forming layer is provided on a supporting substrate via an insulating layer, the insulating layer has a diamond layer and an adhesive layer extending from the element forming layer toward the substrate. A semiconductor device comprising two layers stacked in sequence. 2. After providing an element isolation region on a semiconductor single crystal substrate and forming an element in the semiconductor portion, the semiconductor device forming surface is adhered to a holding substrate with an adhesive, and the semiconductor substrate is removed while being polished from the back side. A semiconductor device characterized in that the layer on which the semiconductor device is formed is left, a diamond layer is formed on the removed surface, and this surface is fixed to a support substrate via an adhesive, and then the holding substrate is removed. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26675684A JPS61144036A (en) | 1984-12-18 | 1984-12-18 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26675684A JPS61144036A (en) | 1984-12-18 | 1984-12-18 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61144036A true JPS61144036A (en) | 1986-07-01 |
Family
ID=17435267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26675684A Pending JPS61144036A (en) | 1984-12-18 | 1984-12-18 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61144036A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02110968A (en) * | 1987-11-16 | 1990-04-24 | Crystallume | Semiconductor element and its manufacture and multilayer semiconductor device |
| JPH0541478A (en) * | 1991-07-22 | 1993-02-19 | Nec Corp | Semiconductor device and manufacture thereof |
| US7339791B2 (en) | 2001-01-22 | 2008-03-04 | Morgan Advanced Ceramics, Inc. | CVD diamond enhanced microprocessor cooling system |
| JP2008244498A (en) * | 1994-05-11 | 2008-10-09 | Chipscale Inc | Semiconductor fabrication with contact processing for wrap-around flange interface |
-
1984
- 1984-12-18 JP JP26675684A patent/JPS61144036A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02110968A (en) * | 1987-11-16 | 1990-04-24 | Crystallume | Semiconductor element and its manufacture and multilayer semiconductor device |
| JPH0541478A (en) * | 1991-07-22 | 1993-02-19 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2008244498A (en) * | 1994-05-11 | 2008-10-09 | Chipscale Inc | Semiconductor fabrication with contact processing for wrap-around flange interface |
| US7339791B2 (en) | 2001-01-22 | 2008-03-04 | Morgan Advanced Ceramics, Inc. | CVD diamond enhanced microprocessor cooling system |
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