JPS62203364A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62203364A JPS62203364A JP4665186A JP4665186A JPS62203364A JP S62203364 A JPS62203364 A JP S62203364A JP 4665186 A JP4665186 A JP 4665186A JP 4665186 A JP4665186 A JP 4665186A JP S62203364 A JPS62203364 A JP S62203364A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- semiconductor
- holder
- backside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 239000010410 layer Substances 0.000 abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 10
- 239000000377 silicon dioxide Substances 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000001737 promoting effect Effects 0.000 abstract 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000011241 protective layer Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 23
- 239000012790 adhesive layer Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003925 fat Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000013464 silicone adhesive Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
半導体基板にスイッチングなどの機能素子を形成しな場
合、素子として機能するのは基板の表面から高々１０μ
ｍ程度であり、残りの半導体基板領域は絶縁体基板にお
きかえた方が、特性Ｅ部会の良いことが多い。例えば絶
縁体基板上の半導体素子はＳｏ Ｉ （Ｓｉｌｉｃｏｎ
ｏｎ Ｉｎ５ｕｌａｔｏｒ）構造と呼ばれ、素子の高
速化、高耐圧化などに有効である。しかし、従来のＳｏ
ｌ構造形成法、例えばレーザあるいは電子ビームによる
再結晶化法ではシリコンの結晶性が充分でないため、期
待される特性が発揮できないという問題がある。When functional elements such as switching are not formed on a semiconductor substrate, the elements that function as elements are at most 10μ from the surface of the substrate.
m, and the characteristic E section is often better if the remaining semiconductor substrate region is replaced with an insulating substrate. For example, a semiconductor element on an insulating substrate is So I (Silicon
This structure is called an inverter (on inverter) structure, and is effective for increasing the speed and breakdown voltage of devices. However, the conventional So
In the l-structure formation method, for example, the recrystallization method using a laser or an electron beam, there is a problem in that expected characteristics cannot be exhibited because the crystallinity of silicon is insufficient.
そこで、半導体単結晶基板上にすでに形成しである素子
表面層を接着剤を用いて、第１の支持基板に固定し、基
板の裏面を物理１ヒ学的研磨法などによって薄膜１ヒし
、続いて、その面を第２の支持基板に絶縁性の接着剤を
用いて固定した後、第１の支持基板を再び物理（ヒ学７
ｉ１Ｆ磨法により除去して、素子表面を露出させるいわ
ゆるデバイス・Ｉ・ランスフγ法がジャパニーズ・ジャ
ーナル・オブ・アプライド・フィシ・ソクス（Ｊａｐａ
ｎｅｓｅ Ｊｏｕｒｎａｌｏｒ Ａｐｐｌｉｅｄ Ｉ’
１ｌｙｓｉｃｓ ） 、 ２３巻、ｉｏ号、Ｌ８１５頁
（１９８４年）に報告されている。Therefore, an element surface layer that has already been formed on a semiconductor single crystal substrate is fixed to a first supporting substrate using an adhesive, and a thin film is applied to the back surface of the substrate using a physical polishing method or the like. Next, after fixing that surface to the second support substrate using an insulating adhesive, the first support substrate is again physically
The so-called Device I Lansf γ method, in which the device surface is exposed by removing it using the i1F polishing method, was published in the Japanese Journal of Applied Physics.
nese Journal Applied I'
1lysics), Volume 23, Issue IO, Page L815 (1984).
（発明が解決しようとする問題点〕
しかしながら、従来のデバイストランスファ法では、素
子を第２の支持基板に移すのに２回の研磨工程が・ピ・
要であり、製造時間が長くかかる欠点をもっている９ま
た、半導体素子を形成している半導体基板が直接接着剤
に接しているため、接着剤中の不純物が素子形成層の中
へ導入され、半導体装置の誤動作の原因になり、その信
頼性を低下させるという問題点がある。(Problems to be Solved by the Invention) However, in the conventional device transfer method, two polishing steps are required to transfer the element to the second support substrate.
In addition, since the semiconductor substrate forming the semiconductor element is in direct contact with the adhesive, impurities in the adhesive may be introduced into the element formation layer, causing the semiconductor There is a problem in that it causes malfunction of the device and reduces its reliability.
本発明の目的はこれｌ′、の問題を解決し、製造時間を
短縮すると共にイＳ頼性の向上した半導体装置の製造方
法を提供することにある。An object of the present invention is to solve the problem l', and to provide a method for manufacturing a semiconductor device that shortens manufacturing time and improves reliability.
ｒ発明の構成〕
本発明の半導体装置の製造方法は、半導体基板表面に所
定の潔さを有し少くとも絶縁層を含む素子分離領域を形
成する工程と、前記素子分離領域間の半導体基板表面に
半導体素子を形成する工程と、゛卜導体素子か形成され
た前記半導体基板表面に樹脂からなる保持体を形成する
工程と、保持体が形成された前記半導体基板の裏面を物
理１ヒ学的に研磨し前記素子分離領域の絶縁層を露出さ
せる工程と、絶縁層が露出した前記半導体基板の裏面に
絶縁膜を形成する一Ｌ程と、絶縁膜が形成された前記半
導体基板の裏面に接着剤を介して支持基板を固定した後
前記保持体を除去する工程とを含んで構成される。rStructure of the Invention] A method for manufacturing a semiconductor device of the present invention includes a step of forming an element isolation region having a predetermined cleanliness on a surface of a semiconductor substrate and including at least an insulating layer; forming a holder made of resin on the surface of the semiconductor substrate on which the conductive element has been formed; polishing to expose the insulating layer in the element isolation region, forming an insulating film on the back surface of the semiconductor substrate with the exposed insulating layer, and adhering to the back surface of the semiconductor substrate on which the insulating film is formed. The method includes a step of fixing the supporting substrate via a material and then removing the holder.
次に、図面に基づき本発明の実施例について説明する。 Next, embodiments of the present invention will be described based on the drawings.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明する為
の工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず第１図（ａ＞に示すようにシリコン基板１の表面に
二酸化シリコン膜２を形成し、この二酸化シリコン膜２
の所定部を写真食刻法、特にドライエツチング等の微細
加工技術を用いて除去し、残りの部分の二酸化シリコン
膜２をマスクとしてシリコン基板１に所望の深さと垂直
形状を有する渦３をドライエ・ソチング法により形成す
る。このｉｔＭ ３は半導体素子の分離領域となるため
、分離溝３の幅を微細にするほど、素子の集積度は向上
する。First, as shown in FIG. 1 (a), a silicon dioxide film 2 is formed on the surface of a silicon substrate 1, and this silicon dioxide film 2 is
A predetermined portion of the silicon substrate 1 is removed using a microfabrication technique such as photolithography, especially dry etching, and a vortex 3 having a desired depth and vertical shape is formed on the silicon substrate 1 using the remaining silicon dioxide film 2 as a mask.・Form by soching method. Since this itM3 becomes an isolation region of the semiconductor element, the finer the width of the isolation groove 3, the higher the degree of integration of the element.
次に、第１図（ｂ）に示すようにマスクとして用いた二
酸化シリコン膜２を除去した後、再度二酸１ヒシリコン
膜２ａとシリコン窒化ｒＩＡ６を基板全面に形成する。Next, as shown in FIG. 1(b), after removing the silicon dioxide film 2 used as a mask, a monoarsenic dioxide film 2a and a silicon nitride rIA6 are again formed on the entire surface of the substrate.
次に、第１図（ｃ）に示すように、多結晶シリコン４を
気相成長法より、溝３の深さ以上の厚みに成長させて、
満３を埋め通常のｌｌＦ壱法等によりに面を平坦にし、
その後、シリコン窒化膜６をマスクとして熱酸化を施す
ことにより、分ＺＷ ｉ’Ａ内に埋め込まれた多結晶シ
リコン４の表面のみに二酸化シリコン膜２ｂを形成する
。Next, as shown in FIG. 1(c), polycrystalline silicon 4 is grown to a thickness equal to or greater than the depth of the groove 3 by vapor phase growth.
Fill in the full 3 and make the surface flat using the usual llf 1 method, etc.
Thereafter, by performing thermal oxidation using the silicon nitride film 6 as a mask, a silicon dioxide film 2b is formed only on the surface of the polycrystalline silicon 4 embedded in the portion ZW i'A.
次に、第１図（＋ｉ ）に示すように、溝３の中以外の
シリコン窒化膜６と酸化膜２ａを除去した後、改めて、
所望の厚さのグー１−酸化膜５を熱酸化法で形成し、続
いて多結晶シリコンでグー１〜電極７を形成する。更に
ゲート電極７をマスクにして、イオン注入法によりソー
ス・トレイン領域８を形成し、その後層間絶縁膜９をＣ
ＶＤ法で堆積した後、コンタクトホールを形成し、ｌ？
配線１０を形成することによりＭＯ３集積回路の素子か
完成する！
次に、第１図（ｅ）に示すように、素子形成面に樹脂、
例えばエポキシ系またはイミド系（４脂を５００μＩｎ
の厚さにスクリーン印刷し保持体１２を形成した後シリ
コン基板１の裏面を物理化学研磨法で除去する。Next, as shown in FIG. 1 (+i), after removing the silicon nitride film 6 and oxide film 2a outside the groove 3,
A goo 1-oxide film 5 of a desired thickness is formed by thermal oxidation, and then goo 1-electrode 7 are formed of polycrystalline silicon. Furthermore, using the gate electrode 7 as a mask, a source/train region 8 is formed by ion implantation, and then the interlayer insulating film 9 is coated with carbon.
After deposition by VD method, contact holes are formed and l?
By forming the wiring 10, the MO3 integrated circuit element is completed! Next, as shown in FIG. 1(e), resin is applied to the element forming surface.
For example, epoxy type or imide type (500μIn of 4 fats)
After forming the holder 12 by screen printing to a thickness of , the back surface of the silicon substrate 1 is removed by physical-chemical polishing.
この研磨工程では砥粒としてコロイダルシリカを用い、
（ヒ学液として有機アミンを用いているため、溝３を被
覆している二酸化シリコンｊ摸２ａはシリコン基板より
も加工速度がかなり小さいため、研磨加工を溝の深さで
止めることができ、素子形成層のみを容易に残すことが
できる。In this polishing process, colloidal silica is used as the abrasive grain,
(Because an organic amine is used as the abrasive solution, the polishing speed of the silicon dioxide layer 2a covering the groove 3 is much lower than that of the silicon substrate, so the polishing process can be stopped at the depth of the groove. Only the element forming layer can be easily left.
次に、第１図（ｆ゛）に示すように、フ゛ラズマＣＶＤ
法による二酸化シリコン又は窒化シリコン等からなる絶
縁膜１３を、研磨したシリコン基板１の裏面全体に形成
する。ＣＶＤ法による絶縁膜１３の形成温度は保持体１
２を形成している樹脂の融点より低いことが望ましい。Next, as shown in FIG. 1(f), plasma CVD
An insulating film 13 made of silicon dioxide, silicon nitride, or the like is formed on the entire back surface of the polished silicon substrate 1 by a method. The temperature at which the insulating film 13 is formed by the CVD method is
It is desirable that the melting point is lower than the melting point of the resin forming No. 2.
ランプ加熱等高温短時間の熱処理法によっても絶縁膜を
形成できる。The insulating film can also be formed by a heat treatment method such as lamp heating at high temperature and for a short time.
続いて、この絶縁膜１３上にエポキシ又はポリイミドか
らなる接着層１４を形成し、シリコンや石英ガラス等か
らなる支持基板１５を固定した後、シリコン基板１表面
に形成した保持体１２を有機溶剤で除去する。Subsequently, an adhesive layer 14 made of epoxy or polyimide is formed on this insulating film 13, and a support substrate 15 made of silicon, quartz glass, etc. is fixed, and then the holder 12 formed on the surface of the silicon substrate 1 is treated with an organic solvent. Remove.
このように本実施例によれば、良好な結晶性を有する素
子形成層を１回の物理化学的研磨工程で容易に支持基板
上に形成することができる。しかも絶縁膜が形成されて
いる為接着層からの汚染がなく素子特性が劣化すること
はない。また、素子形成層の厚みは素子分離領域を形成
する溝の深さにより制御することができる。As described above, according to this embodiment, an element formation layer having good crystallinity can be easily formed on a support substrate in one physicochemical polishing process. Furthermore, since an insulating film is formed, there is no contamination from the adhesive layer and the device characteristics do not deteriorate. Further, the thickness of the element forming layer can be controlled by the depth of the groove forming the element isolation region.
尚、上記実施例においては、接着層として、エポキシ系
またはポリイミド系接着剤を用いたか池に、シリコーン
系およびポリニスデル系等を用いてもよい。In the above embodiments, instead of the epoxy or polyimide adhesive used as the adhesive layer, a silicone adhesive, a polynisdel adhesive, or the like may be used.
また、実施例において、ＭＯ８集積回路の形成を例にあ
げたか、バイポーラ型集積回路等の他の種類の素子につ
いても同様に作ることができる。Further, in the embodiments, the formation of an MO8 integrated circuit has been taken as an example, but other types of devices such as a bipolar type integrated circuit can also be formed in the same manner.
さらに、実施例ではシリコン基板について述Ｉ＼たが、
池の半導体単結晶基板、例えば砒化ガリウムやインジウ
ムリンについても本発明を用いることができる。また素
子分離法としてはＬ ＯＣＯＳ法やその変形など絶縁物
で素子分離する方法であれば用いることができる。Furthermore, although a silicon substrate was described in the embodiment,
The present invention can also be used for semiconductor single crystal substrates such as gallium arsenide and indium phosphide. Further, as the element isolation method, any method that isolates elements using an insulator, such as the LOCOS method or a modification thereof, can be used.
［′発明の効果〕
以上説明したように、本発明は１回の研磨工程でデバイ
スＩ・ランスファを行なうことかてきるので、製造時間
が短縮されるとともに、素子形成層と接着層の間に絶縁
層を設けることにより、素子のｆＭ Ｔａ性を向上させ
ることができる効果がある。['Effects of the Invention] As explained above, the present invention allows device I transfer to be performed in one polishing process, which shortens the manufacturing time and also reduces the amount of material between the element forming layer and the adhesive layer. Providing the insulating layer has the effect of improving the fM Ta properties of the device.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明する為
の工程順に示した半導体チップの断面図である。
１・・・シリコン基板、２．２ａ、２ｂ・・・二酸化シ
リコン膜、３・・・溝、４・・・多結晶シリコン、５・
・・デーｌ−酸化膜、６・・・シリコン窒化膜、７・・
・ゲート電極、８・・・ソース・ドレイン領域、９・・
・層間絶縁膜、１０・・・へｅ配線、１２・・・保持体
、１３・・・絶縁膜、１４・・・接着層、１５・・・支
持基板。
３講
第１図FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2.2a, 2b... Silicon dioxide film, 3... Groove, 4... Polycrystalline silicon, 5...
...D-oxide film, 6...Silicon nitride film, 7...
・Gate electrode, 8... Source/drain region, 9...
- Interlayer insulating film, 10... e-wiring, 12... holder, 13... insulating film, 14... adhesive layer, 15... supporting substrate. Lecture 3 Figure 1
Claims (1)
む素子分離領域を形成する工程と、前記素子分離領域間
の前記半導体基板表面に半導体素子を形成する工程と、
半導体素子が形成された前記半導体基板表面に樹脂から
なる保持体を形成する工程と、保持体が形成された前記
半導体基板の裏面を物理化学的に研磨し前記素子分離領
域の絶縁層を露出させる工程と、絶縁層が露出した前記
半導体基板の裏面に絶縁膜を形成する工程と、絶縁膜が
形成された前記半導体基板の裏面に接着剤を介して支持
基板を固定した後前記保持体を除去する工程とを含むこ
とを特徴とする半導体装置の製造方法。forming an element isolation region having a predetermined depth and including at least an insulating layer on the surface of the semiconductor substrate; forming a semiconductor element on the surface of the semiconductor substrate between the element isolation regions;
forming a holder made of resin on the surface of the semiconductor substrate on which the semiconductor element is formed; and physicochemically polishing the back surface of the semiconductor substrate on which the holder is formed to expose the insulating layer in the element isolation region. a step of forming an insulating film on the back surface of the semiconductor substrate with an exposed insulating layer; and removing the holder after fixing the support substrate to the back surface of the semiconductor substrate with the insulating film formed thereon via an adhesive. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4665186A JPS62203364A (en) | 1986-03-03 | 1986-03-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4665186A JPS62203364A (en) | 1986-03-03 | 1986-03-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203364A true JPS62203364A (en) | 1987-09-08 |
Family
ID=12753217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4665186A Pending JPS62203364A (en) | 1986-03-03 | 1986-03-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203364A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01117047A (en) * | 1987-10-29 | 1989-05-09 | Sony Corp | Manufacture of semiconductor device |
| EP0485719A2 (en) * | 1990-11-16 | 1992-05-20 | Shin-Etsu Handotai Company Limited | Dielectrically isolated substrate and a process for producing the same |
| US6037634A (en) * | 1996-02-02 | 2000-03-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with first and second elements formed on first and second portions |
| JP2008244498A (en) * | 1994-05-11 | 2008-10-09 | Chipscale Inc | Semiconductor fabrication with contact processing for wrap-around flange interface |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS507912A (en) * | 1973-05-30 | 1975-01-27 | ||
| JPS5541767A (en) * | 1978-09-19 | 1980-03-24 | Nec Corp | Fixing semiconductor wafer to jig |
| JPS6116543A (en) * | 1984-07-03 | 1986-01-24 | Nec Corp | Semiconductor device and manufacture thereof |
-
1986
- 1986-03-03 JP JP4665186A patent/JPS62203364A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS507912A (en) * | 1973-05-30 | 1975-01-27 | ||
| JPS5541767A (en) * | 1978-09-19 | 1980-03-24 | Nec Corp | Fixing semiconductor wafer to jig |
| JPS6116543A (en) * | 1984-07-03 | 1986-01-24 | Nec Corp | Semiconductor device and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01117047A (en) * | 1987-10-29 | 1989-05-09 | Sony Corp | Manufacture of semiconductor device |
| EP0485719A2 (en) * | 1990-11-16 | 1992-05-20 | Shin-Etsu Handotai Company Limited | Dielectrically isolated substrate and a process for producing the same |
| EP0485719A3 (en) * | 1990-11-16 | 1995-12-27 | Shinetsu Handotai Kk | Dielectrically isolated substrate and a process for producing the same |
| JP2008244498A (en) * | 1994-05-11 | 2008-10-09 | Chipscale Inc | Semiconductor fabrication with contact processing for wrap-around flange interface |
| US6037634A (en) * | 1996-02-02 | 2000-03-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with first and second elements formed on first and second portions |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7528463B2 (en) | Semiconductor on insulator structure | |
| JP4319251B2 (en) | Semiconductor device having a support body in which a substrate having a semiconductor element and having conductor tracks formed thereon is bonded by an adhesive layer | |
| JP2987081B2 (en) | Semiconductor device manufacturing method | |
| JPH01315159A (en) | Dielectric-isolation semiconductor substrate and its manufacture | |
| JP2001127149A (en) | Semiconductor device and its manufacturing method | |
| KR100297867B1 (en) | Insulator type silicon semiconductor integrated circuit manufacturing method | |
| JPH06268054A (en) | Semiconductor device | |
| JP4060882B2 (en) | Manufacturing method of electronic device | |
| JPS62203364A (en) | Manufacture of semiconductor device | |
| JPH11330438A (en) | Manufacture of soi wafer and soi wafer | |
| JPH113842A (en) | Substrate for semiconductor electronic element and manufacture thereof | |
| JPH04262576A (en) | Semiconductor device and manufacture thereof | |
| JP5231772B2 (en) | Method for manufacturing transmissive liquid crystal display element substrate | |
| JPH06302791A (en) | Semiconductor substrate and manufacture thereof | |
| JPH04199632A (en) | Soi wafer and manufacture thereof | |
| JPS62183168A (en) | Manufacture of semiconductor device | |
| JPH0468770B2 (en) | ||
| JP2001298169A (en) | Semiconductor device and producing method therefor | |
| JPH06310427A (en) | Manufacture of semiconductor device | |
| JPH061778B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH04299859A (en) | Manufacture of semiconductor device | |
| JP4064682B2 (en) | Integrated circuit | |
| JPS63107161A (en) | Manufacture of semiconductor element | |
| JP3086958B2 (en) | Method for manufacturing semiconductor device | |
| JPH0587975B2 (en) |