JP3086958B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3086958B2 JP3086958B2 JP02309437A JP30943790A JP3086958B2 JP 3086958 B2 JP3086958 B2 JP 3086958B2 JP 02309437 A JP02309437 A JP 02309437A JP 30943790 A JP30943790 A JP 30943790A JP 3086958 B2 JP3086958 B2 JP 3086958B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- sio
- silicon
- silicon substrate
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device.
第２図（ａ）〜（ｅ）の工程断面図により従来技術を
説明する。The prior art will be described with reference to the process sectional views of FIGS. 2 (a) to 2 (e).
第２図（ａ）は、半導体シリコンを使った通常のLSI
プロセスにより作製されたシリコン半導体の断面図を示
す。21は半導体シリコン基板、22はトランジスタ、抵
抗、コンデンサー等が形成されているデバイス層、23は
素子分離として使用しているSiO2層を示す。Fig. 2 (a) shows a normal LSI using semiconductor silicon
1 shows a cross-sectional view of a silicon semiconductor manufactured by a process. Reference numeral 21 denotes a semiconductor silicon substrate, 22 denotes a device layer on which transistors, resistors, capacitors and the like are formed, and 23 denotes an SiO 2 layer used as element isolation.
次に、第２図（ｂ）に示すように、エポキシ樹脂24を
用いて、厚いシリコン基板25に接着する。次に、第２図
（ｃ）に示すように、デバイス層22、SiO2層23を残すよ
うに、シリコン基板21を研磨する。ここで、デバイス層
22とSiO2層23をを含む薄膜層26が残る。Next, as shown in FIG. 2B, an epoxy resin 24 is used to adhere to a thick silicon substrate 25. Next, as shown in FIG. 2C, the silicon substrate 21 is polished so that the device layer 22 and the SiO 2 layer 23 are left. Where the device layer
The thin film layer 26 including the layer 22 and the SiO 2 layer 23 remains.
次に、第２図（ｄ）に示すように、シリコンデバイス
層22が形成されている側と反対側27（第２図（ｃ）参
照）に、シリコン基板29をエポキシ樹脂28により接着す
る。最後に、第２図（ｅ）に示すように、上側のシリコ
ン基板25を研磨により取り去る。エポキシ樹脂28がこの
時の研磨のストッパーとして使われる。更に酸素プラズ
マにより、エポキシ樹脂24が取り去られる。Next, as shown in FIG. 2D, a silicon substrate 29 is bonded to the side 27 opposite to the side on which the silicon device layer 22 is formed (see FIG. 2C) with an epoxy resin. Finally, as shown in FIG. 2 (e), the upper silicon substrate 25 is removed by polishing. The epoxy resin 28 is used as a polishing stopper at this time. Further, the epoxy resin 24 is removed by the oxygen plasma.
従来技術においては、第２図（ｅ）の図面において、
接着剤28としてエポキシ樹脂を使用している。デバイス
22とこのエポキシ樹脂28は極く近傍に存在しているた
め、エポキシ樹脂より発生するナトリウムイオン（以
後、Naイオンと略す）がデバイス層22に簡単に侵入す
る。このNaイオンがデバイス特性に悪影響を与える。例
えば、MOSトランジスタにおいて、ゲート電圧を加えて
いない時に流れるリーク電流が、通常のバルクシリコン
上に作製したMOSトランジスタのそれより数オーダー高
いという現象が生じる。In the prior art, in the drawing of FIG.
Epoxy resin is used as the adhesive 28. device
Since the epoxy resin 22 and the epoxy resin 28 are very close to each other, sodium ions (hereinafter abbreviated as Na ions) generated from the epoxy resin easily enter the device layer 22. These Na ions adversely affect device characteristics. For example, a phenomenon occurs in a MOS transistor in which a leakage current flowing when no gate voltage is applied is several orders of magnitude higher than that of a MOS transistor fabricated on normal bulk silicon.
本発明は、上記した従来技術の欠点を解決するために
半導体デバイス層と基板の接着を、スピンオングラス法
（以後SOG法と略す）によるSiO2層によって行うことを
特徴とする。The present invention is characterized in that the semiconductor device layer and the substrate are bonded by a spin-on-glass (hereinafter abbreviated as SOG) SiO 2 layer in order to solve the above-mentioned drawbacks of the prior art.
本発明はシリコンデバイス層のある薄膜層と基板の間
にSOG法によりSiO2層を接着剤として設けると、SiO2中
にはNaイオン等のデバイス特性に悪影響を及ぼす不純物
は存在しないため、このSiO2の接着剤と極く近傍の半導
体シリコンデバイス層にNaイオン等の不純物は侵入しな
い。In the present invention, when an SiO 2 layer is provided as an adhesive between the thin film layer having a silicon device layer and the substrate by the SOG method, impurities such as Na ions do not adversely affect device characteristics in SiO 2. Impurities such as Na ions do not enter the SiO 2 adhesive and the semiconductor silicon device layer in the immediate vicinity.
第１図（ａ）〜（ｅ）の工程断面図により本発明の詳
細を説明する。The details of the present invention will be described with reference to the process sectional views of FIGS. 1 (a) to (e).
第１図（ａ）は、半導体シリコンを使った通常のLSI
プロセスにより作製されたシリコン半導体の断面図を示
す。11は半導体シリコン基板、12はデバイス層、13は素
子分離用のSiO2層を示す。Fig. 1 (a) shows a normal LSI using semiconductor silicon
1 shows a cross-sectional view of a silicon semiconductor manufactured by a process. Reference numeral 11 denotes a semiconductor silicon substrate, 12 denotes a device layer, and 13 denotes a SiO 2 layer for element isolation.
次に第１図（ｂ）に示すように、SOG法を用いたSiO2
層14を接着剤としてシリコン基板11と他のシリコン基板
15を接着する。液状のSOG14をシリコン基板11に塗布
し、シリコン基板15を乗せ、その後約150℃程で熱する
ことによって接着する。Next, as shown in FIG. 1 (b), the SiO 2
The silicon substrate 11 and another silicon substrate using the layer 14 as an adhesive
Glue 15 A liquid SOG 14 is applied to the silicon substrate 11, the silicon substrate 15 is placed thereon, and then bonded by heating at about 150 ° C.
次に第１図（ｃ）に示すように、デバイス層12とSiO2
層13を含む薄膜層16が残るように、シリコン基板11を研
磨する。Next, as shown in FIG. 1C, the device layer 12 and the SiO 2
The silicon substrate 11 is polished so that the thin film layer 16 including the layer 13 remains.
次に第１図（ｄ）に示すように、シリコンデバイス層
12が形成されている側と反対側17（第１図（ｃ）参照）
に、シリコン基板19をSOG法を使ったSiO2層18により接
着する。最後に第１図（ｅ）に示すように、上側のシリ
コン基板15を研磨により取り去る。これ以降、接着剤と
して使用したSiO2層18は取り去っても良いし、残してお
いても良い。Next, as shown in FIG. 1 (d), the silicon device layer
The side 17 opposite to the side on which 12 is formed (see FIG. 1 (c))
Then, a silicon substrate 19 is bonded by an SiO 2 layer 18 using the SOG method. Finally, as shown in FIG. 1 (e), the upper silicon substrate 15 is removed by polishing. Thereafter, the SiO 2 layer 18 used as an adhesive may be removed or may be left.
第３図（ａ）〜（ｃ）の工程断面図により、本発明の
他の実施例を示す。Another embodiment of the present invention is shown in the process sectional views of FIGS. 3 (a) to 3 (c).
第３図（ａ）において、31は通常のLSIプロセスを経
てトランジスタ、抵抗、容量等が形成されたデバイス
層、32はSiO2層、33は裏面シリコン層を示す。このウェ
ハは32のSiO2層が酸素イオン注入により形成されたSOI
（SiOn Insulator）ウェハでも良し、裏面シリコンを
熱酸化して他のシリコン基板と高温で張り合わせたSOI
ウェハでも良い。In FIG. 3A, reference numeral 31 denotes a device layer on which transistors, resistors, capacitors, etc. are formed through a normal LSI process, 32 denotes an SiO 2 layer, and 33 denotes a back silicon layer. This wafer is a SOI with 32 SiO 2 layers formed by oxygen ion implantation
(SiOn Insulator) SOI wafers can be used, and the backside silicon is thermally oxidized and bonded to other silicon substrates at high temperature
A wafer may be used.
第３図（ｂ）において、このウェハをSOG法を用いたS
iO2層を接着剤として利用して絶縁基板35を張り合わせ
る。次に、第３図（ｃ）において、例えば90℃程度のKO
H液にこのウェハを入れて、裏面シリコンをエッチング
する。ここで、注意すべきは接着剤として使用したSiO2
層34はデバイスが形成されているシリコンデバイス層31
のデバイスが形成されている側にあることである。In FIG. 3 (b), this wafer was subjected to SOG using the SOG method.
The insulating substrate 35 is bonded using the iO 2 layer as an adhesive. Next, in FIG. 3 (c), for example, KO at about 90 ° C.
This wafer is put in H solution, and the backside silicon is etched. Here, it should be noted that SiO 2 used as an adhesive
Layer 34 is the silicon device layer 31 on which the device is formed
Device is on the side where it is formed.
以上、詳細に説明したように、本発明の半導体装置及
びその製造方法は、薄いシリコンデバイス層と半導体シ
リコン基板又は絶縁基板をSOG法を用いて形成したSiO2
層を接着剤として利用し張り合わせた事により、接着剤
のSiO2層とデバイス層が極く近傍にあっても、信頼性の
高いSiO2層のため、Naイオン等の不純物によりデバイス
特性が悪影響を受けることもなく、安定なデバイス特性
が得られる大きな利点を持っている。As described above in detail, the semiconductor device of the present invention and the method of manufacturing the same include SiO 2 in which a thin silicon device layer and a semiconductor silicon substrate or an insulating substrate are formed by using the SOG method.
By using the layers as an adhesive and bonding, even if the SiO 2 layer of the adhesive and the device layer are in close proximity, the device characteristics are adversely affected by impurities such as Na ions because of the highly reliable SiO 2 layer There is a great advantage that stable device characteristics can be obtained without receiving the above.
第１図（ａ）〜（ｅ）は本発明の実施例を示す工程断面
図、第２図（ａ）〜（ｃ）は従来技術の実施例を示す工
程断面図、第３図（ａ）〜（ｅ）は本発明の他の実施例
を示す工程断面図である。 11、19……シリコン基板 12、32……シリコンデバイス層 14、18、34……SiO2接着剤層 35……絶縁基板1 (a) to 1 (e) are process sectional views showing an embodiment of the present invention, FIGS. 2 (a) to 2 (c) are process sectional views showing an embodiment of the prior art, and FIG. 3 (a). (E) is a process sectional view showing another embodiment of the present invention. 11, 19 ...... silicon substrate 12, 32 ...... silicon device layer 14,18,34 ...... SiO 2 adhesive layer 35 ...... insulating substrate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松山 信義 東京都江東区亀戸６丁目31番１号 セイ コー電子工業株式会社内 (72)発明者 丹羽 均 東京都江東区亀戸６丁目31番１号 セイ コー電子工業株式会社内 (72)発明者 吉野 朋之 東京都江東区亀戸６丁目31番１号 セイ コー電子工業株式会社内 (56)参考文献 特開 平２−154232（ＪＰ，Ａ) 特開 昭63−199442（ＪＰ，Ａ) 特開 昭63−308386（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/12 H01L 21/336 H01L 27/00 301 H01L 29/786 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuyoshi Matsuyama 6-31-1, Kameido, Koto-ku, Tokyo Inside Seiko Electronics Corporation (72) Inventor Hitoshi Niwa 6-31, Kameido, Koto-ku, Tokyo Inside Seiko Electronics Co., Ltd. (72) Inventor Tomoyuki Yoshino 6-31-1, Kameido, Koto-ku, Tokyo Inside Seiko Electronics Co., Ltd. (56) References JP-A-2-154232 (JP, A) JP 63-199442 (JP, A) JP-A-63-308386 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 27/12 H01L 21/336 H01L 27/00 301 H01L 29/786
Claims (2)
を形成する工程と、前記第１のシリコン基板上の前記Si
O2層表面に第２のシリコン基板を熱で張り合わせる工程
と、前記第２のシリコン基板にトランジスタ、抵抗及び
容量を形成することによりシリコンデバイス層を形成す
る工程と、前記シリコンデバイス層の上にSiO2を接着剤
として絶縁基板を張り合わせる工程と、前記シリコン基
板をエッチング除去する工程よりなることを特徴とする
半導体装置の製造方法。A step of forming an SiO 2 layer on the first silicon substrate by thermal oxidation; and forming the Si 2 layer on the first silicon substrate.
Bonding a second silicon substrate to the surface of the O 2 layer by heat, forming a silicon device layer by forming a transistor, a resistor and a capacitor on the second silicon substrate; A step of bonding an insulating substrate using SiO 2 as an adhesive, and a step of etching and removing the silicon substrate.
請求項１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein said SiO 2 used as an adhesive is formed by an SOG method.
Priority Applications (15)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02309437A JP3086958B2 (en) | 1990-11-15 | 1990-11-15 | Method for manufacturing semiconductor device |
| US07/791,912 US5347154A (en) | 1990-11-15 | 1991-11-13 | Light valve device using semiconductive composite substrate |
| KR1019910020276A KR100292974B1 (en) | 1990-11-15 | 1991-11-14 | Semiconductor device and manufacturing method |
| DE69133628T DE69133628D1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve and its method of manufacture |
| EP91310565A EP0486318B1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| DE69133483T DE69133483T2 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve and its method of manufacture |
| DE69133440T DE69133440T2 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve and its method of manufacture |
| EP98204180A EP0915503B1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| EP00200828A EP1026733B1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| US08/264,635 US5486708A (en) | 1990-11-15 | 1994-06-23 | Light valve device using semiconductive composite substrate |
| US08/460,536 US5728591A (en) | 1990-11-15 | 1995-06-02 | Process for manufacturing light valve device using semiconductive composite substrate |
| US08/459,834 US5618739A (en) | 1990-11-15 | 1995-06-02 | Method of making light valve device using semiconductive composite substrate |
| US08/460,538 US5572045A (en) | 1990-11-15 | 1995-06-02 | Light valve device using semiconductive composite substrate |
| KR1019990044494A KR100311340B1 (en) | 1990-11-15 | 1999-10-14 | light valve device, method of manufacturing the device, and image projection system using the device |
| HK99105064.2A HK1020801A1 (en) | 1990-11-15 | 1999-11-05 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02309437A JP3086958B2 (en) | 1990-11-15 | 1990-11-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04180675A JPH04180675A (en) | 1992-06-26 |
| JP3086958B2 true JP3086958B2 (en) | 2000-09-11 |
Family
ID=17992991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02309437A Expired - Lifetime JP3086958B2 (en) | 1990-11-15 | 1990-11-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3086958B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6570221B1 (en) | 1993-07-27 | 2003-05-27 | Hyundai Electronics America | Bonding of silicon wafers |
-
1990
- 1990-11-15 JP JP02309437A patent/JP3086958B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04180675A (en) | 1992-06-26 |
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