JPH03232239A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a disconnection of the contact parts of wirings on a source and a drain from being generated and to prevent the generation of the kink characteristics of an element by a method wherein a pair of first grooves and a second groove shallower than the first grooves are respectively formed in the surface of a single crystal silicon substrate and in the substrate surface between the first grooves by a photolithography method. CONSTITUTION:A photoresist film 12 is formed on a substrate 11, the substrate is etched by a reactive ion etching(RIE) method in a depth of about 15nm using this film 12 as a mask and a second groove 20 is formed. This groove is finally used as the bottom of a channel. Then, the film 12 is removed and after that, a photoresist film 14 is formed and the substrate 11 is etched by an RIE method in a depth of above 20nm using this film 14 as a mask to form first grooves 15. These grooves are finally used as bottoms other than the bottom of the channel part. Then, an oxide layer 22 and a polycrystalline silicon layer 17 are formed on the substrate 11 to obtain a flat surface. Then, another Si substrate 21 is laminated on the layer 17 in an atmosphere of 1100 deg.C, the rear 11b of the substrate 11 is subjected to mechanical polishing, then, the rear 11b is subjected to chemical polishing to perform the exposure of the layer 22.

Description

[Detailed description of the invention] (b') Industrial application fields The present invention relates to a method for manufacturing a semiconductor device.

For more details, please visit S OI (Si on In5ula)
tor), and is particularly suitable for manufacturing large-scale integrated circuits with high-speed response.

(B) Conventional technology The conventional method for manufacturing a Sol element is as shown in FIG.
Film thickness of 50 mm by laser beam, electron beam, oxygen injection, etc.
A thick film SOI substrate of approximately 0++a+ is fabricated, and then thermal oxidation and dry etching are performed to achieve a film thickness of 100.
A thin film SOI substrate with a thickness of ~200 nm is obtained and an element is incorporated therein. However, 11 is a silicon substrate, 12a and 12b are diffusion layers, 12c is a channel part,
13 is an insulating film, 16 is a wiring, 18 is a gate electrode, and 19 is a gate insulating film.

In recent years, it has been discovered that ultra-thin film SOI devices with a film thickness of about 30 to 100 m thick have higher driving force without the occurrence of king characteristics than thin-film SOI devices with conventional film thicknesses, making it possible to realize ultra-high-speed devices. Let's be Shome Sae for the sake of this.

(c) Problems to be Solved by the Invention In the above-mentioned thin film So2 device, a problem arises in that the resistance to drain breakdown decreases. For example, the channel length is 0°5μm
Sol film thickness 50 nm in n-channel trannostar
Comparing the device characteristics of 200r++n and 200r++n, the breakdown voltage of the 50nm device is about 1.5μ lower. The reason for this is
This is thought to be because the curve of the equipotential line near the drain becomes smaller as the film thickness becomes thinner. Furthermore, since Si is thin in a 50 nm element, Si reacts with the wiring at the junction with the wiring, and Si diffuses into the wiring, creating a cavity and easily causing disconnection symptoms.

This invention has been made to solve the above problems, and is a thin film SO which has high reliability against voltage drop and disconnection failure, does not generate king characteristics, and has high driving force.
The present invention aims to provide a method for manufacturing a semiconductor device consisting of an L element.

(d) Means for solving the problem According to the second invention, (a) on the surface of a single crystal silicon substrate,
A pair of first grooves and a second groove shallower than the first groove are formed between them by a photolithography method, and (b) an insulating film is formed on the surface of the substrate including the inside of these grooves, and burying polycrystalline or amorphous silicon or a compound thereof in the groove; (C) then removing the back surface of the substrate until it reaches the insulating film at the bottom of the first groove; and forming a single crystal silicon element formation region isolated by the insulating film, (d) forming a channel in the single crystal silicon opposite to the second groove formation region in the single crystal element formation region; There is provided a method for manufacturing a semiconductor device, characterized in that a gate electrode is laminated via a gate insulating film, and a source and a drain are formed in single crystal silicon on both sides of the gate electrode.

In this invention, a pair of first grooves are formed on the surface of a single-crystal silicon substrate by photolithography, and a first groove is formed between the two grooves.
A second groove shallower than the groove is formed. The first groove is separated by an insulating film on the back surface of the single-crystal silicon substrate and constitutes a region for forming an f-2 quasi-antagonistic silicon element, and usually has a depth of 030 to 0.55 um.

It consists of a pair of grooves having a width of 0 and a cross section of 54 m or less, and can be formed on the substrate surface by a known photolithography method. The distance between this pair of grooves is usually 1.0
It can be less than μm. The second groove is for forming a thin film channel in the single crystal element formation region, and corresponds to the thickness of the thin film channel intended to be formed with respect to the depth of the first groove. It is suitable to form it as shallow as 0.25 to 0.55 μm in depth and 0.5 μm in width.
Grooves having a cross section of less than μm can be formed between the l pair of first grooves.

In this invention, an insulating film is formed on the surface of the substrate including inside these grooves, and polycrystalline or amorphous silicon or a compound thereof is buried in these grooves. The insulating film is for configuring an isolated single-crystal silicon element formation region, and is applied to the surface of the substrate including the inside of the first and second grooves by a method such as a thermal oxidation method or a CVD method. Silicon oxide, silicon nitride, etc. can be formed and used according to an appropriately selected method. Further, the thickness of this insulating film is usually suitably 0.3 to 1.0 μm. The above-mentioned polycrystalline but non-crystalline silicon or a compound thereof can be used by being buried in the groove in which the above-mentioned insulating film is formed, as it is a part that supports the above-mentioned single-crystal silicon element forming region. It can be formed by laminating it on an insulating film by, for example, a CVD method, a sputtering method, or the like. Since this laminated layer is usually used with another substrate attached thereon, it is preferable to form the surface flat.

According to this invention, the back surface of the substrate is then removed until it reaches the insulating film at the bottom of the first groove, thereby removing the single crystal silicon element formation region located between the first grooves and isolated by the insulating film. Configure. The purpose of removing the back surface of the substrate is to form a single-crystal silicon element formation region isolated by an insulating film, and can be performed by, for example, polishing, grinding, etc. until the insulating film at the bottom of the first groove is reached. . Also, this removal may be performed first by a high-speed polishing method up to the vicinity of the insulating film, and then by a selective polishing method until reaching the insulating film. Examples of the high-speed polishing method include IN polishing. Examples of the selective polishing method include chemical polishing. By removing the back surface of the substrate, an f single-crystal silicon element forming region is formed isolated by an insulating film formed in a region including the first and second grooves.

This single-crystal element forming region has an uneven shape with respect to the outer surface because the inner bottom part thereof has a protrusion of the second groove forming part in the central part, and the thickness of the central part is usually 30 to 6 (lnm), and the thickness on both sides thereof is uneven. The thickness can be usually 0.4 to 0.6 μm.

In the present invention, a channel is formed in the single crystal silicon in the single crystal element forming region opposite to the second groove forming region, and a gate electrode is laminated thereon via a gate insulating film, and a gate electrode is laminated on both sides of the channel. A semiconductor device is manufactured by forming a source and a drain in single crystal silicon.

The channel can be formed by doping impurities into the single crystal silicon facing the second groove formation site by a known method, and is usually 30 to 60 nm thick.
It has a thickness. By setting the thickness within the above range, it is possible to form a fast-responsive element with high driving force without the occurrence of king characteristics.

The gate electrode is formed by laminating layers of polycrystalline silicon, tungsten solicide, etc., with a gate insulating film interposed therebetween,
It can be formed by etching into a predetermined shape using a photolithography method.

This shape usually has a width of 08 μm or less and a thickness of 0.2 to 0.4
It has a cross section of μm. The source and drain can be formed, for example, by using the gate electrode as a mask and implanting impurities into the single crystal silicon on both sides of the gate electrode by a known method.

(E) Effect: Form a thick source and drain in the first trench to prevent disconnection of the wiring contact portion on the thick source and drain, and also make the second trench deep with the first trench. A thin channel corresponding to the difference in height is formed, and 6) the thin channel element prevents the occurrence of kick characteristics and leads to a higher driving force.

(f) Actual Speed Example FIG. 1(a) is an explanatory diagram showing the structure of a MOS type semiconductor device according to an embodiment of the present invention. This semiconductor device is
Substrate 11, insulating film 13, and diffusion layer 121! 2b, a gate electrode 18, and a wiring layer 16. Here S
01 layer is 12a, 12b, 12c. Figure 1(b)
and (c) are explanatory plan views of FIG. 1(a), in which various channel widths (Wl, W2) and arrangement of elements are mixed.

FIG. 2 is an explanatory diagram for explaining this manufacturing process. As shown in FIG. 2(a), about IAtm is placed on the substrate 11.
A thick photoresist film 12 is formed, and using this as a mask, reactive ion etching (RI) is performed to a depth of approximately 15 nm.
The second groove 20 is formed by etching according to step E). This second groove 20 ultimately becomes the bottom of the channel. Next, as shown in FIG. 2(b), after removing the photoresist film 12, a photoresist film 14 is formed again, and using this as a mask, the base plate is etched to a depth of about 20 nm by RIE. 1 groove 15 is formed. The second first groove 15 ultimately becomes the bottom of the portion other than the channel portion.

Next, as shown in FIG. 2(c), an oxide layer 22 with a thickness of 05 μm and a polycrystalline Si layer with a thickness of 54o++ are formed on the substrate 11.
Form layer I7 to obtain a flat surface. However, the oxide layer 22
may be formed by a thermal oxidation method or a CVD method, but a combination of a thermal oxidation method and a CVD method is preferred from the viewpoint of surface flatness and Si/310w interface characteristics.

Next, as shown in FIG. 2(d), a polycrystalline Si layer 17 is formed.
Then, another Si substrate 21 is bonded together in an atmosphere of 1100°C. In this case, oxide layers may be attached to both surfaces.

Next, as shown in FIG. 2(e), the back surface zb of the substrate 11 is
is polished at high speed by mechanical polishing.

Next, as shown in FIG. 2(f), selective polishing is performed by chemical polishing. Polishing is stopped when the oxide layer 22 is exposed. Here, the thickness of the region 23 that becomes the channel portion and the region 24 other than the channel portion are 50 nm and 200 nm, respectively.
m. In these processes, the element isolation process is automatically realized. Using this board, normal M
By forming a desired element through an OS FET manufacturing process, a semiconductor device as shown in the first [ffl] is manufactured.

The obtained semiconductor device had an ultra-thin channel portion, a thin film structure in areas other than the channel portion, and had a high response speed and high reliability. It should be noted that the present invention is not limited to the above embodiments, and can be implemented with various modifications without departing from the spirit thereof.

(G) Effects of the Invention According to the present invention, a semiconductor device comprising a thin film SO element has high reliability against voltage drop and disconnection failure, does not generate kink characteristics, and has high driving force (high speed response). A manufacturing method can be provided.

By using the method of the present invention, a large scale integrated circuit semiconductor device with high speed response can be manufactured.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a semiconductor device manufactured according to an embodiment of Toji's invention, FIG. 2 is an explanatory diagram of the manufacturing process, and FIG. 3 is an explanatory diagram of a conventional semiconductor device. 11...Substrate, 12...Photoresist film, 12a, 12b...Diffusion layer, 12c...Channel portion, 13...Insulating film,
14... Photoresist film, 15... First
Groove, 16... Wiring, 17... Polycrystalline Si
Layer, 18... Gate electrode, 19... Gate insulating film, 20... Second groove, 21... Si substrate, 22... Oxidation layer,
23... Area that will become the channel part, 24...
・Area other than the channel part. (a) Wei 918 Bo (a) Fig. 2 (C) Fig. (d) Flash (f) Fig.

Claims (1)

[Claims] 1. (a) forming a pair of first grooves and a second groove shallower than the first grooves therebetween by photolithography on the surface of a single-crystal silicon substrate; (b) forming these grooves; (c) After that, an insulating film is formed on the surface of the substrate including the first trench, and polycrystalline or amorphous silicon or a compound thereof is buried in these trenches; By removing the film until it reaches the film, a single crystal silicon element formation region located between the first grooves and isolated by the insulating film is formed; (d) forming the second groove in the single crystal element formation region; A channel is formed in the single crystal silicon facing the region, a gate electrode is laminated thereon via a gate insulating film, and a source and a drain are formed in the single crystal silicon on both sides. A method for manufacturing a semiconductor device.