JP2000031490A - Manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To self-aligningly form two gates of MOS transistors which are disposed on the upper and lower sides of an SOI(Si-on-insulator) layer, without limiting the degrees of design freedom. SOLUTION: For forming a first gate 10c on an insulation film 6 formed on a support substrate 14, its preliminary pattern 10 is formed thicker than desired final width, a semiconductor active layer 2a and second gate electrode 18 are formed thereon through insulation films 8, 16 inserted between the layers, both side parts not masked with the second gate electrode 18 are etched down, starting from the surface, to expose a part of the preliminary pattern 10, and the exposed preliminary pattern 10 is etched (may be insulated by the oxidation, etc.), to obtain a first gate electrode 10c having final width. The partial exposure of the preliminary pattern 10 is pref. by the etching using sidewalls 22 (and 24) formed on the side faces as a self-aligning mask, after forming the second gate electrode 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, SOI (Sil)
The present invention relates to a method for manufacturing a semiconductor device having a semiconductor active layer of an insulating layer separation type such as an (icon on insulator) layer, and two gate electrodes disposed on both sides in the thickness direction of the semiconductor active layer via an insulating film.

[0002]

2. Description of the Related Art An SOI structure facilitates complete isolation between elements and between a substrate and a soft error or CM.
It is known that latch-up specific to the OS can be suppressed.
Consideration has been given to increasing the speed and reliability of transistors and LSIs.

The silicon active layer in this SOI structure is buried in an insulating layer, so that elements can be formed on both sides in the thickness direction of the active layer. Therefore, it is easy to three-dimensionally arrange the elements, and studies on high integration of an LSI using an SOI structure have begun. Also,
2. Description of the Related Art In recent years, a MOS transistor is formed by arranging a normal gate electrode to which a signal is applied, above an active layer, in a so-called “XMOS”. A MOS transistor having a gate electrode for controlling a value voltage has been proposed.

Conventional Example 1 FIG. 12 is a sectional view showing a structural example of a MOS transistor having two gate electrodes. The MOS transistor 100 is formed on an SOI substrate manufactured by a so-called bonding method (hereinafter, referred to as a bonded SOI substrate). In FIG. 12, reference numeral 112 denotes a support substrate, 102a denotes a silicon active layer obtained by polishing a substrate to be polished from the back surface, and 110 denotes a polysilicon layer which becomes an adhesive layer when both substrates are bonded.

[0005] Insulating films 104 and 108 are interposed between the silicon active layer 102a and the polysilicon layer 110, and a first gate electrode 106 is buried therebetween. The insulating film 104 functions as a gate insulating film of the first gate electrode 106. A second gate electrode 116 is formed on the polished surface (upper surface) of the silicon active layer 102a with a gate insulating film 114 interposed therebetween. This second gate electrode 11
The source / drain impurity regions 102b having a high impurity concentration are formed in the silicon active layer 102a on both sides of the wiring 6, and the wiring layers 118 are connected to the respective regions.

FIGS. 10 and 11 show the bonding S
FIG. 3 is a diagram showing a process of manufacturing a MOS transistor using an OI substrate. FIG. 10A is a plan view when a first gate is formed in an insulating layer on a substrate to be polished. Also,
FIG. 10A-2 is a sectional view taken along line AA ′ of FIG. 10A-1, and FIG. 11 is a sectional view taken along line BB ′ of FIG. is there.

In FIG. 10, a projection 102a which will later become a silicon active layer is formed on the surface of a substrate 102 to be polished made of a silicon wafer. First gate insulating film 10 on the entire surface
4 is formed, and a first gate electrode 106 having a predetermined pattern is formed thereon. An insulating film 108 is deposited on the entire surface,
The gate electrode 106 is embedded in the insulating film.

In FIG. 11B, the substrate 1 to be polished is
A polysilicon film 110 is formed on the substrate 02 and bonded to a support substrate 112 such as a silicon wafer. And
CMP (Chemical Mechanical Pol)
ishering), and the substrate 10 to be polished 10
Remove almost 2 The protrusions 102a are separated from each other, thereby forming a silicon active layer embedded in the insulating film.

In FIG. 11C, a second gate insulating film 114 and a film serving as a second gate electrode, for example, a polysilicon film 116a are formed on the polished surface.

In FIG. 11D, a polysilicon film 1 is formed.
The second gate electrode 116 is formed by patterning 16a by etching using a photoresist or the like as a mask. At this time, the width (gate length) F of the second gate electrode 116 is usually set smaller than the width FF of the first gate electrode.

Thereafter, source / drain impurity regions 102b are formed in the silicon active layer 102a by ion implantation using the second gate electrode as a mask, and a contact hole is opened in the second gate insulating film 114. Layer 1
18 are formed to complete the basic structure of the MOS transistor shown in FIG.

Conventional Example 2 FIGS. 14 and 15 show a method of manufacturing a MOS transistor in which an active region of a buried gate electrode (first gate electrode) is determined in a self-aligned manner with respect to a second gate electrode.

In FIG. 14 and FIG.
Denotes a support substrate, 124 denotes a substrate isolation insulating film, and 126 denotes a silicon layer to be a first gate electrode. This MOS structure is
Substrate bonding method similar to that of Conventional Example 1 described above, or
SIMOX (Separation by Implanted Oxygen) that forms a buried oxide film in the deep part of the substrate by implanting high-concentration oxidizing species (oxygen ions) into the silicon substrate and heating it
It is formed by a method. Hereinafter, it is assumed that the silicon layer 126 is made of polysilicon on the assumption of the substrate bonding method.

Thereafter, a first gate oxide film 128 is formed on the polysilicon layer 126, and a polysilicon layer 130a serving as a silicon active layer is formed thereon. The thickness and impurity concentration of the polysilicon layer 126 are set such that the work function difference between polysilicon and silicon oxide (the first gate oxide film 128) depletes the entire region of the polysilicon layer in the thickness direction. ing.

In FIG. 14B, a polysilicon layer 1 is formed.
The silicon active layer 130 is formed by patterning 30a, and the element isolation insulating layer 132 is embedded between adjacent active layers. Then, a second gate oxide film 134 and a polysilicon layer 136a to be a second gate electrode are formed on the entire surface. During or after this film formation, the polysilicon layer 13 is formed.
Impurity is introduced into 6a to make it conductive.

In FIG. 14C, for example, a silicon nitride film serving as a mask layer is formed on the entire surface, and a polysilicon layer 136a as a lower layer is patterned to form a second gate electrode 136 and a mask layer 138. Obtain a laminated pattern.

In FIG. 15D, the formed laminated patterns 136 and 138 are used as a self-alignment mask,
(Phosphorus) ions are implanted. The energy of this ion implantation is set to a value such that the peak value of the impurity concentration enters the polysilicon layer 126 below the stacked patterns 136 and 138, and almost no additional ion implantation is performed in the region of the polysilicon layer 126 around the polysilicon layer 126. Is done. Generally, the penetration depth (projection range Rp) of the implanted ions depends on the material to be transmitted in addition to the energy.
8 and the material of the mask layer 138 are also considered. Further, the concentration of the ion implantation is set to a value that can sufficiently increase the conductivity in the region below the stacked patterns 136 and 138 of the polysilicon layer 126.

As a result, ions are implanted into a region shown by a broken line in FIG.
As shown in (e), an active region 126a of a polysilicon layer functioning as a first gate electrode is formed in a self-aligned manner with respect to the second gate electrode 136. This active area 126
The polysilicon region around a is always a depleted high resistance layer.

Thereafter, similarly to the conventional example 1, the source / drain impurity region 130a is formed, the second gate oxide film 134 is opened, and the wiring layer 140 is formed.
Complete the basic structure of the transistor.

[0020]

However, the methods of manufacturing the MOS transistors shown in the prior art examples 1 and 2 have the following problems.

In the first conventional example, since the second gate electrode 116 is positioned with respect to the first gate electrode 106 by mask alignment, there is a problem of misalignment between gates. That is, in the photolithography process at the time of forming the second gate electrode 116 in FIG. 11D, alignment of the photomask is performed using a mask alignment target formed in advance in the wafer. It depends on the mechanical accuracy of the exposure apparatus. Therefore, it is necessary to provide sufficient alignment margin in consideration of other factors, for example, pattern transfer accuracy by photoresist and etching.

In the first conventional example, the second gate electrode 11
The width of 6 (gate length) is set as the minimum dimension F of the design rule, and the width FF of the first gate electrode 106 is set to be larger than F in advance, so that the alignment margin is secured.
This alignment margin is about F / 3 on one side. Further, the source / drain impurity region 102b is formed using the second gate electrode 116 as a self-aligned mask. Therefore, the overlap between the source / drain impurity region 102b and the first gate electrode 106 cannot be avoided.
As a result, the parasitic capacitance between the gate and the source or drain on the first gate electrode side is large.

On the other hand, if the overlap is set small to reduce the parasitic capacitance value, a space may be generated between the source / drain region 102b and the first gate electrode 106 as shown in FIG. When this occurs, the electric field of the gate electrode does not reach the active region in the space portion, and as a result, the channel has a high resistance, and the transistor characteristics deteriorate, or the transistor does not operate normally.

Conventional Example 2 is proposed as a self-aligned manufacturing method for avoiding such misalignment between gate electrodes. However, this method has a problem in controllability of ion implantation. In the step shown in FIG.
The ion implantation into the polysilicon layer 126 buried in the insulating film and serving as the first gate electrode is performed by the second gate electrode 13.
6 It is necessary that the lower region is sufficiently doped with impurities. At this time, the condition is that the impurity is not doped into the silicon active layer 130 thereon, and even if doped, the doping amount does not affect the channel concentration to a practically problematic level. Therefore, the thin first gate oxide film 12
8, a steep impurity concentration profile must be achieved.

On the other hand, a region 126a to be the first gate electrode
It is a condition that the impurity doping amount of the region of the polysilicon layer 126 other than the other region is small enough to deplete the entire region in the film thickness direction. Further, as described above, the impurity amount for depleting the region may be defined by the initial concentration of the polysilicon layer. In this case, it is necessary that no additional ion implantation is performed on the depleted region. Becomes

As described above, in the ion implantation performed on the polysilicon layer buried in the substrate after the MOS structure is completed, all the conditions described above must be satisfied. difficult. Further, in order to satisfy all the conditions described above, the ion species to be implanted, the material and thickness of the layers 136 and 138 serving as the ion implantation mask, and the first
The thickness of the polysilicon layer 126 serving as a gate electrode is restricted. For this reason, the MOS transistor shown in Conventional Example 2 has disadvantages in that the degree of freedom in device and process design is limited, and that it is difficult to manufacture.

It is an object of the present invention to provide a method of manufacturing a semiconductor device which can easily apply a self-aligning positioning method when forming a buried gate electrode with respect to an upper gate electrode without suffering the above disadvantages. Aim.

[0028]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: an active layer of a semiconductor embedded in an insulating layer on a supporting substrate; and an insulating layer between the active layer and the supporting substrate. A method for manufacturing a semiconductor device, comprising: a first gate electrode embedded in a layer and facing a lower surface of the active layer; and a second gate electrode formed on the insulating layer and facing an upper surface of the active layer. In the first manufacturing method, when forming the first gate electrode, a preliminary pattern of the first gate electrode is formed to be thicker than a desired final width, and an insulating film is interposed between the preliminary pattern and an interlayer to form the active pattern. A layer and the second gate electrode are formed, and both sides not masked by the second gate electrode are dug down from the surface by etching to expose a part of the preliminary pattern, and the preliminary pattern is etched from the exposed surface. The final width of the first
Obtain a gate electrode. In the second manufacturing method, a part of the preliminary pattern is insulated (eg, oxidized or nitrided) to obtain the first gate electrode having a final width.

In these manufacturing methods, a so-called substrate bonding method may be used to form an active layer in an insulating layer on a supporting substrate. Also, in order to easily achieve self-alignment between the gate electrodes, preferably, after the formation of the second gate electrode, a first sidewall is formed on the second gate electrode, and the first sidewall is self-aligned. A part of the preliminary pattern is exposed by etching used as a matching mask. Further, when the active layer is exposed during etching for exposing a part of the preliminary pattern, the active layer portion is etched off, and a second sidewall is formed on a side surface of the active layer after the etch-off. The insulating pattern underlying the active layer may be etched to expose the preliminary pattern. This is because the active layer is protected by the second sidewall when the preliminary pattern is etched or insulated thereafter. In this case, the first and second sidewalls may be formed from materials having different etching rates. This is because the second gate electrode is not exposed at the time of etching back when the second sidewall is formed, and the second sidewall may be selectively removed later.

In the first manufacturing method, after the formation of the first gate electrode, an isolation insulating layer is formed on a side surface of the first gate electrode, the second sidewall is removed, and a trench formed by the second etching is formed. Then, a conductive layer that contacts the side surface of the active layer may be embedded. This is because the conductive layer is used as a source or drain extraction electrode layer. In this case, the isolation insulating layer may be formed of a material that is not etched when the second sidewall is removed or has a low etching rate. For the same purpose, in the second manufacturing method, after the insulation, the second sidewall is removed, and a conductive layer that is in contact with a side surface of the active layer is buried in a groove formed by the etching. Good.

In the first manufacturing method, in the etching of the preliminary pattern, the exposed portion of the preliminary pattern is etched off by anisotropic etching, and both ends in the width direction of the preliminary pattern after the etching off are isotropically. It is good to etch. This is because the amount of isotropic etching can be reduced, and a desired final width can be easily obtained. For the same reason, in the second manufacturing method, after the etching, the exposed portion of the preliminary pattern may be etched off by anisotropic etching, and both ends in the width direction of the preliminary pattern after the etching off may be insulated. .

In the second manufacturing method, the preliminary pattern may be formed from polysilicon, and the second sidewall may be formed from a material having a different etching rate from silicon oxide. This is because the insulated portion of the spare pattern is not receded when the second sidewall is removed.

In the method of manufacturing a semiconductor device according to the present invention, when the first gate electrode is embedded in the insulating layer, it is formed as a preliminary pattern having a large width, and is formed from the surface after forming the second gate. After excavating both ends in the width direction by etching, the final width is reduced by etching (or insulating). For this reason, the distance from the second gate at the location to be etched at both ends in the width direction of the second gate is important for adjusting the relative position between the gates.

In the manufacturing method of the present invention, the position of the etching portion can be positioned on the surface, so that the alignment can be easily performed even when performing normal mask alignment using a mask alignment target. In Conventional Example 1, the first gate electrode is aligned with the projection of the substrate to be polished, and the mask alignment target at that time is necessarily embedded in the insulating film, like the first gate electrode. For this reason,
It is difficult to perform alignment when forming the second gate electrode with respect to the first gate electrode. Further, in order to perform alignment on the surface, it is necessary to use a mask alignment target formed at the time of forming the active layer (projection), but this lowers the alignment accuracy. On the other hand, in the manufacturing method of the present invention, the position of the etching portion that determines the relative position between the gates can be determined using the mask alignment target formed at the time of forming the second gate electrode, and the alignment between the gates is easy.

In the manufacturing method of the present invention, for example, a self-aligning positioning method using a sidewall can be easily applied. When the sidewalls are used, etching can be performed at substantially equal positions on both sides of the second gate electrode, and by using anisotropic etching, even if the inner wall of the etching groove is slightly tapered, the center of the second gate electrode can be obtained. The preliminary pattern appears at a position symmetrical with respect to the axis. For this reason,
In the etching (or insulation) of the next preliminary pattern, the etching (or insulation) proceeds uniformly from both ends in the width direction,
The relative position between the gates hardly shifts. In the etching (or insulation), there is a strict variation, but the variation at such a close place as to be regarded as the same location on the wafer surface is extremely small, and this is a problem. Absent. Further, by adjusting the etching amount (insulating amount), the width of the first gate electrode can be arbitrarily set. Therefore, the amount of overlap between the source or drain and the gate can be controlled to reduce the parasitic capacitance. Furthermore, as long as the cross-sectional structure of the portion to be etched is the same, there is no restriction on the film thickness and material of each layer as in Conventional Example 2.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings.

First Embodiment FIGS. 1 to 7 are plan views or sectional views showing the steps of manufacturing a semiconductor device (MOS transistor) according to this embodiment.

In FIG. 1A, a substrate 2 to be polished such as a silicon wafer is prepared. In FIG. 1B, on the surface of the substrate 2 to be polished, a projection 2a to be a silicon active layer later is formed. An insulating layer 4 in which a preliminary pattern of the first gate electrode is buried is formed on the entire surface, and the insulating layer 4 is covered with a polysilicon layer 12 serving as an adhesive layer when the substrates are bonded.

FIG. 4B-1 shows a pattern after the formation of the insulating layer 4. FIG. 4 (b-2) shows the state shown in FIG.
A cross section taken along line AA ′ of 1) is shown in an enlarged manner. As shown in FIG. 4B-2, the insulating layer 4 includes a thin first gate insulating film 6 and a relatively thick insulating film 8 thereon. The first gate insulating film 6 is made of, for example, a silicon oxide film of about 10 nm, and the insulating film 8 is made of, for example, a silicon oxide film of about 300 nm. Between these two insulating films 6 and 8,
A preliminary pattern 10 for the first gate electrode is formed.
As shown in FIG. 4 (b-1), the preliminary pattern 10 is formed relatively thick in the effective gate portion 10a (the portion on the protrusion 1a of the substrate to be polished). The effective gate portion 10a of the preliminary pattern has a width W in the gate length direction, and is a portion where the width W is later processed by etching. The width W of the effective gate portion 10a is determined by the minimum line width F of the design rule, which is the width of the second gate electrode formed later.
Then, at least, it is set to be larger than (F + 2ΔF = 5F / 3). The portion 10b of the preliminary pattern 10 other than the effective gate portion is the same as in the prior art (FIG. 10A-1).
See, for example, a relatively thin final shape.

In FIG. 2C, the polysilicon layer 12
The surface is planarized by, for example, CMP. And FIG.
In (d), after the substrate to be polished 2 is bonded to the support substrate 14 prepared in advance from the planarized polysilicon layer 12 side (front side), the adhesive strength is increased by heat treatment.

In FIG. 3E, the wafer peripheral portion on the side of the substrate to be polished 2 is ground and tapered. In FIG. 3F, the substrate 2 to be polished is thinned to some extent by grinding, and then polished by CMP. This CMP detects an end point when the insulating layer 4 is exposed, and stops polishing. At this time, the protrusions are separated from each other, thereby forming a silicon active layer 2a embedded in the insulating layer 4.

FIG. 5F-1 shows the silicon active layer 2
FIG. 5B is an enlarged cross-sectional view taken along line BB ′ shown in FIG.

Referring to FIG. 5G, a second gate insulating film 16 made of, for example, a silicon oxide film of about 10 nm is formed on the entire surface of the polished surface. Further, for example, a laminated film of a polysilicon film and a silicon nitride film is formed, and is patterned into a predetermined shape by etching using a photoresist or the like as a mask to form the second gate electrode 18 and the mask layer 20. . At this time, the width (gate length) of the second gate electrode 18 is formed, for example, with the minimum dimension F of the pattern rule.

In FIG. 5H, source / drain impurity regions 2b are formed in the silicon active layer 2a by ion implantation using the second gate electrode 18 and the mask layer 20 as a mask. Second gate electrode 18 and mask layer 20
A first sidewall 22 made of, for example, silicon oxide is formed on the side surface of the second gate insulating film 16 by anisotropic etching using the sidewall 22 as a mask.
Then, the silicon active layer 2a is processed.

In FIG. 6I, the silicon active layer 2a
The second sidewall 24 is formed on the side surface of the first gate insulating film 8 and the step facing the step. The second sidewall 24 has a role of protecting the silicon active layer 2a when the preliminary pattern 10 is later etched to the final width. Further, the second sidewall 24 needs to be selectively removed later. Therefore, the material of the second sidewall 24 is a layer of silicon oxide (for example,
6, 8, 16, 22), and in particular, a material having an etching rate different from that of the first sidewall 22, such as silicon nitride, is selected.

In FIG. 6J, the exposed portion of the first gate insulating film 8 and both ends in the width direction of the preliminary pattern 10 are etched off by anisotropic etching using the second sidewall 24 as a mask. . In this etching,
Although only the exposed portion of the first gate insulating film 8 may be etched, it is desirable to etch both ends in the width direction of the preliminary pattern 10 in advance in that the line width controllability by the next isotropic etching is enhanced. .

In FIG. 6K, the preliminary pattern 10 is isotropically etched to reduce its width. The etching amount at this time is adjusted, and the first gate electrode 10c having the final width F is obtained.

In FIG. 7L, an isolation insulating layer 26 is formed on the side wall of the first gate electrode 10c by, for example, thermal oxidation or thermal nitridation. When the formation of the isolation insulating layer 26 is performed by thermal oxidation or thermal nitridation, the above-described FIG.
In this case, it is necessary to set the width of the first gate electrode 10c to be slightly larger in consideration of the line width reduction due to the formation of the isolation insulating layer. Thereby, the width of the first gate electrode 10c after the formation of the isolation insulating layer becomes the final width F.

In FIG. 7 (m), the second sidewall 24 is selectively removed. At this time, it is important that other insulating films are not etched as much as possible. Therefore, when the second sidewall 24 is formed from a silicon nitride film, it is desirable that the material of the isolation insulating layer 26 be silicon oxide. After removing the second sidewall 24,
As a result, the end surface of the exposed silicon active layer 2a is sufficiently contacted, and the inside of the etching groove is filled with a conductive material.
A source / drain extraction electrode layer 28 is formed. The source / drain extraction electrode layer 28 is made of, for example, polysilicon or metal into which p-type or n-type impurities are introduced at a high concentration.

Thereafter, a source or drain wiring layer,
If necessary, an upper layer wiring is formed via an interlayer insulating layer, and the semiconductor device is completed through overcoat film formation, opening of a pad window, and the like.

Various modifications can be made to the above-described method for manufacturing a semiconductor device. For example, in the step of FIG.
Before etching the gate insulating film 16 and the silicon active layer 2a, a sidewall made of a different material from the first sidewall 22 may be formed on the outside, and etching may be performed using the double sidewall. After the etching, the outer side wall is removed, and the first gate insulating film 16 is removed.
When the outer portion of the side wall 22 is removed by etching, the silicon active layer 2a is in a state in which the silicon active layer 2a protrudes outside as shown in FIG. This method has the advantage that when the source / drain extraction electrode layer 28 is formed later, the contact area between the source / drain extraction electrode layer 28 and the source / drain impurity region 2b can be increased, and the contact resistance can be reduced.

In the method of manufacturing a semiconductor device according to the present embodiment,
When the first gate electrode is embedded in the insulating layer, it is formed as a preliminary pattern 10 having a large width. After the second gate electrode 18 is formed, the preliminary pattern is formed by using the first sidewall 22 formed on the side surface thereof. Etching is performed to expose both end portions in the width direction of 10 and a preliminary pattern is etched from the exposed portion to obtain a final shape. This first
By the method of positioning the etching portion using the side wall 22, the etching can be performed at substantially the same position on both sides of the second gate electrode 18, and even if the inner wall of the etching groove is slightly tapered by the anisotropic etching, the second
The preliminary pattern 10 appears at a position symmetrical with respect to the center axis of the gate electrode 18. Therefore, in the next etching of the preliminary pattern 10, the etching proceeds uniformly from both ends in the width direction, and the relative position between the gates hardly shifts. In these etchings, there is a strict variation, but the variation at such a close place as to be regarded as the same location on the wafer surface is extremely small, and this does not cause a problem. By adjusting the etching amount, the width of the first gate electrode 10c can be set arbitrarily. Therefore, the amount of overlap between the source or drain and the gate can be controlled to reduce the parasitic capacitance. Furthermore, it is sufficient that the cross-sectional structure of the portion to be etched is the same, and there is no restriction on the film thickness or material of each layer.

Second Embodiment FIGS. 8 and 9 are sectional views showing a main part manufacturing process of a method for manufacturing a semiconductor device according to the present embodiment. FIG. 8A corresponds to FIG. 6I, and the steps up to FIG. 8A are the same as the steps (FIGS. 1 to 6I) of the first embodiment.

In FIG. 8B, the exposed portion of the first gate insulating film 8 is etched off by anisotropic etching using the second sidewall 24 as a mask.

In FIG. 9C, the preliminary pattern 10 is thermally oxidized (or thermally nitrided) from the exposed portion to separate the insulating layer 30.
Is formed, whereby the width of the preliminary pattern 10 is reduced.
At this time, the amount of thermal oxidation (or the amount of thermal nitridation) is adjusted, and the first gate electrode 10c having the final width F is obtained.

In FIG. 9D, FIG.
In the same manner as in the step (m), the second sidewall 24 is selectively removed, and the silicon active layer 2
The source / drain lead-out electrode layer 28 is formed by sufficiently contacting the end face a and filling the etching groove with a conductive material.

Thereafter, a source or drain wiring layer,
If necessary, an upper layer wiring is formed via an interlayer insulating layer, and the semiconductor device is completed through an overcoat film formation, a pad window opening step, and the like.

In the method of manufacturing a semiconductor device, modifications similar to those of the first embodiment can be made. Further, in the step of FIG. 8B, a part of the preliminary pattern 10 may be etched similarly to FIG. 6J of the first embodiment, and thereafter, the process may proceed to the step of FIG. In this case, FIG.
In this case, the thermal oxidation amount (thermal nitridation amount) of the first gate electrode 10c may be small, and the line width controllability of the first gate electrode 10c is preferably increased.

In the method of manufacturing a semiconductor device according to the present embodiment,
As in the first embodiment, the first and second gate electrodes 10
The relative position between c and 18 hardly deviates, and the width of the first gate electrode 10c can be arbitrarily set by adjusting the amount of oxidation (the amount of nitriding), whereby the parasitic capacitance can be reduced.
Further, there are various advantages such as no limitation on the film thickness and the material of each layer. Also, compared with the first embodiment, the source / drain extraction electrode layer 28 does not need to be buried deep, and is easy to manufacture. In addition, since the isolation insulating layer 30 is thick in the lateral direction, the source or drain and gate in this portion are There is an advantage that the parasitic capacitance between them is small.

In the above-described first and second embodiments, the positioning of the etching portion for exposing the preliminary pattern is performed using the sidewall, but in the present invention, this positioning may be performed by ordinary mask alignment. . In this case, since the above-mentioned etching portion can be positioned on the surface, normal mask alignment using the mask alignment target is easy.

In Conventional Example 1, the first gate electrode is aligned with the projection on the substrate to be polished, and the mask alignment target at that time is necessarily embedded in the insulating film, like the first gate electrode. . For this reason, it is difficult to perform alignment when forming the second gate electrode with respect to the first gate electrode. Further, in order to perform alignment on the surface, it is necessary to use a mask alignment target formed at the time of forming the active layer (projection), but this lowers the alignment accuracy.

On the other hand, in the manufacturing method of the present invention, the etching position for determining the relative position between the gates can be determined by using a mask alignment target formed on the surface when the second gate electrode is formed. Is easy.

[0063]

According to the method of manufacturing a semiconductor device according to the present invention, there are few restrictions on the size and material of each part, the degree of freedom in designing devices and processes is high, and it is easy to manufacture. In addition, alignment when forming a buried gate electrode (first gate electrode) with respect to an upper gate electrode (second gate electrode) is easy, and in particular, application of a self-aligning positioning method such as when a sidewall is used. As a result, there is no relative displacement between the gates, and the parasitic capacitance can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views illustrating respective manufacturing steps of a semiconductor device according to a first embodiment of the present invention, up to formation of a polysilicon layer on a substrate to be polished.

FIGS. 2A and 2B are cross-sectional views illustrating respective manufacturing steps of the semiconductor device according to the first embodiment of the present invention, up to lamination of substrates.

FIGS. 3A and 3B are cross-sectional views illustrating respective manufacturing steps of the semiconductor device according to the first embodiment of the present invention, and show steps up to formation of a silicon active layer by polishing;

FIG. 4 is a view showing a semiconductor device according to the first embodiment of the present invention;
It is the expanded top view and sectional drawing in the process of (b).

FIGS. 5A and 5B are cross-sectional views showing the steps of manufacturing the semiconductor device according to the first embodiment of the present invention, and show up to the etching of the silicon active layer by the first sidewall.

FIGS. 6A and 6B are cross-sectional views illustrating respective manufacturing steps of the semiconductor device according to the first embodiment of the present invention, up to the final processing of the first gate electrode by etching a preliminary pattern;

FIGS. 7A and 7B are cross-sectional views illustrating respective manufacturing steps of the semiconductor device according to the first embodiment of the present invention, up to formation of a source / drain extraction electrode layer.

FIG. 8 is a cross-sectional view showing a process of manufacturing the semiconductor device according to the second embodiment of the present invention, which shows the process up to the etching of the first gate insulating film using the second sidewall.

FIG. 9 is a cross-sectional view showing a process of manufacturing the semiconductor device according to the second embodiment of the present invention, up to formation of a source / drain extraction electrode layer.

FIGS. 10A and 10B are a plan view and a cross-sectional view illustrating a process of manufacturing a MOS transistor using a bonded SOI substrate according to a conventional method (conventional example 1), up to formation of a polysilicon layer on a substrate to be polished.

FIG. 11 shows an M using the bonded SOI substrate of Conventional Example 1.
FIG. 9 is a cross-sectional view showing a manufacturing process of the OS transistor,
The steps up to the formation of the gate electrode are shown.

FIG. 12 shows an M using the bonded SOI substrate of Conventional Example 1.
FIG. 4 is a cross-sectional view when the basic structure is completed by an OS transistor manufacturing method.

FIG. 13 is a cross-sectional view for explaining a problem of Conventional Example 1.

FIG. 14 is a cross-sectional view showing a process of manufacturing a MOS transistor using an SOI substrate according to another conventional method (Prior art 2);
The process up to the formation of the second gate electrode is shown.

FIG. 15 shows an M using the bonded SOI substrate of Conventional Example 2;
FIG. 4 is a cross-sectional view when the basic structure is completed by an OS transistor manufacturing method.

[Explanation of symbols]

2 ... substrate to be polished, 2a ... protrusion or silicon active layer, 2
b: source / drain impurity region, 4: insulating layer, 6: first gate insulating film, 8: insulating film, 10: preliminary pattern of first gate electrode, 10a: effective gate portion, 10b: other portion, 10c ... 1st gate electrode, 12 ... polysilicon layer,
14 support substrate, 16 second gate insulating film, 18 second
Gate electrode, 20 mask layer, 22 first sidewall, 24 second sidewall, 26, 30 isolation insulating layer, 28 source / drain extraction electrode layer, W, F, FF
... line width.

Claims (16)

[Claims] An active layer of a semiconductor embedded in an insulating layer on a supporting substrate; and a first active layer embedded in the insulating layer facing the lower surface of the active layer between the active layer and the supporting substrate.
A method for manufacturing a semiconductor device, comprising: a gate electrode; and a second gate electrode formed on the insulating layer and facing an upper surface of the active layer, wherein the forming of the first gate electrode includes the step of forming the first gate electrode. Forming a preliminary pattern thicker than a desired final width, forming the active layer and the second gate electrode with an insulating film interposed between the preliminary pattern and the interlayer, and both sides not masked by the second gate electrode; A method of manufacturing a semiconductor device in which a portion of the preliminary pattern is exposed by etching a portion from a surface to expose the preliminary pattern, and the preliminary gate is etched from an exposed surface to obtain the first gate electrode having a final width. 2. A method according to claim 1, wherein after forming the second gate electrode, a first sidewall is formed on the second gate electrode, and a part of the preliminary pattern is exposed by etching using the first sidewall as a self-alignment mask. The method of manufacturing a semiconductor device according to claim 1, wherein 3. The preliminary pattern etching step, wherein the exposed portion of the preliminary pattern is etched off by anisotropic etching, and both ends in the width direction of the preliminary pattern after the etching off are isotropically etched. 13. The method for manufacturing a semiconductor device according to item 5. 4. When the active layer is exposed during etching for exposing a part of the preliminary pattern, the active layer portion is etched off, and a second sidewall is formed on a side surface of the active layer after the etch-off. 3. The method according to claim 2, wherein the preliminary pattern is exposed by etching an insulating film underlying the active layer. 5. The first and second sidewalls are formed of materials having different etching rates.
13. The method for manufacturing a semiconductor device according to item 5. 6. After the formation of the first gate electrode, an isolation insulating layer is formed on a side surface of the first gate electrode, the second sidewall is removed, and the active layer is formed in a groove formed by the second etching. The method for manufacturing a semiconductor device according to claim 4, wherein a conductive layer contacting the side surface is embedded. 7. The method according to claim 6, wherein the isolation insulating layer is formed of a material that is not etched when the second sidewall is removed or has a low etching rate. 8. A projection serving as the active layer is formed on a surface of a semiconductor substrate, the surface of the semiconductor substrate is covered with a first insulating film, and the preliminary pattern is overlapped with the projection on the first insulating film. Covering the formed preliminary pattern with a second insulating film, bonding the semiconductor substrate to the support substrate from the front surface, polishing the semiconductor substrate from the back surface until the protrusion is separated, and forming the active layer 2. The method according to claim 1, wherein a third insulating film is formed on the polished surface, and the second gate electrode is formed on the third insulating film above the active layer. 3. 9. A semiconductor active layer embedded in an insulating layer on a supporting substrate, and a first active layer embedded in the insulating layer and opposed to a lower surface of the active layer between the active layer and the supporting substrate.
A method for manufacturing a semiconductor device, comprising: a gate electrode; and a second gate electrode formed on the insulating layer and facing an upper surface of the active layer, wherein the forming of the first gate electrode includes the step of forming the first gate electrode. Forming a preliminary pattern thicker than a desired final width, forming the active layer and the second gate electrode with an insulating film interposed between the preliminary pattern and the interlayer, and both sides not masked by the second gate electrode; The portion is dug down from the surface by etching to expose a part of the preliminary pattern.
A method for manufacturing a semiconductor device for obtaining a gate electrode. 10. After the formation of the second gate electrode, the second gate electrode is formed.
The method of manufacturing a semiconductor device according to claim 9, wherein a first sidewall is formed on the gate electrode, and a part of the preliminary pattern is exposed by etching using the first sidewall as a self-alignment mask. 11. The semiconductor device according to claim 9, wherein after the etching, the exposed portion of the preliminary pattern is etched off by anisotropic etching, and both ends in the width direction of the preliminary pattern after the etching off are oxidized or nitrided. Manufacturing method. 12. When the active layer is exposed during etching for exposing a part of the preliminary pattern, the active layer is etched off, and a second sidewall is formed on a side surface of the active layer after the etch-off. The method of manufacturing a semiconductor device according to claim 10, wherein the preliminary pattern is exposed by etching an insulating film underlying the active layer. 13. The method according to claim 13, wherein the first and second sidewalls are
13. The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor devices are formed from materials having different etching rates. 14. The semiconductor device according to claim 12, wherein the second sidewall is removed after the oxidation, and a conductive layer that is in contact with a side surface of the active layer is buried in the groove formed by the etching. Method. 15. The method according to claim 14, wherein the preliminary pattern is formed of polysilicon, and the second sidewall is formed of a material having an etching rate different from that of silicon oxide. 16. A protrusion serving as the active layer is formed on a surface of a semiconductor substrate, a surface of the semiconductor substrate is covered with a first insulating film, and the preliminary pattern is overlapped with the protrusion on the first insulating film. Covering the formed preliminary pattern with a second insulating film, bonding the semiconductor substrate to the support substrate from the front surface, polishing the semiconductor substrate from the back surface until the protrusion is separated, and forming the active layer The method according to claim 9, wherein a third insulating film is formed on the polished surface, and the second gate electrode is formed on the third insulating film above the active layer.