JPS62272556A - Three-dimensional semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a 3-dimensional IC laminated in multiple layers in high yield by using a unit 3-dimensional element having a semiconductor circuit electrically connected through a conductor post passing through a semiconductor substrate on both sides of the substrate and connecting terminals led on an insulating film to be coated from the conductor circuits. CONSTITUTION:A 3-dimensional semiconductor integrated circuit device is composed to include a unit 3-dimensional semiconductor integrated circuit element A having semiconductor circuits 2a, 2b on both side surfaces of a semiconductor substrate 1 so that the circuits 2a, 2b are electrically connected by a conductor post 4 insulated from the substrate 1 through the substrate 1 and connecting terminals 6, 7 led from the circuits 2a, 2b on at least one of insulating film 5 to be coated of the films 5 for covering the circuits 2a, 2b. Thus, since the 3-dimensional ICs are formed of multilayer unit of the unit 3-dimensional IC element of both side structure, its integration density is improved. Since it has a laminated structure, good components can be sorted at every semiconductor circuit of each layer to be laminated, its manufacturing yield is improved.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example Structure Implementation A side sectional view of an example (Fig. 2) A process sectional view of an example of the manufacturing method (Fig. 3) A process diagram of forming a wiring contact portion (Fig. 4) A schematic diagram of a general example of FROM (
(Fig. 5) Schematic diagram of an application example of a mask ROM (Fig. 6) Effects of the invention [Summary] Conductor posts (
A three-dimensional semiconductor consisting of a unit three-dimensional semiconductor integrated circuit element, which has semiconductor circuits that are electrically connected to each other via (through-holes), and connection terminals are led out from each semiconductor circuit onto a covering insulating film. Integrated circuits and their manufacturing methods.

[Industrial application field]

The present invention relates to an improvement in a three-dimensional semiconductor integrated circuit device (IC) in which semiconductor integrated circuit devices are vertically stacked and highly integrated.

Conventional ICs are made of thick silicon (Si) (limited to a required thickness to avoid damage during process steps).
A half-quad circuit was formed on only one surface of the board.

High integration of the IC has been achieved by expanding the size of the chip, miniaturizing elements and wiring, and arranging them at high density.

However, with this method, the size of the chip is limited, which puts a limit on the degree of integration, so three-dimensional semiconductor ICs have been developed to further improve the degree of integration.

[Conventional technology]

Conventionally, the popular method for manufacturing 3D ICs is S C) 1 (Silicon On In5ula).
This is a method using the tor technology.

According to this method, an insulating film is grown in vapor phase on the lower semiconductor element, a polycrystalline silicon layer is grown in vapor phase on the insulating layer,
A three-dimensional tC is manufactured by recrystallizing the polycrystalline silicon layer by a method such as laser annealing and forming an upper semiconductor element on the recrystallized silicon layer.

However, with this method, it is difficult to form a high-quality recrystallized silicon layer with few grain boundaries with good reproducibility during laser annealing, making it extremely difficult to form three-dimensional ICs stacked in multiple layers with a high yield. There was a problem.

In addition, when trying to arrange a mask ROM in the three-dimensional IC, the process of forming contact windows, which corresponds to writing information, comes in the middle of the process of forming the three-dimensional structure. A problem arises in that the manufacturing process until shipment is extremely long.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention is that it is almost possible to improve the manufacturing yield by stacking three-dimensional ICs in multiple layers using the conventional method. (It is not practical because the yield would be reduced to a level of

[Means for solving problems]

The above problem is that semiconductor circuits (
2a) (2b) is formed, and the semiconductor circuit (2a)
(2b) is electrically connected to the semiconductor substrate by an insulated conductor post (4) penetrating the semiconductor substrate (1), and the coating covers the semiconductor circuits (2a) and (2b). Insulating film (5z) On the surface of at least one covering insulating film of u, the half-quad circuit (2a) (2
A three-dimensional semiconductor integrated circuit device according to the present invention, comprising a unit three-dimensional semiconductor integrated circuit element (A) having connection terminals (6) and (7) led out from b), and a non-through hole in the surface of the semiconductor substrate. forming a conductor post insulated from the semiconductor substrate on the semiconductor substrate by forming an insulating film on the inner surface of the non-through hole and filling the non-through hole with a conductor; forming a first semiconductor circuit electrically connected to the upper end of the true electric post on the surface of the substrate; forming a first covering insulating film on the semiconductor substrate; A step of leading out a connection terminal from the first semiconductor circuit on the surface of the film, and after pasting a support substrate on the semiconductor substrate, polishing the back surface of the semiconductor substrate to expose the lower end of the conductor post. forming a second semiconductor circuit electrically connected to the lower end of the conductive post on the back surface of the semiconductor substrate; and forming a second covering insulating film on the back surface of the semiconductor substrate. However, this problem is solved by the method of manufacturing a three-dimensional semiconductor integrated circuit device according to the present invention, which includes the step of leading out connection terminals from the second semiconductor circuit on the surface of the second covering insulating film.

[For production]

That is, according to the present invention, as shown in the principle diagram showing a schematic side cross section in FIG.
Since interconnected semiconductor circuits are formed on a single semiconductor substrate, the degree of integration of semiconductor circuits formed on a single semiconductor substrate is doubled, and furthermore, the unit three-dimensional ICs (A) can be drawn out on both sides of the semiconductor substrate. Since the semiconductor devices are electrically connected via the connecting terminals (6) and (7) and stacked, it is possible to form a three-dimensional IC (B) having a multi-layered structure with a high degree of integration.

Furthermore, since the semi-solid elements constituting the semiconductor circuits (2a) (2b) in each layer are all formed by the semi-integrated heavy crystal substrate (1), their characteristics are stable, and at the same time, the stacked structure (B) described above is achieved. Since characteristics can be selected for each layer of semiconductor circuits (2a) (2b), the manufacturing yield of multilayer three-dimensional ICs is greatly improved.

Furthermore, by obtaining the above-mentioned stacked structure (B),
Since the wiring on the bottom surface of the substrate (1) can be changed for each unit three-dimensional TC element (A) immediately before the stacking and laminating process, the ROM
It becomes extremely easy to change the wiring when changing information, etc.
The manufacturing time for a multilayer three-dimensional IC including a ROM is also greatly reduced.

〔Example〕

The present invention will be specifically described below with reference to illustrated embodiments.

FIG. 2 is a schematic side sectional view showing an embodiment of the structure of the present invention;
3(a) to +11 are process cross-sectional views showing one embodiment of the manufacturing method of the present invention, FIG. 4 is a process cross-sectional view showing a method for forming contacts between conductor posts and circuit wiring, and FIG. l) A schematic plan view (al) showing the structure of the ROM according to the present invention and a schematic side sectional view fbl, FIG. 6 shows the mask RO according to the present invention.
Circuit diagram of M (al, schematic side sectional view in case of information “1”)
FIG. 3 is a schematic side sectional view (C) in the case of bl and information “0”.

Identical objects are indicated by the same reference numerals throughout the figures.

For example, as shown in FIG. 2, a three-dimensional IC with a laminated structure according to the present invention has a first layer on a wiring board 46 made of ceramic or the like.
A unit three-dimensional IC element (A,) is fixed thereon, and a second unit three-dimensional IC element (A2) is further laminated and fixed thereon.

That is, the first unit three-dimensional IC element (A,) is, for example, p
A first semiconductor circuit including a first n-channel MOS transistor (Trl) is formed on the front surface of a type silicon (p-3i) substrate 1, and a second n-channel MOS transistor (Trl) is formed on the back surface.
A second semiconductor circuit including a transistor (Tr2) is formed, and the front and back surfaces are formed on interlayer insulating films 26 and 41 made of, for example, silicon dioxide (SiO□). The circuit wirings 27 and 42 are
-SiO through the Si substrate 1 and between the Si substrate 1 and the Si substrate 1
□A covering insulating film 29 that is electrically connected by conductor posts 4a and 4b made of n° type poly-Si insulated by the insulating film 3, and has a thermosetting silicone resin layer on at least the upper layer on the semiconductor circuits on both sides. .45, and connecting terminals made of aluminum (A1), for example, are connected from the lower circuit wiring 27.42 to the surface of the covering insulating film 29.45!
1) Thermocompression bonding terminals 6a, 6b, 7a, and 7b are respectively led out, and are electrically connected to the wiring board 46 made of ceramic or the like by thermocompression bonding means via 78.7b, and are coated with an insulating film. 45 is firmly fused and fixed via a thermosetting silicone resin layer.

The second unit three-dimensional 1c element (A2) includes thermocompression terminals 6a and 6b on the surface and a thermosetting silicone resin layer 29h.
The first unit three-dimensional Ic element (
The circuit structure is, of course, not necessarily the same as that of A, ), but the thermocompression terminal 6a of the first unit three-dimensional IC element (AI) is attached via the thermocompression terminals 7a and 7b by thermocompression means.
, 6b, and the covering insulating film 45 on the back surface.
The thermosetting silicone resin layer 2 on the surface of the first unit three-dimensional (C element (A,)
By being firmly fused and fixed to 9b, it is laminated on the first unit three-dimensional IC element (A,).

The three-dimensional IC of the present invention will be explained in more detail below with reference to its manufacturing method.

Referring to FIG. 3(a), the method of the present invention can be used, for example, to create a three-dimensional structure according to the structure of the present invention.
- When forming the MO3IC, non-through holes with a diameter of 2 to 4 μm and a depth of about 10 μm are formed at a plurality of predetermined positions on the surface 1a of the Si substrate 1 by a normal ion milling method or an active ion etching method. 21a
. The above-mentioned non-through hole 2 is formed on the substrate by a growth method.
An n-type poly-Si layer 104, which becomes a first conductor, is formed to a thickness that allows filling La, 21b, etc.

FIG. 3 (See BL) Next, etch hacking using isotropic dry enoneration means is performed to selectively remove only the poly-Si layer 104 on the top surface of the substrate 1, and then the SiQ□ insulating film on the top surface of the substrate 1 is etched by ordinary plasma etching. 3 is removed, and conductor posts 4a, 4b, etc. made of an n-type poly-Si layer 104 and insulated from the substrate 1 by the SiO□i colored edge film 3 are formed in the substrate 1.

Figure 3 (see C1) Next, a gate oxide film is formed by thermal oxidation, chemical vapor deposition (CVD) and reactive ion etching (
A gate oxide film 22, a poly-Si gate electrode 23, A first n source region 24 and an n type tray region 25
A channel MO3I-transistor ('rrl), and elements such as a resistor and a gear batter (not shown) are formed.

Then, an OS102 interlayer insulating film 26 having a thickness of about 5,000 layers, for example, is formed on the main surface by the CVD method.

FIG. 3 (di reference) Next, a contact window is formed in the layer spread edge film 26 by ordinary glue lithography technique, and then a contact window is formed by CVD method.
After forming a ゛-type polySt layer and patterning using normal glue lithography technology, poly-Si circuit wiring such as a source wiring s27, a drain wiring (not shown), other wiring 28, etc. is formed on the interlayer insulation +1!26. do. At this time, for example, the source wiring 27 is brought into contact with the upper end of the conductor post 4a, and the other wiring 28 is brought into contact with the upper end of the conductor post 4b through contact windows.

Next, a first covering insulating film (passivation film) 29a having a thickness of about 5,000 layers is formed by CVD on the main surface on which the wiring is formed, and then H3 (CI+3) is formed on the main surface by spin code method. :+SiOSiO(C113)y
O---------PMSS (C1h) :+SiOSi O(CI!3)koH
3. A second covering insulating film 29b made of a thermosetting silicone resin layer such as silylated polymethylsilsesquioxane (PMSS) having the molecular structure shown above is coated to a thickness that flattens the surface thereof.

Refer to FIG. 3(e). Next, the substrate is heated to about 100° C. and the above P? 'ls
After evaporating the solvent in the second covering insulating film 29b made of S, an aluminum (8L) layer 30 having a thickness of about 2,000 mm is formed as an etching mask on the second covering insulating film 29b. , an opening 31a corresponding to a thermocompression bonding terminal forming area is formed in the AI mask layer 30 by normal gluing lithography technique.
, 31b is formed, and the insulating film 2 is coated with oxygen plasma.
9b, then RI with CHF, gas, etc.
Openings 32 are formed in the covering insulating films 29a and 29b by E treatment to expose a portion of the polyst wirings 27 and 28, for example.
a, forming 32b.

Referring to FIG. 3(f), a metal layer 106 for thermocompression terminals, for example, an At layer 106, which is thicker than or equal to the covering insulating film 29, is then deposited on the main surface by vapor deposition or the like.
, and then the opening 32a of the A1 layer 106,
A resist 34 is embedded in the four portions 33 formed on the resist 32b through an etch pack process using a spin cord and Oz gas.

Referring to FIG. 3(g), the first layer 106 on the main surface is selectively etched away using the resist 34 as a mask, and then the resist 34 is removed to remove the covering insulating film 29.
At connection terminals, that is, thermocompression bonding terminals 6a and 6b, which are embedded in (29a and 29b) and are in contact with the source wiring 27 and other wiring 28', are formed.

FIG. 3 (See hl) Next, a supporting substrate 3 made of quartz or the like is coated with a thermoplastic or thermally decomposable resin such as polyimide 35 that can be peeled off by heat treatment in a humid atmosphere on the main surface (surface) side of the substrate.
6 is pasted, and the back surface of the silicon substrate 1 is polished by ordinary surface polishing means until the lower ends of the conductor posts 4a, 4b, etc. are exposed, and finally mirror-finished by a method such as mechanical chemical etching. do. At this time, the thickness of the silicon substrate is, for example, about 5 to 7 μm.

Next, a step of forming a device on the back side of the semiconductor substrate 1 begins, but in this back side device forming step, the semiconductor substrate 1 is placed on the support substrate 36 because the semiconductor substrate 1 is thin and weak.
It is done with the tape still attached.

Therefore, it is necessary to maintain adhesive strength by suppressing the decomposition of the adhesive resin such as the polyimide 35, and it is necessary to avoid increasing the substrate temperature.

Therefore, all heat treatments such as vapor phase growth and activation of the impurity-introduced region are performed by surface heating means achieved by short-time pulse irradiation such as a laser.

Refer to Figure 3 (i). First, monosilane (SiH
The silicon substrate 1 in a mixed gas of a) and oxygen (O, t)
Only the back surface of is heated to about 400 to 500°C by laser irradiation, and a gate SiO□ film 3 is deposited on the back surface by CVD method.
6 was formed, and then the pressure was reduced to about 100 Torr.
In a mixed gas of i 114 and phosphine (PH3), only the back surface of the substrate 1 is heated to about 600 to 650 ℃, and a 0-type poly-Si layer with a thickness of about 5000 is formed on the gate sio□ film 37. The second gate electrode 38 made of the n-type poly-Si layer is formed by back-cooning using ordinary lithographic means, and then the second gate electrode 38 made of the n-type poly-Si layer is formed on the back surface of the jAp-type silicon substrate 1 by ordinary selective ion implantation technique. Arsenic (As) is implanted in alignment with the gate electrode 38, and the ion-implanted region is heated to about 850 to 900° C. by laser irradiation to activate it, forming an n-type second source region 39 and a second drain. A region 40 is formed.

Refer to FIG. 3(J). Next, as described above, a laser beam is irradiated in a mixed gas of S i H, and 02 to form a layer of 0S with a thickness of about 5000 on the back surface of the substrate.
An iO□ interlayer insulating film 41 is formed, and then the Si is formed on the interlayer insulating film 41, for example, on the upper part of the second source region 39 including the upper part of the conductor post 4a, and on the second drain region 40.
A contact window is formed on the top of the substrate and on the top of the conductor post l-4b by normal lamination lithography, and then, as in section 1, laser irradiation is performed in a mixed gas of SiHa and PH to form a thick layer on the back surface of the substrate. About 5,000 people formed a 0S type poly-Si layer and patterned it by a normal method to form a second source wiring made of n type polySt and in contact with the source region 39 and the end surface of the conductor boss 4a. 42, a second drain wiring 43 in contact with the drain region 40 and a second other wiring 44 in contact with the end surface of the conductor post 4b are formed.

Figure 3 (see kl) Next, a layer of 1 μm thick was coated on the back side of the substrate using a spin code method.
A covering insulating film 45 made of a PMSS layer of about m is formed,
By a method similar to that explained in FIGS. 1(e) to (g), a thermocompression bonding terminal 7a and a second source wiring 42 made of At and leading out, for example, the second source wiring 42 to the surface of the M@R film 45 are bonded. A thermocompression bonding terminal 7b from which other wiring 44 is led out is formed.

Although not shown, the substrate is then cut into chip shapes by a method such as laser scribing to complete a unit three-dimensional IC element (A) with a double-sided structure. Note that the above-mentioned cutting is performed so as to reach the adhesive resin, that is, the polyimide layer 35.

In addition, when the above-mentioned three-dimensional three-dimensional IC element (8) is used exclusively as the uppermost element during stacking, the steps of forming the second covering insulating film 29b made of pPlss and forming the thermocompression terminals 6a and 6b on the front side are performed. is sometimes omitted.

Next, characteristics of each element (semi-dedicated circuit) are selected through the thermocompression terminals 7a, 7b, etc., and non-defective elements are marked or stored.

Refer to FIG. 3 fl) Next, when the three-dimensional tC is to be further integrated, the unit three-dimensional IC elements (AI), (A2), etc. are stacked and stacked.

First, a normal wiring board 46 made of ceramic or the like is heated to 400 to 450°C, and a good unit three-dimensional IC element attached to the support substrate 36 is placed on the wiring 47 of the wiring board 46. Thermocompression terminal 7a on the back side of (A,)
, 7b, etc., to electrically connect and fix them. The PMSS layer covering the back surface of this unit three-dimensional IC element as the covering insulating film 45 has the property of melting at 400°C and curing and solidifying with the passage of time. The original IC element (A1) is closely fixed on the covering insulating film, that is, the PMSS layer 45.

Next, the unit three-dimensional 1c element (8,
) from the back surface of the support substrate 36;
lOO~25 by irradiation with energy rays (L) such as laser
It is heated to about 0° C. in a humid atmosphere to peel off the adhesive resin, ie, the polyimide 35, and separate the thermocompression bonded unit three-dimensional IC element (8) from the support substrate 36.

Next, the polyimide adhering to the upper surface of the unit three-dimensional IC element (A,) is completely removed by oxygen plasma treatment or the like.

Refer to FIG. 2. Next, on the unit three-dimensional IC element (A1) heated to 200 to 250°C via the vA substrate, another good unit three-dimensional IC element (A2) is placed in the same manner as described above. The thermocompression bonding terminals 6a and 7a, 6b and 7b are aligned and thermocompression bonded to each other to electrically connect and fix them.

At this time, as described above, the PMSS layers 29b and 45 are melted and then solidified, so that the unit three-dimensional IC element (^,) and the unit three-dimensional IC element (A2) are firmly fused and fixed via the PMSSN. They are stacked in a stacked state.

Note that since the unit three-dimensional IC element (A2) is used only for the upper part during stacking, the PMSS on the upper surface (front surface) side
Layer 29b and thermocompression terminals 6a and 6b are not formed.

Next, the support substrate 36 is peeled off from the unit three-dimensional IC element (At) using the same method as described above.

In the structure of the present invention, if the conductor post is thin, the area around the tip of the conductor post should be avoided to avoid a short circuit between the circuit wiring and the board due to misalignment of the contact window of the interlayer insulating film with respect to the conductor post. A structure is used in which a recess is formed in the substrate surface, a coated insulating film such as PMSS is buried in the recess, and the tip of the conductor post and the circuit wiring are connected on the buried insulating film.

When using this structure, the method described below with reference to FIGS. 4 (al to (C1) is used.

4 (see al) A resist mask film 52 having an annular opening 51 surrounding the tip of the conductor post 4 is formed on the Si substrate 1 on which the conductor post 4 is formed, and the resist mask film 5
By wet etching using an isotropic etching means such as a fluoronitric acid solution through the openings 51 of 2, a width of 5i (h) is formed around the insulating film 3, which is interposed between the conductive post 4 and the substrate 1. Concave portion 5 of approximately 2 μm and depth of 1 μm
form 3.

FIG. 4 (bl) After removing the resist mask film 52, a coated insulating film 54 such as PMSS is buried in the recess 53 on the substrate surface by a spin code method or the like.

Refer to FIG. 4(C). Next, a SiO2 interlayer insulating film 2 is formed on the substrate surface by CVO method.
6 and then the S
A contact window 55 is formed in the interlayer insulating film 26, and then a poly-Si circuit wiring 27 is formed in the contact window 55 portion to contact the conductor post 4 by a normal wiring forming method.

According to the above method, the coated insulating film 54 is embedded in a wide area around the tip of the conductor post 4, so even if the contact window 55 is slightly displaced, the circuit wiring 27 will not be short-circuited to the substrate l. .

In addition, when forming the contact window by etching, the StO□ insulating film 3 along the conductive post 4 is removed by over-etching.
A recess is formed in the coated insulating film 54 containing
Since the conductive post 4 and the circuit wiring 27 are coated so as to wrap around the conductive post 4, the quality of contact between the conductive post 4 and the circuit wiring 27 is improved.

Note that the above wiring connection method is similarly applied to the back side of the board.

Next, we will discuss an example of application of the present invention to an insulating film breakdown type FROM, which writes information by electrically breaking down an insulating film.
The explanation will be given with reference to the plan view (al) and side sectional view (bl) shown in the figure.

In the figure, 11 is a power supply wiring on the back side of the substrate, 12 is a wiring connecting the front and back sides (conductor post), 13 is a connection part with the source/drain region 14b of a MOS I-transistor, and 14a
, 14b is a source/drain region, 15 is a word line,
115 is the word line of the adjacent cell, 16 is the program element,
17 is a bit line.

When programming this PROM cell, the word line 15 of the cell to be occupied is driven, and the bit line 17 of the cell to be occupied is driven.
to a high potential for programming. This destroys program element 16 and causes conduction between bit line 17 and source/drain region 14a. Program element 1
6 is formed of a thin insulating film of about 100 layers or poly-Si. (In the case of poly-Si, the phenomenon in which impurities from the surroundings diffuse into poly-Si due to the heat generated by the current flowing through the progelater and its conductivity changes is utilized.) In this case, the pulse current required for programming is The instantaneous value changes depending on the resistance of the power supply wiring.

Although not shown, in a conventional structure in which a device is formed on one side of a substrate, the power supply wiring is composed of a diffusion layer formed integrally with the source/drain region 14b. Therefore, the wiring resistance is large and the instantaneous current value cannot be obtained large.
Since a problem arises in that writing is not easy, countermeasures such as reinforcing the power supply wiring with a metal wiring layer are required at the time of design. At this time, since the bit lines are also formed of metal wiring, it is impossible for both to satisfy the optimal layout conditions at the same time, and it is inevitable that unnecessary power supply wiring will be run within the cell array, resulting in a reduction in the degree of integration. There was a problem in that it caused a decline.

If the present invention is applied, as shown in FIG.
Since power can be supplied from the back side of the board 1 through the through holes (conductor posts) 12 formed in the board, the power supply wiring 11 is optimized independently of the wiring on the front side such as the bit line 17 on the back side of the board, and is made of a wide range of low-resistance metal materials. Therefore, it can be formed with low resistance.

Therefore, the degree of integration of the ROM array can be improved, and since writing can be performed easily and reliably, its reliability is improved.

Next, we will discuss the application example of the present invention to a mask ROM in the sixth section.
Description will be given with reference to the circuit diagram (al) shown in the figure, a schematic side sectional view (b) in the case of information "1", and a schematic side sectional view (C) in the case of information "0".

In the figure, - is a word line, BL is a bit line, Vcc is a power supply line, Ml, M2 are memory transistors, 1 is a substrate, 3
is an insulating film, 4 is a wiring (conductor post) connecting the front and back sides,
Reference numerals 14a and 14b indicate source/drain regions of memory transistors, and reference numeral 18 indicates a layer-opened 8M film on the back surface of the substrate.

As shown in the figure, in the mask ROM to which the present invention is applied, the power supply Vcc of memory transistors M1, M2, etc.
A conductor post 4 insulated from the substrate 1 by an insulating film 3 is led out from the bottom of the source/drain 14a on the side not connected to the substrate 1 to the back surface of the substrate 1, and an interlayer insulating film 18 is formed covering the back surface of the substrate l. The bit line B is provided on the interlayer insulating film 18 on the back surface of the substrate 1. Information is then written into the interlayer insulating film 18 depending on whether the contact window to the conductor post 4 is present or absent.In this example, the contact window "present" corresponds to "1", and "absent" corresponds to "O". corresponds to

In this way, the mask ROM can be easily formed at the final stage of the process, that is, just before the three-dimensional 1c elements are stacked, so that when the mask ROM information is changed, the shipping of the three-dimensional IC with the mask ROM becomes easier. The number will be significantly shortened.

〔Effect of the invention〕

As described above, according to the present invention, a three-dimensional IC is a double-sided IC in which semiconductor circuits are formed on both sides of a semiconductor substrate and interconnected through current-carrying posts formed through the semiconductor substrate. Since each unit of the structure is formed by a multilayer stack of three-dimensional IC elements, the integration density is improved.

In addition, since all the semiconductor elements that make up the semiconductor circuits in each layer are formed directly on both sides of the semiconductor single crystal substrate, their characteristics are stable.At the same time, because of the stacked structure mentioned above, good products can be selected separately for each semiconductor circuit in each layer. Since it becomes possible to perform multi-layer stacking, manufacturing yields can be greatly improved.

Furthermore, due to the above-mentioned stacked structure, the wiring on the bottom surface of the board can be changed for each unit three-dimensional IC element in just one step during the stacking (lamination) process, making it extremely easy to change the wiring when changing ROM information, etc. This greatly reduces the number of steps needed to manufacture a three-dimensional RC including ROM.

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view showing the principle of a three-dimensional IC according to the present invention, FIG. 2 is a schematic side sectional view showing an embodiment of the structure of the present invention, and FIGS. FIG. 4 is a process cross-sectional view showing an embodiment of the manufacturing method of the invention; FIG. 4 is a process cross-sectional view showing a method for forming contacts between conductor posts and circuit wiring; FIG. 5 is a schematic diagram showing the structure of the FROM according to the present invention. A plan view (a), a schematic side sectional view (b), and FIG. 6 are a circuit diagram of a mask ROM according to the present invention (al, a schematic side sectional view fb in the case of information "1") and a schematic side sectional view fb in the case of information "0". Schematic side sectional view of (
It is C1. In the figure, ■ is a semiconductor substrate, 2a and 2b are semiconductor circuits, 3 is an insulating film, 4 is a conductor post, 5 is a covering insulating film, 6.7 is a connection terminal, A is a unit three-dimensional 1c element, and B is a unit Figure 3 shows a multilayer stack of three-dimensional IC elements.

Claims (1)

[Claims] 1. Semiconductor circuits (2a) (2) on both sides of the semiconductor substrate (1)
b) is formed, and the semiconductor circuit (2a) (2b) passes through the semiconductor substrate (1), and the conductor post (4) is insulated from the semiconductor substrate.
and the surface of at least one of the covering insulating films (5) covering the semiconductor circuits (2a) (2b), the semiconductor circuits (2a) (2b) below the covering insulating film (5). A three-dimensional semiconductor integrated circuit device comprising a unit three-dimensional semiconductor integrated circuit element (A) having connection terminals (6) and (7) led out from ). 2. The three-dimensional semiconductor integrated circuit device according to claim 1, wherein the semiconductor circuit on the front surface of the semiconductor substrate is a ROM circuit, and the semiconductor circuit on the back surface is a part of the ROM wiring. 3. The three-dimensional semiconductor integrated circuit device according to claim 1, wherein the upper layer of the covering insulating film covering the semiconductor circuit is made of thermosetting silicone resin. 4. The connection between the conductive post tip and the semiconductor circuit or circuit wiring is made on a coated insulating film embedded around the conductive post tip. The three-dimensional semiconductor integrated circuit device according to item 1. 5. Forming a non-through hole in the surface of the semiconductor substrate, forming an insulating film on the inner surface of the non-through hole, and filling the non-through hole with a conductor to make the semiconductor substrate conductive insulated from the semiconductor substrate. forming a first semiconductor circuit electrically connected to the upper end of the conductive post on the surface of the semiconductor substrate; and forming a first covering insulating film on the semiconductor substrate. forming and leading out connection terminals from the first semiconductor circuit on the surface of the first covering insulating film; and after pasting a support substrate on the semiconductor substrate, polishing the back surface of the semiconductor substrate. a step of exposing the lower end of the conductor post; a step of forming a second semiconductor circuit electrically connected to the lower end of the conductor post on the back surface of the semiconductor substrate; and a step of forming a second semiconductor circuit on the back surface of the semiconductor substrate. A method for manufacturing a three-dimensional semiconductor integrated circuit device, comprising the steps of forming a second covering insulating film on a surface of the second covering insulating film, and leading out connection terminals from a second semiconductor circuit on the surface of the second covering insulating film. . 6. Claim 5, wherein the first and second covering insulating films are comprised of a vapor grown insulating film and a thermosetting silicone resin film coated on the vapor grown insulating film. A method of manufacturing the three-dimensional semiconductor integrated circuit device described above. 7. When connecting the tip of the conductor post and the semiconductor circuit, a recess is formed around the conductor post on the surface of the semiconductor substrate, a coated insulating film is embedded in the recess, and the conductive film is filled with the coated insulating film. Claim 4, further comprising the step of forming a concave portion for protruding the tip of the conductive post, and forming a wiring material layer for a semiconductor circuit on the protruding portion of the conductive post and the coated insulating film. A method of manufacturing the three-dimensional semiconductor integrated circuit device described above.