JP2005268662A - Method of manufacturing three-dimensional device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a three-dimensional device, which has few manufacturing processes and can complicatedly arrange a thin film semiconductor device. <P>SOLUTION: The method of manufacturing the three-dimensional device comprises steps of: forming an isolation layer 102 on a substrate 101; forming an interlayer 103; forming an identical conduction type thin film semiconductor device all over the substrate 101; forming an interlayer 202 on a substrate 201; forming an identical conduction type thin film semiconductor device all over the substrate 201; laminating these two device layers; and peeling the substrate 101 by projecting XeCl excimer laser light from the substrate 101 side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a three-dimensional device.

  In recent years, with the aim of realizing higher integration and higher density of semiconductor devices and solving problems related to wiring such as signal delay and increased power consumption, three-dimensional integration of a plurality of devices three-dimensionally Device development is underway.

  Conventionally, when manufacturing a three-dimensional device such as a three-dimensional IC, first, a first layer including a field effect transistor (FET) or the like is formed on a Si substrate through a number of processes. Next, a similar second layer is formed on the first layer. Thereafter, the third and subsequent layers are formed in the same manner.

  However, in the conventional method for manufacturing a three-dimensional device, the layers are formed so as to be sequentially stacked on the same substrate. Therefore, the formation of the upper layer must not adversely affect the lower layer, and various restrictions ( For example, the upper limit of the temperature at which the lower layer does not change.

  Also, when different layers are stacked, it is very difficult to form each layer with suitable device parameters (for example, manufacturing conditions such as gate line width, gate insulating film thickness, design rule, temperature, etc.).

  Further, in the conventional method for manufacturing a three-dimensional device, each layer is formed on the substrate constituting the device, so that the substrate used has both compatibility as a substrate of the device and compatibility as a substrate when forming each layer. Only certain substrates could be used.

  Furthermore, since each layer is formed in order on the substrate constituting the device, there is a problem that the manufacturing time becomes very long.

  In order to solve the above problems, a technique for laminating thin film device layers as disclosed in JP-A-5-41478 and JP-A-2001-250913 has been studied. In these techniques, a semiconductor element is formed on a single crystal silicon substrate, the back surface of the substrate is polished, the substrate is thinned, and the thin film devices are three-dimensionally stacked.

  However, JP-A-5-41478 and JP-A-2001-250913 also have problems. In these techniques, the back surface of the substrate is polished to reduce the thickness of the substrate. Single crystal silicon substrates require enormous energy for manufacturing and are expensive. Therefore, the above substrate back surface polishing step is very wasteful in terms of energy and cost.

  The above problem has been solved by the manufacturing method disclosed in JP-A-11-251517. In this technique, a thin film device layer is formed on a substrate via a separation layer, the separation layer is irradiated with light to peel off the separation layer, and the thin film device layer is transferred to another substrate. Since an inexpensive glass substrate can be used, it is advantageous in terms of energy and cost. Further, a substrate polishing step is not necessary.

JP-A-5-41478 JP 2001-250913 A JP-A-11-251517

  The three-dimensional device manufactured by such a conventional manufacturing method has a problem that there are many manufacturing processes. In the manufacturing method of a three-dimensional device, the manufacturing method of each thin film device layer is as usual. Therefore, when the thin film device layer includes a CMOS (Complementary Metal Oxide Semiconductor) circuit composed of a thin film semiconductor device, the thin film device layer includes an N-type thin film semiconductor device using electrons as carriers and a P using holes as carriers. There is a need to form a type of thin film semiconductor device. In the case where an impurity is implanted into a region where an N-type thin film semiconductor device is to be formed, it is necessary to form a mask in the region where a P-type thin film semiconductor device is to be formed by photolithography so that the impurity is not implanted. In contrast, when impurities are implanted into a region where a P-type thin film semiconductor device is to be formed, a mask is formed in the region where an N-type thin film semiconductor device is to be formed by photolithography so that the impurities are not implanted. It is necessary to. As described above, when the CMOS circuit is to be two-dimensionally configured, there are problems that the number of photolithography processes increases, and the manufacturing cost increases and the time required for the manufacturing increases.

  Further, in the three-dimensional device manufactured by the conventional manufacturing method, there is a problem that it is difficult to arrange a thin film semiconductor device in a complicated manner. When N-type and P-type thin film semiconductor devices are two-dimensionally arranged, a P-type (N-type) thin film semiconductor device is formed in which an impurity to be implanted into a region where an N-type (P-type) thin film semiconductor device is to be formed. The N-type and P-type thin film semiconductor devices need to be formed at a certain distance so as not to be injected into the region. When the N-type and P-type thin film semiconductor devices are formed at a certain distance as described above, it is difficult to realize a complicated arrangement in which the N-type and P-type thin film semiconductor devices are intricately arranged. If such an arrangement is to be realized, there is a problem that the circuit area becomes very large, and the circuit cannot be configured in a desired region.

  The invention disclosed in this specification provides means for solving the above-described problems. Specifically, an object of the present invention is to provide a method for manufacturing a three-dimensional device, which has a small number of manufacturing steps and can arrange thin film semiconductor devices in a complicated manner.

  In order to solve the above problems, a method for manufacturing a three-dimensional device according to the present invention is a method for manufacturing a three-dimensional device in which a plurality of thin film device layers arranged in a predetermined region in the two-dimensional direction are stacked in the thickness direction. In addition, at least one of the thin film device layers includes a plurality of thin film semiconductor devices, and carriers that contribute to the conduction of the thin film semiconductor device are the same in the thin film device layer, and among the thin film device layers, And a transfer step of laminating by peeling and transferring at least one of the above from another substrate.

  According to the above three-dimensional device manufacturing method, the conductivity types of the thin film semiconductor devices in one thin film device layer are all the same. That is, thin film semiconductor devices of different conductivity types are not adjacent two-dimensionally. Therefore, there is no restriction on the distance between adjacent thin film semiconductor devices due to the conductivity type of the thin film semiconductor device, so that the thin film semiconductor devices can be arranged close to each other. In addition, since a thin film semiconductor device having a single conductivity type may be formed in a certain thin film device layer, the manufacturing process can be reduced.

  The three-dimensional device manufacturing method of the present invention is characterized in that, in the method of manufacturing a thin film semiconductor device existing in the thin film device layer, the same impurity is implanted into the entire semiconductor layer of the thin film semiconductor device.

  According to the method for manufacturing a three-dimensional device, the manufacturing process can be reduced. When a circuit is formed using a thin film semiconductor device, a CMOS circuit is often used. In order to construct a CMOS circuit, N-type and P-type thin film semiconductor devices must be two-dimensionally arranged in the same thin film device layer. When an impurity is implanted into a region where a thin film semiconductor device having one conductivity type is formed, a mask is formed in the region where a thin film semiconductor device having the other conductivity type is formed by a photolithographic method so that the impurity is not implanted. It is necessary to do so. As described above, when the CMOS circuit is to be two-dimensionally configured, there are problems that the number of photolithography processes increases, and the manufacturing cost increases and the time required for the manufacturing increases. However, in the manufacturing method of the present invention, the CMOS circuit is not two-dimensionally configured, and the same impurity is entirely injected into the semiconductor layer of the thin film semiconductor device existing in one thin film device layer. There are fewer lithography processes and fewer manufacturing processes.

  In addition, the three-dimensional device manufacturing method of the present invention is characterized in that carriers contributing to conduction of thin film semiconductor devices existing in the thin film device layers adjacent to each other are different. Further, the three-dimensional device manufacturing method of the present invention is characterized in that a thin film semiconductor device existing in adjacent thin film device layers forms a CMOS circuit.

  According to the above three-dimensional device manufacturing method, a CMOS circuit can be three-dimensionally formed by thin film semiconductor devices existing in adjacent thin film device layers. When a two-dimensional CMOS circuit is formed in a thin film device layer, the N-type region and the P-type region must be formed at a certain distance, so that the N-type region and the P-type region seem to be complicated. It was difficult to realize a simple configuration. In addition, the number of photolithography processes in the impurity implantation process is also a problem. According to the present invention, since a CMOS circuit can be formed three-dimensionally, there is no restriction on the two-dimensional distance between the N-type region and the P-type region, and a CMOS circuit having a complicated configuration can be formed. It can be done. Further, since it is only necessary to form a thin film semiconductor device of the same conductivity type two-dimensionally, the number of photolithography processes accompanying the impurity implantation process is small, and the number of manufacturing processes is reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

The present invention is characterized by including a transfer step of laminating by peeling and transferring at least one of each thin film device layer from another substrate. This transfer step is carried out by using a “thin film structure transfer method” described in detail in [0032] to [0120] of [Embodiment of the invention] of JP-A-11-251517. The transfer process will be briefly described below with reference to the cross-sectional views shown in FIGS. First, a separation layer 2 is formed on a substrate 1 as shown in FIG. Specific examples of the substrate 1 include a quartz substrate and a glass substrate. A specific example of the separation layer 2 is an amorphous silicon film. An intermediate layer 3 is formed on the separation layer 2 using a silicon oxide film such as SiO ₂ . A transferred layer 4 such as a device layer is formed on the intermediate layer 3. As shown in FIG. 2, the transfer layer 4 is bonded to a transfer body 6 such as a separate substrate through the adhesive layer 5. When light 7 such as excimer laser light is irradiated from the back side of the substrate 1, separation and / or interface separation occurs in the separation layer 2, and the bonding force decreases or disappears, so that the substrate 1 and the transfer body 6 are separated from each other. Then, the transferred layer 4 is detached from the substrate 1 and transferred to the transfer body 6 as shown in FIG.

  4 to 10 are cross-sectional process diagrams illustrating a method of manufacturing a three-dimensional device according to the first embodiment of the present invention. Hereinafter, the manufacturing method of the three-dimensional device according to the first embodiment of the present invention will be described with reference to this drawing.

As shown in FIG. 4, the separation layer 102 is formed on the substrate 101, and the intermediate layer 103 is formed on the separation layer 102 using a silicon oxide film such as SiO ₂ . A thin film semiconductor device is formed on the intermediate layer 103. First, a polycrystalline silicon film 104 as a semiconductor film is formed on the intermediate layer 103. The polycrystalline silicon film 104 may be formed directly by a chemical vapor deposition (CVD) method or the like, but after the amorphous silicon film is formed by the CVD method, the amorphous silicon film is crystallized. This is preferable because the crystallinity of the silicon film is excellent. The crystallization method is a solid phase growth method in which heat treatment is performed for several hours in an inert atmosphere of about 500 ° C. to 700 ° C., or a laser that melts and solidifies an amorphous silicon film by irradiating intense light such as an excimer laser. An annealing method is mentioned. The solid phase growth method has little variation in crystal grain size, and large crystal grains may be obtained depending on the formation conditions of the amorphous silicon film, but there are many defects in the crystal grains. On the other hand, the laser annealing method melts the silicon film once, so that there are very few defects in the crystal grains and a high-quality polycrystalline silicon film can be obtained. After the polycrystalline silicon film 104 is formed, the polycrystalline silicon film 104 is processed into a desired shape by using a photolithography method. After that, a silicon oxide film 105 such as SiO ₂ is formed as a gate insulating film, a polycrystalline silicon film in which a metal or an impurity is implanted is formed on the gate insulating film 105, and is formed into a desired shape by photolithography. The gate electrode 106 is formed by processing. Thereafter, impurities 107 are implanted into the polycrystalline silicon film 104 to form source / drain regions 104a of the thin film semiconductor device. Examples of impurities to be implanted include phosphorus (P) when forming an N-type thin film semiconductor device, and boron (B) when forming a P-type thin film semiconductor device. Any impurities can be used. Conventionally, in order to form a CMOS circuit two-dimensionally, it has been necessary to form N-type and P-type thin film semiconductor devices on the same device layer, so that a mask for distinguishing N-type and P-type impurities is used. In the present invention, since the thin film semiconductor device of the same conductivity type is formed on the entire surface of the device layer in the present invention, a mask for distinguishing between N-type and P-type impurities is unnecessary, and the process is simplified. be able to.

  As shown in FIG. 5, a silicon oxide film 108 as an interlayer insulating film is formed. Then, you may planarize the surface as needed. Examples of the flattening method include mechanical polishing and spin coating of a liquid material. Contact holes are opened in the interlayer insulating film 108 to form connection electrodes 109 connected to the source / drain regions of the thin film semiconductor device. The connection electrode is formed of a conductive material such as a polycrystalline silicon film into which metal or impurities are implanted. It may be formed of a single substance or a plurality of substances. If it is made of a single material, the number of steps is reduced. Moreover, if it forms with a several substance, the connection electrode as needed can be formed. For example, if the material filling the contact hole and the material on the interlayer insulating film are changed and a low melting point metal is used on the interlayer insulating film, the connection electrodes can be easily joined. Here, the connection electrode 109 is electrically connected to the source / drain region of the thin film semiconductor device.

Next, in the same manner as in FIGS. 4 and 5, a thin film semiconductor device is formed on another substrate. As shown in FIG. 6, an intermediate layer 202 is formed on a substrate 201 using a silicon oxide film such as SiO ₂ . A thin film semiconductor device is formed on the intermediate layer 202. A polycrystalline silicon film 203 as a semiconductor film is formed on the intermediate layer 202. After the polycrystalline silicon film 203 is formed, the polycrystalline silicon film 203 is processed into a desired shape by using a photolithography method. After that, a silicon oxide film 204 such as SiO ₂ is formed as a gate insulating film, a polycrystalline silicon film in which a metal or an impurity is implanted is formed on the gate insulating film 204, and is formed into a desired shape by photolithography. The gate electrode 205 is formed by processing. Thereafter, impurities 206 are implanted into the polycrystalline silicon film 203 to form source / drain regions 203a of the thin film semiconductor device. Impurity 206 is different from impurity 107 shown in FIG. 4, and the conductivity type of source / drain region 203a is different from the conductivity type of source / drain region 104a shown in FIG. That is, when the impurity 107 is phosphorus, the impurity 206 is boron, and when the impurity 107 is boron, the impurity 206 is phosphorus.

  As shown in FIG. 7, a silicon oxide film 207 as an interlayer insulating film is formed. Then, you may planarize the surface as needed. Contact holes are opened in the interlayer insulating film 207 to form connection electrodes 208 connected to the source / drain regions of the thin film semiconductor device. Here, the connection electrode 208 is electrically connected to the source / drain region of the thin film semiconductor device.

  As shown in FIG. 8, the connection electrode 109 and the connection electrode 208 are joined to electrically connect the thin film semiconductor devices, and the device layers are mechanically joined by the adhesive 11. This bonding process may be any method as long as the device layers can be bonded electrically and mechanically. For example, the electrical connection includes a method in which the connection electrodes are solid-phase bonded, or the connection electrodes are bonded to each other via a low melting point metal such as solder. There is also a method of performing electrical and mechanical bonding through an anisotropic conductive film. Since any bonding method may be used, the adhesive 11 is not always necessary.

  The substrate 101 is peeled off using a thin film structure transfer method. Specifically, in FIG. 8, for example, XeCl excimer laser light (wavelength 308 nm) is irradiated from the substrate 101 side. Then, the light is absorbed by the separation layer 102, and in-layer separation and / or interface separation occurs in the separation layer 102, so that the bonding force is reduced or disappears. Can do. When a part of the separation layer 102 remains on the surface of the intermediate layer 103, the residue of the separation layer 102 is removed by an etching method or the like. Thus, as shown in FIG. 9, the thin film semiconductor device formed on the substrate 101 is transferred to the substrate 201. FIG. 9 shows a three-dimensional device in which thin film semiconductor devices are three-dimensionally stacked. In this three-dimensional device, the carriers contributing to the conduction of the thin film semiconductor device existing in the same layer are the same and exhibit the same conductivity type. Therefore, there is no restriction on the distance between the thin film semiconductor devices due to the conductivity type of the thin film semiconductor device, and a complicated circuit configuration can be realized. Further, in this three-dimensional device, carriers contributing to conduction are different in adjacent device layers. Therefore, the CMOS circuit can be configured three-dimensionally.

  In order to stack three or more device layers, the above steps are repeated. Specifically, as shown in FIG. 10, contact holes are opened in the intermediate layer 103 to form connection electrodes 110. Then, a device layer may be stacked on the connection electrode 110 in the same manner as in the step of FIG.

  In this manner, a desired number of device layers can be stacked to create a three-dimensional device.

  As described above, according to the first embodiment, it is possible to manufacture a three-dimensional device in which the manufacturing process is small and the thin film semiconductor device can be arranged in a complicated manner.

  11 to 13 are cross-sectional process diagrams illustrating a method of manufacturing a three-dimensional device according to the second embodiment of the present invention. Hereinafter, a method of manufacturing a three-dimensional device according to the second embodiment of the present invention will be described with reference to this drawing.

  The second embodiment of the present invention is the same as the first embodiment except that the connection electrodes are different.

Similar to FIGS. 4 and 5, a thin film semiconductor device is formed on a substrate. As shown in FIG. 11, a separation layer 302 is formed on a substrate 301, and an intermediate layer 303 is formed on the separation layer 302 using a silicon oxide film such as SiO ₂ . A thin film semiconductor device is formed on the intermediate layer 303. First, a polycrystalline silicon film 304 as a semiconductor film is formed on the intermediate layer 303, and the polycrystalline silicon film 304 is processed into a desired shape by using a photolithography method. After that, a silicon oxide film 305 such as SiO ₂ is formed as a gate insulating film, a polycrystalline silicon film in which a metal or an impurity is implanted is formed on the gate insulating film 305, and is formed into a desired shape by photolithography. The gate electrode 306 is formed by processing. Thereafter, impurities are implanted into the polycrystalline silicon film 304 to form source / drain regions 304a of the thin film semiconductor device. Next, a silicon oxide film 308 is formed as an interlayer insulating film. Then, you may planarize the surface as needed. Contact holes are opened in the interlayer insulating film 308 to form connection electrodes 309 connected to the source / drain regions of the thin film semiconductor device. In the first embodiment, the connection electrode is electrically connected to the source / drain region of the thin film semiconductor device, but here the connection electrode 309 is electrically connected to the gate electrode and the source / drain region of the thin film semiconductor device.

Next, in the same manner as in FIGS. 4 and 5, a thin film semiconductor device is formed on another substrate. As shown in FIG. 12, an intermediate layer 402 is formed on a substrate 401 using a silicon oxide film such as SiO ₂ . A thin film semiconductor device is formed on the intermediate layer 402. A polycrystalline silicon film 403 as a semiconductor film is formed on the intermediate layer 402. After the polycrystalline silicon film 403 is formed, the polycrystalline silicon film 403 is processed into a desired shape by using a photolithography method. Thereafter, a silicon oxide film 404 such as SiO ₂ is formed as a gate insulating film, and a polycrystalline silicon film in which a metal or an impurity is implanted is formed on the gate insulating film 404, and is formed into a desired shape by photolithography. The gate electrode 405 is formed by processing. Thereafter, impurities are implanted into the polycrystalline silicon film 403 to form source / drain regions 403a of the thin film semiconductor device. The impurity to be implanted is different from the impurity implanted into the source / drain region 304a in FIG. 11, and the conductivity type of the source / drain region 403a is different from the conductivity type of the source / drain region 304a shown in FIG. A silicon oxide film 407 is formed as an interlayer insulating film. Then, you may planarize the surface as needed. Contact holes are opened in the interlayer insulating film 407 to form connection electrodes 408 connected to the source / drain regions of the thin film semiconductor device. In the first embodiment, the connection electrode is electrically connected to the source / drain region of the thin film semiconductor device, but here the connection electrode 408 is electrically connected to the gate electrode of the thin film semiconductor device.

  As shown in FIG. 13, the connection electrode 309 and the connection electrode 408 are joined to electrically connect the thin film semiconductor devices to each other, and the device layers are mechanically joined by the adhesive 21. This bonding process may be any method as long as the device layers can be bonded electrically and mechanically.

  Then, as in Example 1, the substrate 301 is peeled off using a thin film structure transfer method. Thus, the thin film semiconductor device formed over the substrate 301 is transferred to the substrate 401.

  As described above, according to the second embodiment, the gate electrodes of the thin film semiconductor device can be electrically connected, and the gate electrode and the source / drain regions can be electrically connected. In the first embodiment, the source / drain regions of the thin film semiconductor device are electrically connected to each other. However, according to the present invention, the electrical connection between the thin film device layers is freely performed as in the second embodiment. be able to. In the embodiment, two connection electrodes are connected, but it is naturally possible to connect a plurality of connection electrodes.

  As described above, according to the three-dimensional device manufacturing method of the present invention, it is possible to manufacture a three-dimensional device in which a thin film semiconductor device can be arranged in a complicated manner with fewer manufacturing steps. Therefore, according to the present invention, it is possible to manufacture a three-dimensional device with low manufacturing cost, and it is possible to manufacture a three-dimensional device that realizes high integration and high density of semiconductor devices.

It is sectional drawing which shows typically the process of the Example of the transfer method of the thin film structure in this invention. It is sectional drawing which shows typically the process of the Example of the transfer method of the thin film structure in this invention. It is sectional drawing which shows typically the process of the Example of the transfer method of the thin film structure in this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 1 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 2 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 2 of the manufacturing method of the three-dimensional device of this invention. It is sectional drawing which shows typically the process of Example 2 of the manufacturing method of the three-dimensional device of this invention.

Explanation of symbols

1, 101, 201, 301, 401 ... Substrate 2, 102, 302 ... Separation layer 3, 103, 202, 303, 402 ... Intermediate layer 4 ... Transfer layer 5 ... Adhesive layer 6 ... transfer body 7 ... light 11, 21 ... adhesives 104, 203, 304, 403 ... semiconductor films 104a, 203a, 304a, 403a ... source / drain regions 105, 204, 305 404, gate insulating films 106, 205, 306, 405 ... gate electrodes 107, 206 ... impurities 108, 207, 308, 407 ... interlayer insulating films 109, 110, 208, 309, 408,. ..Connection electrodes

Claims (4)

In the method of manufacturing a three-dimensional device in which a plurality of thin film device layers arranged in a predetermined region in the two-dimensional direction are stacked in the thickness direction, a thin film semiconductor device is provided in at least one of the thin film device layers. A plurality of carriers that contribute to conduction of the thin film semiconductor device are the same in the thin film device layer, and transfer is performed by peeling and transferring at least one of the thin film device layers from another substrate. The manufacturing method of the three-dimensional device characterized by including a process. 2. The method of manufacturing a three-dimensional device according to claim 1, wherein in the method of manufacturing a thin film semiconductor device existing in the thin film device layer, the same impurity is implanted into the entire semiconductor layer of the thin film semiconductor device. 3. The method of manufacturing a three-dimensional device according to claim 1, wherein carriers contributing to conduction of thin film semiconductor devices existing in the thin film device layers adjacent to each other are different from each other. 4. The method for manufacturing a three-dimensional device according to claim 3, wherein the thin film semiconductor devices existing in the thin film device layers adjacent to each other form a complementary metal oxide semiconductor (CMOS) circuit.

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