JP2013089752A - Stacked semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked semiconductor device capable of reducing parasitic capacitance of a gate without increasing a connection electrode pitch and achieving both faster circuit speed and density growth of interlayer connection, and a manufacturing method thereof.SOLUTION: A stacked semiconductor device comprises: a first semiconductor element 70 including a first gate 60 and a first impurity diffusion region 31 and a second impurity diffusion region 33 formed on a lower layer than the first gate; and a second semiconductor element 75 including a second gate 65 joined facing the first gate and a third impurity diffusion regions 36 and a fourth impurity diffusion region 38 formed on a higher layer than the second gate.

Description

  The present invention relates to a stacked semiconductor device and a manufacturing method thereof, and more particularly to a stacked semiconductor device having a first semiconductor element and a second semiconductor element and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, there has been known a stacked semiconductor device in which a circuit substrate including a transistor is thinned and stacked for high integration of a semiconductor integrated circuit (for example, see Patent Documents 1 and 2).

  FIG. 1 is a diagram showing a conventional method for manufacturing a stacked semiconductor device described in Patent Document 1. In FIG. FIG. 1A is a view showing a laminated substrate forming process in which a MOS transistor is formed on an SOI (Silicon On Insulator) substrate in a conventional method of manufacturing a laminated semiconductor device. In the laminated substrate forming step, an insulating film 450 is formed on an SOI substrate 445 composed of a support substrate 415, a buried oxide film 425 and an active layer 435, and an n-channel MOS having a gate 465 and impurity diffusion regions 436 to 438. A transistor 475 is formed. In addition, the wiring 485 is also formed at the same time in the multilayer substrate formation step, so that the multilayer substrate 495 is formed. Note that the surface of the multilayer substrate 495 is planarized.

  FIG. 1B is a view showing a supporting substrate removing step of a conventional method for manufacturing a stacked semiconductor device. In the support substrate removal step, the support substrate 415 is removed from the multilayer substrate 495 by polishing, and the surface of the multilayer substrate 495 is attached to the temporary substrate 515.

  FIG. 1C is a view showing a back surface wiring forming step of a conventional method for manufacturing a stacked semiconductor device. In the back surface wiring formation step, part of the buried oxide film 425 is removed, and the back surface wiring 530 is formed on the back surface of the multilayer substrate 495.

  FIG. 1D is a diagram showing a substrate bonding step in a conventional method for manufacturing a stacked semiconductor device. In the substrate bonding step, the stacked substrate after the back surface wiring 530 shown in FIG. 1C is bonded and stacked on the base substrate 490 on which the separately manufactured MOS transistor 470 is formed. Then, the temporary substrate 515 on the surface is removed, and the stacked semiconductor device is completed.

  At this time, although not described in Patent Document 1, in order to stabilize the operation of the MOS transistor 475, the back surface of the MOS transistors 470 and 475 (opposite to the gates 460 and 465 across the buried oxide films 420 and 425). The side surface) is preferably grounded. In the example of FIG. 1, the support substrate 410 can be grounded with respect to the base substrate 490 as shown in FIG.

Japanese Patent Publication No. 5-39345 JP 2002-334968 A

  However, in the stacked semiconductor device manufactured by the manufacturing method of the stacked semiconductor device described in Patent Document 1 described above, the upper layer MOS transistor 470 has no ground electrode on the back surface, and therefore the circuit operation is unstable. There was a problem that it might become.

  FIG. 2 is a diagram showing a configuration for stabilizing the circuit operation of the stacked semiconductor device described in Patent Document 1. In FIG. As shown in FIG. 2, in order to stabilize the circuit operation of the stacked semiconductor device shown in FIG. 1D, it is conceivable to form a ground electrode 540 on the back surface of the upper substrate.

  However, in the configuration shown in FIG. 2, since the gate 460 of the MOS transistor 470 on the base substrate 490 and the ground electrode 540 are close to each other, the parasitic capacitance 550 of the gate 460 increases. The increase in the parasitic capacitance 550 has a problem that it hinders the speeding up of the circuit operation, which is widely known.

  On the other hand, a three-dimensional semiconductor chip is known in which thin-film LSI chips are three-dimensionally bonded and integrated (see, for example, Patent Document 2). Such a three-dimensional semiconductor chip has a configuration in which a groove communicating with the outside of the three-dimensional semiconductor chip is formed in a substrate of the LSI chip, and a heat radiation material is embedded in the groove. According to such a three-dimensional semiconductor chip, since there is a space between the stacked substrates, the distance between the gate of the base substrate and the upper substrate is increased, and the parasitic capacitance of the gate is decreased. Therefore, stacking is possible without sacrificing high-speed circuit operation.

  However, in the configuration described in Patent Document 2, since the substrates are connected by bumps, it is difficult to reduce the connection pitch. Compared to the configurations shown in FIGS. 1 and 2, the density of interlayer connection is increased. Then there is a problem that it is disadvantageous. In summary, in the configuration of the conventional semiconductor device described in Patent Documents 1 and 2, there is a problem that it is difficult to achieve both high-speed circuit and high density of interlayer connection.

  Accordingly, the present invention provides a stacked semiconductor device that can reduce the parasitic capacitance of the gate without increasing the pitch of the connection electrodes, and can achieve both high speed of the circuit and high density of the interlayer connection, and a manufacturing method thereof. The purpose is to provide.

In order to achieve the above object, a stacked semiconductor device according to one embodiment of the present invention includes a first gate and first and second impurity diffusion regions formed in a lower layer than the first gate. A first semiconductor element;
A second semiconductor element having a second gate joined opposite to the first gate, and third and fourth impurity diffusion regions formed in a layer above the second gate; It is characterized by having.

A semiconductor device according to another aspect of the present invention includes a first gate having a first metal wiring formed on a surface thereof, and first and second impurity diffusion regions formed in a lower layer than the first gate. A first semiconductor element comprising:
A second metal wiring is formed on the surface, the second metal wiring is joined to face the first metal wiring, and a second gate is formed above the second gate. And a second semiconductor element having third and fourth impurity diffusion regions.

The first semiconductor element is formed on a first substrate,
The second semiconductor element is formed on a second substrate;
A first insulating film is provided on the opposite surface of the first substrate to the first gate,
A second insulating film is provided on the opposite surface of the second substrate to the second gate,
A support substrate having a ground potential is provided on the surface of the first insulating film,
It is preferable that an electrode connected to the first semiconductor element and the second semiconductor element is provided on a surface of the second insulating film.

  The first and second semiconductor elements may be MOS transistors.

The first semiconductor element is a P-channel MOS transistor,
The second semiconductor element is an N-channel MOS transistor;
A CMOS in which the drains of the N-channel MOS transistor and the P-channel MOS transistor are connected to each other may be used.

A method for manufacturing a stacked semiconductor device according to another aspect of the present invention includes a step of forming a first semiconductor element so that a first gate is disposed in the vicinity of a surface of a first substrate;
Forming a second semiconductor element such that the second gate is disposed near the surface of the second substrate;
Planarizing the surfaces of the first and second substrates;
Disposing the first substrate and the second substrate so that the first gate and the second gate face each other, and bonding the first substrate and the second substrate by direct bonding It is characterized by having.

The step of forming the first semiconductor element includes a step of forming a first metal wiring on the first gate,
Forming the second semiconductor element includes forming a second metal wiring on the second gate;
In the step of bonding the first substrate and the second substrate, the first metal wiring and the second metal wiring may be bonded.

Further, in the step of planarizing the surfaces of the first and second substrates, the first and second gates are in a state of being flatly exposed on the surfaces of the first and second substrates,
In the step of bonding the first substrate and the second substrate, the first gate and the second gate may be bonded.

  According to the present invention, the circuit operation can be speeded up and the density of interlayer connection can be increased.

FIG. 10 is a diagram showing a conventional method for manufacturing a stacked semiconductor device described in Patent Document 1. FIG. 1A is a view showing a laminated substrate forming process in which a MOS transistor is formed on an SOI substrate in a conventional method for manufacturing a laminated semiconductor device. FIG. 1B is a view showing a supporting substrate removing step of a conventional method for manufacturing a stacked semiconductor device. FIG. 1C is a view showing a back surface wiring forming step of a conventional method for manufacturing a stacked semiconductor device. 10 is a diagram showing a configuration for stabilizing the circuit operation of a stacked semiconductor device described in Patent Document 1. FIG. It is sectional drawing which showed an example of the laminated semiconductor device which concerns on Example 1 of this invention. 1 is a circuit diagram of a semiconductor device according to Example 1. FIG. FIG. 4A is a circuit diagram illustrating only electrical connection of the semiconductor device according to the first embodiment. FIG. 4B is a circuit diagram reflecting the physical layout of the semiconductor device according to the first embodiment. 6 is a diagram illustrating an example of a first semiconductor element formation step of the method for manufacturing a semiconductor device according to the first embodiment. FIG. It is a plane block diagram of the base substrate after the planarization process. 6 is a diagram showing an example of a second semiconductor element formation step of the method for manufacturing a semiconductor device according to Example 1. FIG. It is the plane block diagram which showed the laminated substrate after the planarization process. 6 is a diagram illustrating an example of a bonding process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing an example of an electrode contact hole forming step in the method for manufacturing a semiconductor device according to Example 1. FIG. 6 is a diagram showing an example of an electrode forming process of the method for manufacturing a semiconductor device according to Example 1. FIG. It is the plane block diagram which showed the semiconductor device after an electrode formation process. 6 is a diagram showing an example of an input / output electrode formation step of the method for manufacturing a semiconductor device according to Example 1. FIG. It is a plane block diagram of the completed semiconductor device after an input / output electrode formation process. It is the figure which showed the cross-sectional structure of the semiconductor device after completion shown to FIG. 5J. FIG. 5K (a) is a diagram showing the configuration of the AA ′ cross section of FIG. 5J. FIG. 5K (b) is a diagram showing the configuration of the BB ′ cross section of FIG. 5J. FIG. 5K (c) is a diagram showing the configuration of the CC ′ cross section of FIG. 5J. It is the figure which showed an example of the semiconductor device which concerns on Example 2 of this invention. 6 is a diagram showing an example of a first semiconductor element formation step of a method for manufacturing a semiconductor device according to Example 2. FIG. 6 is a diagram showing an example of a second semiconductor element formation step of the method for manufacturing a semiconductor device according to Example 2. FIG. 6 is a diagram illustrating an example of a bonding process of a method for manufacturing a semiconductor device according to Example 2. FIG. 6 is a diagram illustrating an example of a wiring forming process of a method for manufacturing a semiconductor device according to Example 2. FIG. 7D is a cross-sectional view of the semiconductor device according to Example 2 after completion shown in FIG. 7D, taken along a plane perpendicular to FIG. It is the figure which showed an example of the semiconductor device which concerns on Example 3 of this invention. FIG. 8A is a transparent plan view of the semiconductor device according to the third embodiment. FIG. 8B is a configuration diagram in the CC ′ cross section of FIG. Moreover, FIG.8 (c) is a block diagram in the AA 'cross section of Fig.8 (a). FIG. 8D is a configuration diagram in the BB ′ cross section of FIG. It is the figure which showed the cross-sectional structure of the conventional power device which concerns on a comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 3 is a cross-sectional view showing an example of a stacked semiconductor device according to the first embodiment of the invention. In FIG. 3, the stacked semiconductor device according to the first embodiment includes a base substrate 90, a stacked substrate 95, an electrode 100, an interlayer insulating film 110, an input electrode 120, and an output electrode 121. The base substrate 90 and the multilayer substrate 95 have a configuration in which the multilayer substrate 95 is laminated and bonded onto the base substrate 90 after being manufactured independently of each other. A P-channel MOS transistor 70 is formed on the base substrate 90, and an N-channel MOS transistor 75 is formed on the laminated substrate 95. By laminating the laminated substrate 95 on the base substrate 90, the P-channel MOS transistor 70 and the N-channel MOS transistor 75 are configured to be connected in a complementary manner. Further, the electrode 100, the interlayer insulating film 110, the input electrode 120, and the output electrode 121 provided on the laminated substrate 95 are connected to both in order to perform the circuit operation of both the P-channel MOS transistor 70 and the N-channel MOS transistor 75. This is a common area.

  The base substrate 90 includes a support substrate 10, a buried oxide film layer 20, an active layer 30, and an insulating film 50. The support substrate 10, the buried oxide film layer 20, and the active layer 30 constitute an SOI substrate 40. In the active layer 30, a source region 31, a channel region 32, a drain region 33, and an insulating isolation region 34 are formed side by side in the horizontal direction. An insulating film 50 is formed on the active layer 30, and a gate 60 is formed in the insulating film 50. Further, a metal wiring 80 is formed on the surface of the gate 60, and a metal wiring 81 is formed on the drain 33. A contact hole 131 is formed on the source 31. The gate 60 is formed near the surface of the base substrate 90.

  A P channel MOS transistor 70 is formed by the gate 60, the source region 31, the channel region 32, and the drain region 33 formed on the base substrate 90. The source region 31 and the drain region 33 are formed as P-type impurity diffusion regions, and the channel region 32 is formed as an N-type impurity diffusion region. When a negative voltage is applied to the gate 60, a transistor operation is performed in which the N-type channel region 32 is inverted to P-type and the source region 31 and the drain region 33 are brought into conduction.

  The support substrate 10 is connected to the ground and set to the ground potential, so that the circuit operation of the stacked semiconductor device is stabilized. The support substrate 10 can be composed of various conductive substrates. For example, the support substrate 10 may be composed of a silicon substrate with increased impurity concentration and increased conductivity.

The buried oxide film layer 20 can be composed of various insulating films other than the oxide film, but is preferably composed of SiO ₂ .

The active layer 30 is composed of an active layer of silicon. The regions constituting the source region 31, the channel region 32 and the drain region 33 are doped with impurities to form a P-type impurity diffusion region or an N-type impurity diffusion region. The insulating isolation region 34 may be formed by, for example, forming a trench in the active layer 30 and then embedding an insulating film such as SiO ₂ by a CVD (Chemical Vapor Deposition) method.

  Since the laminated body of the support substrate 10, the buried oxide film layer 20, and the active layer 30 is commercially available as an SOI substrate 40, the laminated body is directly formed on the active layer 30 without performing the step of forming the laminated body. Impurity diffusion regions 31 to 33 can be formed.

The insulating film 50 may be composed of various insulating films, but may be composed of, for example, SiO ₂ . The insulating film 50 may be formed by the above-described CVD method, for example.

  The gate 60 is formed near the surface of the base substrate 90. In the stacked semiconductor device according to the present embodiment, the gate 60 of the base substrate 90 and the gate 65 of the stacked substrate 95 are arranged to face each other and are electrically connected via a metal wiring 80 and a metal wiring 85 described later. Therefore, in order to easily connect the gates 60 and 65 with low resistance, the gate 60 is disposed in the vicinity of the surface of the base substrate. In the stacked semiconductor device according to the present embodiment, the metal wiring 80 is disposed on the surface of the base substrate 90 and the gate 60 is disposed directly below the metal wire 80, so that the gate 60 is exposed on the surface of the base substrate 90. It is not, but is located near the surface just below the surface.

  The gate 60 can be made of various conductive materials, but may be made of polysilicon, for example. The gate 60 made of polysilicon may be formed by depositing polysilicon by CVD, for example.

  The metal wirings 80 and 81 are wirings for electrically connecting the constituent elements of the base substrate 90 and the constituent elements of the multilayer substrate 95, and a conductive film made of metal may be used. The metal wirings 80 and 81 are formed so as to be exposed on the surface of the base substrate 90 in order to make electrical connection with the laminated substrate 95. The metal wirings 80 and 81 may be made of a metal material appropriate for the application, such as copper, aluminum, silver, gold, or tungsten. The metal wirings 80 and 81 may be formed by plating, for example.

  The metal wiring 80 is a wiring for electrically connecting the gate 60 of the base substrate 90 and the gate 65 of the multilayer substrate 95 as described above, and is formed on the surface of the gate 60. The metal wiring 81 is a wiring for making an electrical connection between the drain region 33 of the base substrate 90 and a drain region 38 of a laminated substrate 95 described later. Therefore, the metal wiring 81 is formed on the drain region 33 of the base substrate 90 and extends upward so as to be exposed on the surface of the base substrate 90.

  Next, the laminated substrate 95 will be described. The laminated substrate 95 has a configuration that is approximately symmetrical with the underlying substrate 90. The laminated substrate 95 has a buried oxide film layer 25, an active layer 35, an insulating film 55, a gate 65, and metal wirings 85 and 86. These have a configuration in which the upper and lower arrangement relations with each layer of the base substrate 90 are reversed, with the buried oxide film layer 25 being the uppermost layer, the active layer 35 being below it, and the insulating film 55 being below it. Have. The active layer 35 has a source region 36, a channel region 37, a drain region 38, and an insulating isolation region 39. A gate 65 is disposed in the insulating film 55 in the vicinity of the lower surface of the multilayer substrate 95. A metal wiring 85 is formed on the lower surface of the gate 65, and a metal wiring 86 is formed on the lower surface of the drain region 38.

  The buried oxide film layer 25 and the active layer 35 may be configured as a part of the SOI substrate, similarly to the base substrate 90. In the multilayer substrate 95, the active layer 35 of the SOI substrate is disposed on the lower side, and the support substrate of the SOI substrate is removed.

In the active layer 35, a source region 36 and a drain region 38 which are N-type impurity diffusion regions and a channel region 37 which is a P-type impurity diffusion region are formed by impurity implantation. Also, an insulating isolation region 39 is formed by embedding the insulating film after forming the trench. The insulating isolation region 39 may be formed by an CVD method using an insulating film such as SiO ₂ .

  The gate 65 is disposed in the vicinity of the lower surface of the multilayer substrate 95 and is disposed so as to face the gate 60 of the base substrate 90. Note that the gate 65 may be made of polysilicon, for example, similarly to the gate 60.

  The gate 65, the source region 36, the channel region 37, and the drain region 38 constitute an N-channel MOS transistor 75.

  The metal wiring 85 is formed on the lower surface of the gate 65 and is exposed on the lower surface of the multilayer substrate 95. Then, at the boundary surface between the laminated substrate 95 and the base substrate 90, the metal wiring 80 of the base substrate 90 is contacted and bonded. As a result, the gate 60 of the base substrate 90 and the gate 65 of the multilayer substrate 95 are electrically connected, and the gates 60 and 65 are connected in parallel.

  The metal wiring 86 is formed on the lower surface of the drain region 38 and is exposed on the lower surface of the multilayer substrate 95. Then, at the boundary surface between the laminated substrate 95 and the base substrate 90, the drain regions 33 and 38 are electrically connected to each other by being brought into contact with and bonded to the metal wiring 81 of the base substrate 90.

  The base substrate 90 and the laminated substrate 95 are preferably joined by direct joining. In the direct bonding, the surface to be a bonding surface of the base substrate 90 and the multilayer substrate 95 is flattened to a level where only unevenness of several nanometers exists, and the base substrate 90 and the multilayer substrate 95 are bonded to each other at a level of 100 to 200 ° C. This is done by heating at a relatively low temperature. Accordingly, the base substrate 90 and the laminated substrate 95 can be physically and electrically bonded without using a bonding material such as a solder bump, and the density of interlayer connection can be increased.

  In FIG. 3, the electrode 100 is configured as an electrode for supplying a ground potential, and is electrically connected to the source region 35 of the N-channel MOS transistor 75 through the contact hole 130. Although not shown in FIG. 3, an electrode for supplying the power supply potential VDD is formed on the buried oxide film layer 25 on the back side of the electrode 100 in the same manner as the electrode 100. It is electrically connected to the source region 31 of the P-channel MOS transistor 70 through the hole 131. In addition, the electrode 100 may be comprised from metal materials, such as copper, aluminum, silver, gold | metal | money, tungsten, similarly to the metal wiring 80, 81, 85, 85. The electrode 100 may also be formed by plating.

Interlayer insulating film 110, than the electrode 100 is an insulating film provided to form electrodes on the upper layer, for example, it may be constituted by SiO _2. Further, the interlayer insulating film 110 may be formed by, for example, a CVD method.

  The input electrode 120 is an electrode connected to the gates 60 and 65. In FIG. 3, the input electrode 120 is formed on the interlayer insulating film 110 and is electrically connected to the gates 60 and 65 through the contact hole 132. Similarly to the electrode 100, the input electrode 120 may also be formed by plating using a metal material for wiring.

  The output electrode 121 is an electrode connected to the drain regions 33 and 38. Similarly to the input electrode 120, the output electrode 121 is also formed on the interlayer insulating film 110. As shown in FIG. 3, the output electrode 121 is electrically connected to the drain regions 33 and 38 through the contact hole 133 and the metal wirings 81 and 86.

  As described above, the contact holes 130 to 133 are wiring holes for electrically connecting the upper layer electrodes 100, 120, and 121 to the lower layer MOS transistors 70 and 75. A hole is formed through each insulating film 25, 50, 55, 110 to be connected to the MOS transistors 70, 75 and filled with a metal material to be electrically connected to each electrode 100, 120, 121.

  Thus, in the semiconductor device according to the first embodiment, the P-channel MOS transistor 70 formed on the base substrate 90 and the N-channel MOS transistor 75 formed on the stacked substrate 95 are vertically symmetric at the stack boundary surface. It has a configuration that is directly joined by arrangement. For this reason, a bonding material such as a solder bump becomes unnecessary, and the lamination density can be increased. In addition, since the gates 60 and 65 are opposed to each other and the electrical connection is made directly only through the metal wirings 80 and 85, the metal wirings can be routed long to electrically connect the gates 60 and 65 to each other. It becomes unnecessary. Therefore, the wiring resistance can be reduced and the circuit operation of the MOS transistors 70 and 75 can be speeded up.

  Note that the support substrate 10 of the base substrate 90 is connected to the ground so as to have a ground potential. Thereby, the operation of the MOS transistor 70 can be stabilized. In addition, the electrode 100 is connected to the ground and has a ground potential. Thereby, the operation of the MOS transistor 75 can be stabilized. In addition, since there is no ground potential substrate on the lower surface of the multilayer substrate 95, the parasitic capacitance between the gate 60 and the multilayer substrate 95 and between the gate 65 and the base substrate 90 can be reduced. The circuit operation of the transistors 70 and 75 can be speeded up.

  FIG. 4 is a circuit diagram of the semiconductor device according to the first embodiment. FIG. 4A is a circuit diagram illustrating only the electrical connection of the semiconductor device according to the first embodiment, and FIG. 4B illustrates the physical arrangement of the semiconductor device according to the first embodiment. FIG.

  As shown in FIG. 4A, the semiconductor device according to the first embodiment is configured as a CMOS (Complementary Metal Oxide Semiconductor) inverter. In FIG. 4A, the same reference numerals corresponding to those in FIG. That is, the P-channel MOS transistor 70 and the N-channel MOS transistor 75 are connected to the input electrode 120 with the gates 60 and 65 in common, and connected to the output electrode 121 with the drains 33 and 38 in common. As described above, in the semiconductor device according to the first embodiment, a CMOS that performs high-speed circuit operation can be realized with high-density interlayer connection.

  FIG. 4B is a diagram of a CMOS inverter in which a P-channel MOS transistor 70 is arranged on the lower side and an N-channel MOS transistor 75 is arranged on the upper side in accordance with the arrangement shown in FIG. The support substrate 10 is grounded to stabilize the CMOS circuit operation, and is not electrically connected to the CMOS. Therefore, the circuit diagram of the semiconductor device according to the first embodiment is as shown in FIG.

  3 and 4B, an example in which the P-channel MOS transistor 70 is formed on the base substrate 90 and the N-channel MOS transistor 75 is formed on the laminated substrate 95 has been described. However, the vertical relationship is reversed. Alternatively, the N-channel MOS transistor 75 may be formed on the base substrate 90 and the P-channel MOS transistor 70 may be formed on the laminated substrate 95. The vertical relationship can be easily changed by simply changing the configuration of the electrodes 100, 120, 121 and the contact holes 130-131.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 5A to 5K. 5A to 5K, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 5A is a diagram illustrating an example of the first semiconductor element formation step of the method for manufacturing the semiconductor device according to the first embodiment. In the first semiconductor element formation step, a P-channel MOS transistor 70 is formed on the base substrate 90 as the first semiconductor element.

  Specifically, first, an SOI substrate 40 including a support substrate 10, a buried oxide film layer 20, and an active layer 30 is prepared. A P-type impurity diffusion region serving as a source region 31 and a channel are formed in the active layer 30 of the SOI substrate 40. An N-type impurity diffusion region that becomes the region 32 and a P-type impurity diffusion region that becomes the drain region 33 are formed in this order from the left. These impurity diffusion regions may be formed by doping each region 30 to 33 with a predetermined impurity and heating to perform diffusion. Note that the support substrate 10 is configured such that an SOI substrate 40 having a high impurity concentration and high conductivity is prepared, or an impurity is implanted to increase the conductivity of the support substrate 10. Further, an isolation region 34 is formed for lateral element isolation.

  Next, a gate oxide film is formed on the active layer 30, polysilicon is then deposited by CVD or the like, and necessary heating, surface polishing, etching, etc. are performed to form the gate 60. Subsequently, an insulating film 50 is formed by a CVD method or the like. In this figure, a region sandwiched between the gate 60 and the channel region 32 is a gate oxide film (the gate oxide film and the insulating film are indicated by 50 without being distinguished). The gate 60 is formed so as to be disposed near the surface of the base substrate 90.

  Next, a hole is formed on the drain region 33 and the gate 60 by etching, and a conductive film is formed by plating to form a conductive film including the metal wirings 80 and 81. Since the P-channel MOS transistor 70 is formed at this stage, the process up to this point may be considered as the first semiconductor element formation process. In addition, the first semiconductor element formation step can also be called a base substrate formation step because it can be regarded as a step of forming the semiconductor substrate on the SOI substrate 40 to form the entire base substrate 90.

  Finally, a surplus portion of the formed conductive film is polished and removed, and the insulating film 50 of the base substrate 90 is exposed, and a planarization process for forming the metal wirings 80 and 81 is performed. Polishing is performed by, for example, a CMP (Chemical Mechanical Polishing) method. At that time, the surface of the base substrate 90 is flattened by mirror polishing, and the surface is flattened to a level where only unevenness of several nm exists so that atomic level bonding by direct bonding is possible.

  FIG. 5B is a plan configuration diagram of the base substrate 90 after the planarization step. As shown in FIG. 5B, a source region 31 and a drain region 33 are formed on both sides of the gate 60, and a P-channel MOS transistor 70 is formed. The gate width of the gate 60 is indicated by WP. A metal wiring 80 is formed on the gate 60, and a metal wiring 81 is formed on the drain region 33.

  As described above, the P-channel MOS transistor 70 is formed on the base substrate 90 as described with reference to FIGS. 5A and 5B.

  FIG. 5C is a diagram illustrating an example of the second semiconductor element formation step of the method for manufacturing the semiconductor device according to the first embodiment. In the second semiconductor element formation step, an N-channel MOS transistor 75 is formed as a second semiconductor element on the laminated substrate 95.

  The second semiconductor element formation step is substantially the same as the first element semiconductor formation step, and an SOI substrate 45 including a support substrate 15, a buried oxide film layer 25, and an active layer 35 is prepared. A source region 36 made of an impurity diffusion region, a channel region 37 made of a P-type impurity diffusion region, a drain region 38 made of an N-type impurity diffusion region, and an insulating isolation region 39 made of an insulating film are formed. Up to this point, the first region except that the conductivity types of the source region 36, the channel region 37, and the drain region 38 are reversed, the source region 3 is disposed on the right side, and the drain region 38 is disposed on the left side. This is the same as the semiconductor element forming step. However, since the source region 36 and the drain region 38 are N-type impurity diffusion regions having the same concentration as the diffusion region, there is no substantial distinction as the impurity diffusion region. This also applies to the source region 31 and the drain region 33 of the base substrate 90.

  The formation of the next gate 65, the formation of the oxide film 55, and the formation of the metal wirings 85 and 86 are basically the same as those in the first semiconductor element formation step. However, in the laminated substrate 95, the gate 65 comes to the lower side. Therefore, the metal wiring 86 is formed on the drain region 38 formed on the left side so as to come into contact with the metal wiring 81 when being inverted upside down. .

  Note that since the N-channel MOS transistor 75 serving as the second semiconductor element is once formed at the stage where the conductive films to be the metal wirings 85 and 86 are formed, the process up to this stage is the second semiconductor element forming process or stacking. The point that may be referred to as a substrate forming step is the same as in the first semiconductor element forming step and the base substrate forming step.

  FIG. 5D is a plan configuration diagram showing the laminated substrate after the planarization step. In FIG. 5D, a source region 36 and a drain region 38 are formed on both sides of the gate 65, and a MOS transistor 75 is formed. A metal wiring 85 is formed on the gate 65, and a metal wiring 86 is formed on the drain region 38. Although the gate width of the gate 65 is indicated by WN, it is shorter than the gate width WP shown in FIG. 5B. As shown in FIGS. 5B and 5D, the gate width WN of the N-channel MOS transistor 70 is generally shorter than the gate width WP of the P-channel MOS transistor 75. Therefore, the P-channel MOS transistor having a large gate width WP. The arrangement of 70 on the base substrate 90 has the advantage that wiring formation is facilitated. Therefore, in the semiconductor device and the manufacturing method thereof according to the present embodiment, an example in which the P-channel MOS transistor 70 is formed on the base substrate 90 is described.

  FIG. 5E is a diagram illustrating an example of a bonding process in the method for manufacturing a semiconductor device according to the first embodiment. In the bonding step, the multilayer substrate 95 is stacked on the base substrate 90, and the base substrate 90 and the multilayer substrate 95 are bonded. The bonding between the base substrate 90 and the laminated substrate 95 is preferably performed by direct bonding. This eliminates the need for bonding materials such as solder bumps, and can increase the density of interlayer connections.

  As described above, in the direct bonding, the surface of the base substrate 90 and the surface of the laminated substrate 95 are flattened to a level at which only unevenness of a few nm level exists, and the flattened surfaces are bonded together. And it joins by an atomic level by heating at the comparatively low temperature of 100-200 degreeC.

  The planarization of the surface of the base substrate 90 and the laminated substrate 95 is preferably performed immediately before bonding the two, so that the first semiconductor element formation step and the second semiconductor element formation step are performed in parallel. The planarization may be performed almost simultaneously, or once the conductive film is formed for both the base substrate 90 and the laminated substrate 95, and the planarization process for both is performed immediately before bonding, and the bonding process. May be executed.

  Further, after the joining process is completed, a support substrate removing process is performed in which the support substrate 15 of the laminated substrate 95 is removed. Thereby, the buried oxide film layer 25 is exposed on the surface.

  FIG. 5F is a diagram illustrating an example of the electrode contact hole forming step in the method for manufacturing the semiconductor device according to the first embodiment. In the electrode contact hole forming step, a contact hole 130 that is conductive to the source region 36 of the multilayer substrate 95 is formed in the buried oxide film layer 25, and a contact hole 131 that is conductive to the source region 31 of the base substrate 90 is embedded in the buried oxide film layer. 25, the insulating film 55 and the insulating film 50.

  FIG. 5G is a diagram illustrating an example of an electrode forming process of the method for manufacturing the semiconductor device according to the first embodiment. In the electrode formation step, the electrode 100 is formed on the buried oxide film layer 25 and the contact holes 130 and 131 are filled with a conductive film. The formation of the electrode 100 and the filling of the contact holes 130 and 131 may be performed by forming a conductive film by plating and planarizing the conductive film by a CMP method.

  FIG. 5H is a plan configuration diagram transparently showing the semiconductor device after the electrode forming step. As shown in FIG. 5H, an electrode 100 connected to the ground is formed on the front side, and an electrode 101 connected to the power supply VDD is formed on the back side. As shown in the circuit diagram of FIG. 4, the ground is connected to the source region 36 of the N-channel MOS transistor 75 through the contact hole 130, and the source region 31 of the P-channel MOS transistor 70 is connected through the contact hole 131. It can be seen that the power supply VDD is connected.

FIG. 5I is a diagram illustrating an example of the input / output electrode formation step of the method for manufacturing the semiconductor device according to the first embodiment. In the input / output formation step, the interlayer insulating film 110 is formed on the electrode 100, the contact holes 132 and 133 are formed, and then the input electrode 120 and the output electrode 121 are formed. As the interlayer insulating film 110, for example, an insulating film such as SiO ₂ may be formed by a CVD method or the like. Thereafter, contact holes 132 and 133 are formed through the interlayer insulating film 110, the buried oxide film layer 25 and the insulating film 55. Then, by forming a conductive film on the interlayer insulating film 110 by plating and filling the contact holes 132 and 133 and then planarizing the conductive film by CMP, the input electrode 120 and the output electrode 121 can be formed. . Note that the semiconductor device according to Example 1 is completed upon completion of the input / output electrode formation step.

  FIG. 5J is a plan configuration diagram of the completed semiconductor device after the input / output electrode formation step. As shown in FIG. 5J, it can be seen that the input electrode 120 is connected to the gate 60 through the contact hole 132, and the output electrode 121 is connected to the drain 33 through the contact hole 133.

  FIG. 5K is a diagram showing a cross-sectional configuration of the completed semiconductor device shown in FIG. 5J. 5K (a) is a diagram showing the configuration of the AA ′ cross section of FIG. 5J, and FIG. 5K (b) is a diagram showing the configuration of the BB ′ cross section of FIG. 5J. (C) is the figure which showed the structure of CC 'cross section of FIG. 5J. 5J (a), (b), and (c), the right side corresponds to the back side of FIG. 5J and the left side corresponds to the near side of FIG. 5J.

  In FIG. 5K (a), the wiring of the electrodes 100 and 101 is shown. As shown in FIG. 5K (a), the wiring on the ground GND side is connected to the source region 36 of the N-channel MOS transistor 70, and the wiring on the power supply VDD side is connected to the source region 31 of the P-channel MOS transistor 75. 4 is consistent with the circuit diagram shown in FIG. In addition, the dashed-dotted line in FIG. 5K (a) has shown the location where a cross section switches.

  In FIG. 5K (b), the wiring of the input electrode 120 is shown. As shown in FIG. 5K (b), the input wiring 120 is connected to a portion extending to the back side of the metal wiring 80 through the contact hole 120. It can be seen that a voltage is applied from the metal wirings 80 and 85 to the gates 60 and 65. Further, the gate 60 surrounds the channel region 32 and the gate 65 surrounds the channel region 37, which matches the configuration of the MOS transistors 70 and 75.

  In FIG. 5K (c), the wiring of the output electrode 121 is shown. As shown in FIG. 5K (c), the output wiring 121 is connected to the back side portion of the metal wiring 81 and connected to the drain region 38 via the drain region 33 and the metal wiring 86, as shown in FIG. Consistent with the circuit diagram.

  As described above, according to the method of manufacturing a semiconductor device according to the first embodiment, the semiconductor device in which the high density of the stacked connection and the high speed of the circuit operation are realized only by using the general semiconductor process and the direct bonding. Can be manufactured.

  In the semiconductor device and the manufacturing method thereof according to the first embodiment, the example in which the semiconductor device is configured using the SOI substrates 40 and 45 has been described. However, the semiconductor device can also be configured using a bulk substrate. . In this case, an insulating film and a semiconductor layer may be formed on the back surface of the base substrate 90 in place of the buried oxide film layer 20 and the support substrate 10, and the other configurations are the same as those shown in the first embodiment. And a manufacturing method.

  FIG. 6 is a diagram showing an example of a semiconductor device according to the second embodiment of the present invention. In the semiconductor device according to the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  6, the semiconductor device according to the second embodiment includes a base substrate 91, a laminated substrate 96, an electrode 100, an interlayer insulating film 110, an input electrode 120, and an output electrode 121. The laminated substrate 96 is laminated on the base substrate 91, and the wiring used for both the base substrate 91 and the laminated substrate 96 is formed on the top of the laminated substrate 96 in the same manner as the semiconductor device according to the first embodiment.

  The base substrate 91 includes the support substrate 10, the buried oxide film layer 20, the active layer 30, the insulating film 50, the gate 60, and the metal wiring 81, and the base substrate 90 of the semiconductor device according to the first embodiment. However, it is different from the base substrate 90 of the semiconductor device according to the first embodiment in that the metal wiring 80 on the gate 60 is not provided.

  Similarly, the multilayer substrate 96 is also common to the multilayer substrate 95 of the semiconductor device according to the first embodiment in that it includes the buried oxide film layer 25, the active layer 35, the insulating film 55, the gate 65, and the metal wiring 86. However, it differs from the laminated substrate 95 of the semiconductor device according to the first embodiment in that the metal wiring 85 on the lower surface of the gate 65 is not provided.

  Since the metal wirings 80 and 85 on the surfaces of the gates 60 and 65 do not exist, the base substrate 91 and the multilayer substrate are in a state in which the gate 60 of the base substrate 91 and the gate 65 of the multilayer substrate 96 are in direct contact with each other. 96 is joined. As described above, the gates 60 and 65 may be directly joined to each other without using the metal wirings 80 and 85. Since there is no wiring between the gates 60 and 65, the electrical resistance of the wiring is eliminated, and the circuit operation can be speeded up.

  Also in the semiconductor device according to the second embodiment, it is preferable that the base substrate 91 and the multilayer substrate 96 are joined by direct joining. In this case, the surface of the base substrate 91 is planarized so that the gate 60 of the base substrate 91 is exposed on the surface, and the surface of the multilayer substrate 96 is planarized so that the gate 65 of the multilayer substrate 96 is exposed on the surface. As in the semiconductor device according to the first embodiment, the degree of planarization is planarized to a level where only unevenness of several nanometers or less exists on the surface. Then, bonding at the atomic level is performed by bonding the base substrate 91 and the laminated substrate 96 so that the gates 60 and 65 of both are opposed to each other and heating at a relatively low temperature of about 100 to 200 ° C. The base substrate 91 and the laminated substrate 96 are bonded. This is also the same as in the first embodiment.

  Further, the metal wirings 81 and 86 are the same as in the first embodiment except that the metal wirings 81 and 86 are thinned by the absence of the metal wirings 80 and 85. Since the contact holes 131, 132, and 133 are the same as those in the first embodiment except that the depth is shallower by the metal wirings 80 and 85, the description thereof is omitted.

  Next, a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. 7A to 7E. 7A to 7E, the same components as those in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 7A is a diagram illustrating an example of the first semiconductor element formation step of the method for manufacturing the semiconductor device according to the second embodiment. In the first semiconductor element formation step, a P-channel MOS transistor 70 is formed on an SOI substrate 40 in which a support substrate 10, a buried oxide film layer 20, and an active layer 30 are sequentially stacked from below. The P-channel MOS transistor 70 includes a source region 31 made of a P-type impurity diffusion layer formed in the active layer 30, a channel region 32 made of an N-type impurity diffusion layer, and a drain region 33 made of a P-type impurity diffusion layer. And the point comprised from the gate 60 formed above via the insulating film 50 is the same as that of the semiconductor device which concerns on Example 1, and its manufacturing method. The gate 60 is disposed on the surface of the base substrate 91. Further, the first semiconductor element formation step may be called a base substrate formation step.

  In the planarization step of planarizing the surface of the base substrate 91, the base substrate 91 is polished so that the gate 60 is exposed on the surface of the base substrate 91.

  FIG. 7B is a diagram illustrating an example of the second semiconductor element formation step of the method for manufacturing the semiconductor device according to the second embodiment. Also in the second semiconductor element formation step, the N-channel MOS transistor 75 is formed on the SOI substrate 45 in which the support substrate 15, the buried oxide film layer 25, and the active layer 35 are sequentially stacked from below. The N-channel MOS transistor 75 includes a source region 36 formed of an N-type impurity diffusion layer formed in the active layer 35, a channel region 37 formed of a P-type impurity diffusion layer, and a drain region 38 formed of an N-type impurity diffusion layer. And a gate 65 formed above with the insulating film 55 interposed therebetween. The metal wiring 86 is formed on the drain region 86 so as to face the metal wiring 81 of the base substrate 91 when the laminated substrate 95 is turned upside down. The gate 65 is formed on the surface of the multilayer substrate 96. Note that the second semiconductor element formation step may be referred to as a laminated substrate formation step.

  In the flattening step of flattening the surface of the multilayer substrate 96, the gate 65 is exposed on the surface and polished so that only a few nm unevenness exists on the surface.

  FIG. 7C is a diagram illustrating an example of a bonding process in the method for manufacturing a semiconductor device according to the second embodiment. In the bonding step, the multilayer substrate 96 is stacked on the base substrate 91, and the base substrate 91 and the multilayer substrate 96 are bonded by a direct bonding method heated at 100 to 200 ° C. At that time, the alignment of the base substrate 91 and the laminated substrate 95 is performed so that the gates 60 and 65 and the metal wirings 81 and 86 face each other. A semiconductor element portion configured as a CMOS inverter is completed by the bonding process.

  Further, after the bonding process is completed, a support substrate removal process is performed in which the support substrate 15 of the multilayer substrate 96 is removed. By the supporting substrate removing step, the buried oxide film layer 25 is exposed on the surface.

  FIG. 7D is a diagram illustrating an example of a wiring formation process of the method for manufacturing a semiconductor device according to the second embodiment. In the wiring formation step, wiring connected to the P channel MOS transistor 70 and the N channel MOS transistor 75 is formed. Specifically, electrode 100 is connected to source region 36 of N channel MOS transistor 75 through contact hole 130, and electrode 101 (not shown) is connected to source region 31 of P channel MOS transistor 70 through contact hole 131. Similarly, the input electrode 120 is connected to the gates 60 and 65 through the contact hole 132, and the output electrode 121 is connected to the drain regions 33 and 38 through the contact hole 133 and the metal wirings 81 and 86. By performing this wiring formation process, the semiconductor device according to Example 2 is completed.

  FIG. 7E is a cross-sectional view of the semiconductor device according to the second embodiment after completion shown in FIG. 7D, taken along a plane perpendicular to FIG. In FIG. 7E, the input electrode 120 is directly connected to the back side portion of the gate 60 through the contact hole 132. The gate 65 is joined to the gate 60, and an input voltage is applied to the gates 60 and 65 at the same time.

  As described above, the metal wirings 80 and 85 may not be provided between the gates 60 and 65, and the gates 60 and 65 may be directly joined to each other, and the input electrode 120 may be connected to one or both of the gates 60 and 65. According to the semiconductor device and the manufacturing method thereof according to the second embodiment, since there is no connection wiring between the gates 60 and 65, the electrical resistance due to the connection wiring is eliminated, the electrical resistance of the entire element is reduced, and the circuit operation is speeded up. can do.

  In the second embodiment, the P-channel MOS transistor 70 may be formed on the laminated substrate 96, the P-channel MOS transistor 75 may be formed on the base substrate 91, and the vertical relationship of the semiconductor elements may be reversed. Similar to the semiconductor device according to the first embodiment, the semiconductor device may be configured using a bulk substrate instead of the SOI substrates 40 and 45.

  FIG. 8 is a diagram showing an example of a semiconductor device according to Example 3 of the present invention. FIG. 8A is a transparent plan view of the semiconductor device according to the third embodiment, and FIG. 8B is a configuration diagram in the CC ′ section of FIG. 8A. 8C is a configuration diagram in the section AA ′ in FIG. 8A, and FIG. 8D is a configuration diagram in the section BB ′ in FIG. 8A.

  8A, the semiconductor device according to Example 3 includes a buried oxide film layer 225, an electrode 301, an input electrode 302, an output electrode 303, contact holes 330 to 332, a gate 265, and a source region. 236, a low concentration drain region 238a, a high concentration drain region 238b, an insulating isolation region 239, and an electrode 300.

  8B, the semiconductor device according to Example 3 includes a support substrate 210, a buried oxide film layer 220, an active layer 230, an insulating film 250, a gate 260, metal wirings 280 and 281, and the like. And a buried oxide film layer 225, an active layer 235, an insulating film 255, a gate 265, metal wirings 282 and 283, and an electrode 300.

  Here, the active layer 230 includes a source region 231 composed of a high-concentration N-type impurity diffusion region, a channel region 232 composed of a P-type impurity diffusion region, a low-concentration drain region 233a composed of a low-concentration N-type impurity diffusion region, It has a high-concentration drain region 233b made of a high-concentration N-type impurity diffusion region and an insulating isolation region 234 made of an insulating film. Similarly, the active layer 235 includes a source region 236 composed of a high-concentration N-type impurity diffusion region, a channel region 237 composed of a P-type impurity diffusion region, and a low-concentration drain region 238a composed of a low-concentration N-type impurity diffusion region. , A high-concentration drain region 238b made of a high-concentration N-type impurity diffusion region, and an insulating isolation region 239 made of an insulating film.

  The gate 260, the source region 231, the channel region 232, the low-concentration drain region 233a, and the high-concentration drain region 233b of the base substrate 290 form an N-channel MOS transistor 270, and the gate 265, source region 236, The channel region 237, the low concentration drain region 238a, and the high concentration drain region 238b constitute an N channel MOS transistor 275.

  In the semiconductor device according to the third embodiment, the first N-channel MOS transistor 270 is formed on the base substrate 290, and the second N-channel MOS transistor 275 is also formed on the multilayer substrate 295. The semiconductor device according to the third embodiment is configured not as a CMOS but as a power device in which N-channel MOS transistors 270 and 275 are connected in parallel. As described above, the semiconductor element formed on the base substrate 290 and the semiconductor element formed on the stacked substrate 295 may be formed of semiconductor elements having the same conductivity type. In the three-phase inverter, the N-channel MOS transistors 270 and 275 are often connected in parallel. In such a case, the semiconductor device according to the third embodiment can be suitably used.

  In the semiconductor device according to the third embodiment, the drain region is composed of two types of N-type impurity diffusion regions, the low concentration drain regions 233a and 238a and the high concentration drain regions 233b and 238b. 238a is provided to improve the breakdown voltage, and has a configuration suitable for a power device.

  Further, in the semiconductor device according to the third embodiment, similarly to the semiconductor device according to the second embodiment, no metal wiring is provided between the gates 260 and 265, and the gates 260 and 265 are directly joined to each other. However, as in the first embodiment, a metal wiring may be provided between the gates 260 and 265.

  FIG. 9 is a diagram showing a cross-sectional configuration of a conventional power device according to a comparative example. In FIG. 9, a first N-channel MOS transistor 670 and a second N-channel MOS transistor 675 are formed side by side on an SOI substrate 640 composed of a support substrate 610, a buried oxide film layer 620, and an active layer 630. Yes. In the active layer 630, the source region 631, the channel region 632, the low concentration drain region 633a and the high concentration drain region 633b of the first N channel MOS transistor 670 are formed, and the source region of the second N channel MOS transistor is formed. 636, a channel region 637, a low concentration drain region 638a, and a high concentration drain region 638b are formed. An insulating isolation region 634 is formed between the high-concentration drain region 633b of the first N-channel MOS transistor 670 and the source region 636 of the second N-channel MOS transistor 675.

  An insulating film 650 is formed on the active layer 630, and the gate 660 of the first N-channel MOS transistor 670, the gate 665 of the second N-channel MOS transistor 675, and the metal wirings 680 to 683 are formed in the insulating film 650. Is formed. The metal wirings 680 and 682 on the source regions 631 and 636 are connected by a metal wiring 684, and the metal wirings 681 and 683 on the high-concentration drain regions 633b and 638b are connected by a metal wiring 685. The gates 650 and 655 are connected to each other by a metal wiring 686.

  Thus, since the conventional power device has the first N-channel MOS transistor 670 and the second N-channel MOS transistor 675 arranged in a plane, the area is approximately as compared with the semiconductor device according to the third embodiment. It becomes twice. In addition, the gates 660 and 665 of the first and second N-channel MOS transistors 670 and 665, the source regions 631 and 636, and the high-concentration drain regions 633b and 638b are connected through the metal wirings 684 to 686. As a result, the electrical resistance increases.

  Returning to FIG. On the other hand, in the semiconductor device according to the third embodiment, the base substrate 290 in which the first N-channel MOS transistor 270 is formed and the multilayer substrate 295 in which the second N-channel MOS transistor 275 is formed are stacked. The plane area can be reduced to about half that of a conventional power device. Further, the gates 260 and 265, the source regions 231 and 236, and the high-concentration drain regions 233b and 238b are directly connected by direct bonding between the first N-channel MOS transistor 270 and the second N-channel MOS transistor 275. Therefore, the wiring length between the transistors can be shortened. As a result, the resistance of the wiring can be reduced, so that heat generation due to the resistance can be suppressed and high-speed operation can be achieved.

  In the semiconductor device according to the third embodiment, the surfaces of the base substrate 270 and the laminated substrate 275 can be polished and planarized so that the gates 260 and 265 are exposed, and the two can be bonded directly. Then, after bonding, the support substrate of the multilayer substrate 275 is removed, and the electrode 300 may be formed on the buried oxide film layer 225, and the manufacturing can be performed in the same procedure as the semiconductor device according to the second embodiment.

  FIG. 8C is a diagram showing an AA ′ cross section on the gates 260 and 265 on the semiconductor device according to the third embodiment. The input electrode 301 is connected to the gate 265 through the contact hole 331. The configuration is shown. Further, a state where the channel region 232 is surrounded by the gate 260 and the channel region 237 is surrounded by the gate 265 is shown.

  FIG. 8D is a diagram showing a BB ′ cross section on the high-concentration drain regions 233 b and 238 b of the semiconductor device according to the third embodiment, and outputs to the metal wirings 281 and 283 through the contact holes 332. A state in which the electrode 303 is connected is shown.

  As described above, the semiconductor device according to the third embodiment has substantially the same configuration and manufacture as the semiconductor device according to the second embodiment, except that the same conductive MOS transistors 270 and 275 are formed on the base substrate 290 and the multilayer substrate 275. Can be realized by the method.

  According to the semiconductor device according to the third embodiment, it is possible to provide a power device that can save space and increase the circuit operation speed.

  In the third embodiment, the example in which the N-channel MOS transistors 270 and 275 are stacked has been described. However, the P-channel MOS transistors may be stacked. Further, the N-channel MOS transistors 270 and 275 are not necessarily configured as power devices, and can be applied to various circuits using MOS transistors of the same conductivity type.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  In particular, in the first to third embodiments, the example in which the semiconductor element is a MOS transistor has been described. However, any transistor having a gate may be used, and the present invention may be applied to an IGBT (Insulated Gate Bipolar Transistor). it can.

  The present invention can be used for a transistor having a gate and a transistor circuit using the transistor.

10, 210 Support substrate 20, 25, 220, 225 Buried oxide layer 30, 35, 230, 235 Active layer 31, 36, 231, 236 Source region 32, 37, 232, 237 Channel region 33, 38, 233a, 233b 238a, 238b Drain region 34, 39, 234, 239 Insulation isolation region 40, 45 SOI substrate 50, 55, 250, 255 Insulating film 60, 65, 260, 265 Gate 70 P channel MOS transistor 75, 270, 275 N channel MOS transistor 80, 81, 85, 86, 280, 281, 282, 283 Metal wiring 90, 290 Base substrate 95, 295 Multilayer substrate 100, 101, 300, 301 Electrode 110 Interlayer insulating film 120, 302 Input electrode 121, 303 Output Electrode 130-13 , 330-332 contact hole

Claims (8)

A first semiconductor element having a first gate and first and second impurity diffusion regions formed below the first gate;
A second semiconductor element having a second gate joined opposite to the first gate, and third and fourth impurity diffusion regions formed in a layer above the second gate; A stacked semiconductor device comprising: A first semiconductor element having a first gate having a first metal wiring formed on a surface thereof, and first and second impurity diffusion regions formed in a lower layer than the first gate;
A second metal wiring is formed on the surface, the second metal wiring is joined to face the first metal wiring, and a second gate is formed above the second gate. And a second semiconductor element having a third impurity diffusion region and a fourth impurity diffusion region. The first semiconductor element is formed on a first substrate;
The second semiconductor element is formed on a second substrate;
A first insulating film is provided on the opposite surface of the first substrate to the first gate,
A second insulating film is provided on the opposite surface of the second substrate to the second gate,
A support substrate having a ground potential is provided on the surface of the first insulating film,
The stacked semiconductor device according to claim 1, wherein an electrode connected to the first semiconductor element and the second semiconductor element is provided on a surface of the second insulating film. .   4. The stacked semiconductor device according to claim 1, wherein the first and second semiconductor elements are MOS transistors. 5. The first semiconductor element is a P-channel MOS transistor;
The second semiconductor element is an N-channel MOS transistor;
5. The stacked semiconductor device according to claim 4, wherein the semiconductor device is a CMOS in which drains of the N-channel MOS transistor and the P-channel MOS transistor are connected to each other. Forming a first semiconductor element such that the first gate is disposed near the surface of the first substrate;
Forming a second semiconductor element such that the second gate is disposed near the surface of the second substrate;
Planarizing the surfaces of the first and second substrates;
Disposing the first substrate and the second substrate so that the first gate and the second gate face each other, and bonding the first substrate and the second substrate by direct bonding And a method of manufacturing a stacked semiconductor device. The step of forming the first semiconductor element includes a step of forming a first metal wiring on the first gate,
Forming the second semiconductor element includes forming a second metal wiring on the second gate;
7. The stacked semiconductor device according to claim 6, wherein in the step of bonding the first substrate and the second substrate, the first metal wiring and the second metal wiring are bonded. Manufacturing method. In the step of planarizing the surfaces of the first and second substrates, the first and second gates are exposed flat on the surfaces of the first and second substrates,
7. The stacked semiconductor device according to claim 6, wherein in the step of bonding the first substrate and the second substrate, the first gate and the second gate are bonded. Method.

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