JP4027740B2 - Method for manufacturing semiconductor device - Google Patents

Description

【００６９】
また、酸化シリコン膜、ＴｉＮ膜、Ｗ膜のそれぞれについて、熱処理（５５０℃、４時間）前後での内部応力を測定した。その結果を表２に示す。
【００７０】
【表２】

【００７１】
なお、酸化シリコン膜は、シリコン基板上にスパッタ法で４００ｎｍの膜厚で成膜したものを測定しており、ＴｉＮ膜、Ｗ膜においては、ガラス基板上にスパッタ法で４００ｎｍの膜厚で成膜した後、内部応力を測定し、その後、キャップ膜として酸化シリコン膜を積層し、熱処理を行った後でキャップ膜をエッチングで除去して再度、内部応力を測定した。また、それぞれサンプルは２つ作製し、測定を行った。
【００７２】
Ｗ膜においては、成膜直後では圧縮応力（約−７×１０⁹（Dyne/cm²））を有しているが、熱処理によって引張応力（約８×１０⁹〜９×１０⁹（Dyne/cm²））を有する膜になっており、剥離状態は良好であった。ＴｉＮ膜に関しては熱処理前後で応力はほとんど変わらず、引張応力（約３．９×１０⁹〜４．５×１０⁹（Dyne/cm²））を有したままであった。また、酸化シリコン膜に関しては熱処理前後で応力はほとんど変わらず、圧縮応力（約−９．４×１０⁸〜−１．３×１０⁹（Dyne/cm²））を有したままであった。
【００７３】
これらの結果から、剥離現象は、様々な要因による密着性と関係するが、特に内部応力と深い関係があり、窒化物層または金属層の上に酸化物層を形成した場合、窒化物層または金属層と酸化物層との界面から被剥離層を全面に渡って剥離することができることが読み取れる。
【００７４】
（実験４）
加熱温度の依存性を調べるため、以下の実験を行った。
【００７５】
サンプルとして、ガラス基板上にスパッタ法を用い、５０ｎｍの膜厚でＷ膜（タングステン膜）を形成した後、スパッタ法（シリコンターゲットを用い、アルゴンガス流量１０ｓｃｃｍ、酸素ガス流量３０ｓｃｃｍ、成膜圧力０．４Ｐａ、スパッタ電力３ｋＷ、基板温度３００℃）を用い、２００ｎｍの膜厚の酸化シリコン膜を形成した。次いで、実験１と同様にプラズマＣＶＤ法により下地絶縁層（酸化窒化シリコン膜５０ｎｍと酸化窒化シリコン膜１００ｎｍ）、非晶質シリコン膜を５４ｎｍの厚さで形成する。
【００７６】
次いで、加熱温度の条件を振って熱処理を行った後、接着剤を用いて石英基板を非晶質シリコン膜（或いはポリシリコン膜）表面に貼り付け、人間の手によって石英基板とガラス基板とが分離するように引っ張り、剥離可能かどうかを調べた。加熱温度の条件１として、５００℃、１時間、条件２として４５０℃、１時間、条件３として４２５℃、１時間、条件４として４１０℃、１時間、条件５として４００℃、１時間、条件６として３５０℃、１時間とした。
【００７７】
実験の結果、条件１〜４のサンプルでは剥離することができたが、条件５、条件６のサンプルでは剥離ができなかった。従って、本発明の剥離方法においては、少なくとも４１０℃以上の熱処理を行うことが好ましい。この４１０℃以上の温度とは水素が膜中から放出または膜中に拡散する温度である。
【００７８】
また、剥離させた際、Ｗ膜は、ガラス基板上に全面残っており、石英基板上に、積層（スパッタ法によるＳｉＯ₂膜、PCVD法による絶縁膜（１）及び（２）、非晶質シリコン膜）が転写される。転写されたＳｉＯ₂膜表面をＴＸＲＦで測定した結果が図２１であり、またＡＦＭで測定すると表面粗さＲｚ（３０ポイント）は５．４４ｎｍであった。また、リファレンスとして石英基板上に形成した５０ｎｍのＷ膜表面をＴＸＲＦで測定した結果が図２２であり、ＡＦＭで測定すると表面粗さＲｚ（３０ポイント）は２２．８ｎｍであった。また、石英基板のみをＴＸＲＦで測定した結果が図２３である。図２１と図２２とを比較すると同様のＷ（タングステン）のピークを有していることから、転写されたＳｉＯ₂膜表面には微小の金属材料（ここではＷ）が付着していることがわかる。
【００７９】
本明細書で開示する本発明の構成は、
支持体に接着材で接着された被剥離層は、酸化シリコン膜を有し、酸化シリコン膜と接着材との間には微量の金属材料を有する半導体装置である。
【００８０】
上記構成において、前記金属材料は、Ｗ、Ｔｉ、Ａｌ、Ｔａ、Ｍｏ、Ｃｕ、Ｃｒ、Ｎｄ、Ｆｅ、Ｎｉ、Ｃｏ、Ｚｒ、Ｚｎ、Ｒｕ、Ｒｈ、Ｐｄ、Ｏｓ、Ｉｒ、Ｐｔから選ばれた元素、または前記元素を主成分とする合金材料若しくは化合物材料であることを特徴としている。
【００８１】
【発明の実施の形態】
本発明の実施形態について、以下に説明する。
【００８２】
（実施の形態１）
以下に本発明を用いた代表的な剥離手順を簡略に図１を用いて示す。
【００８３】
図１（Ａ）中、１０は基板、１１は窒化物層または金属層、１２は酸化物層、１３は被剥離層である。
【００８４】
図１（Ａ）において、基板１０はガラス基板、石英基板、セラミック基板などを用いることができる。また、シリコン基板、金属基板またはステンレス基板を用いても良い。
【００８５】
まず、図１（Ａ）に示すように基板１０上に窒化物層または金属層１１を形成する。窒化物層または金属層１１として、代表的な一例はＴｉ、Ａｌ、Ｔａ、Ｗ、Ｍｏ、Ｃｕ、Ｃｒ、Ｎｄ、Ｆｅ、Ｎｉ、Ｃｏ、Ｚｒ、Ｚｎ、Ｒｕ、Ｒｈ、Ｐｄ、Ｏｓ、Ｉｒ、Ｐｔから選ばれた元素、または前記元素を主成分とする合金材料若しくは化合物材料からなる単層、またはこれらの積層、或いは、これらの窒化物、例えば、窒化チタン、窒化タングステン、窒化タンタル、窒化モリブデンからなる単層、またはこれらの積層を用いればよい。
【００８６】
次いで、窒化物層または金属層１１上に酸化物層１２を形成する。酸化物層１２として、代表的な一例は酸化シリコン、酸化窒化シリコン、酸化金属材料を用いればよい。なお、酸化物層１２は、スパッタ法、プラズマＣＶＤ法、塗布法などのいずれの成膜方法を用いてもよい。
【００８７】
本発明においては、この酸化物層１２の膜応力と、窒化物層または金属層１１の膜応力とを異ならせることが重要である。各々の膜厚は、１ｎｍ〜１０００ｎｍの範囲で適宜設定し、各々の膜応力を調節すればよい。また、図１では、プロセスの簡略化を図るため、基板１０に接して窒化物層または金属層１１を形成した例を示したが、基板１０と窒化物層または金属層１１との間に絶縁層や金属層を設け、基板１０との密着性を向上させてもよい。
【００８８】
次いで、酸化物層１２上に被剥離層１３を形成する。（図１（Ａ））被剥離層１３は、ＴＦＴを代表とする様々な素子（薄膜ダイオード、シリコンのＰＩＮ接合からなる光電変換素子やシリコン抵抗素子）を含む層とすればよい。また、基板１０の耐え得る範囲の熱処理を行うことができる。なお、本発明において、酸化物層１２の膜応力と、窒化物層または金属層１１の膜応力が異なっていても、被剥離層１３の作製工程における熱処理によって膜剥がれなどが生じない。
【００８９】
次いで、窒化物層または金属層１１が設けられている基板１０を物理的手段により引き剥がす。（図１（Ｂ））酸化物層１２の膜応力と、窒化物層または金属層１１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。また、ここでは、被剥離層１３の機械的強度が十分であると仮定した例を示しているが、被剥離層１３の機械的強度が不十分である場合には、被剥離層１３を固定する支持体（図示しない）を貼りつけた後、剥離することが好ましい。
【００９０】
こうして、酸化物層１２上に形成された被剥離層１３を基板１０から分離することができる。剥離後の状態を図１（Ｃ）に示す。
【００９１】
実験では、金属層１１としてタングステン膜１０ｎｍ、酸化物層１２としてスパッタ法による酸化シリコン膜２００ｎｍであっても本発明の剥離法により剥離が確認でき、金属層１１としてタングステン膜５０ｎｍと酸化物層１２としてスパッタ法による酸化シリコン膜１００ｎｍであっても本発明の剥離法により剥離が確認できている。また、金属層１１としてタングステン膜５０ｎｍと酸化物層１２としてスパッタ法による酸化シリコン膜４００ｎｍであっても本発明の剥離法により剥離が確認できている。
【００９２】
また、剥離した後、引き剥がした被剥離層１３を転写体（図示しない）に貼り付けてもよい。
【００９３】
また、本発明は様々な半導体装置の作製方法に用いることができる。特に、転写体や支持体をプラスチック基板とすることで、軽量化が図れる。
【００９４】
液晶表示装置を作製する場合は、支持体を対向基板とし、シール材を接着材として用いて支持体を被剥離層に接着すればよい。この場合、被剥離層に設けられた素子は画素電極を有しており、該画素電極と、前記対向基板との間には液晶材料が充填されるようにする。また、液晶表示装置を作製する順序は、特に限定されず、支持体としての対向基板を貼りつけ、液晶を注入した後に基板を剥離して転写体としてのプラスチック基板を貼りつけてもよいし、画素電極を形成した後、基板を剥離し、第１の転写体としてのプラスチック基板を貼り付けた後、第２の転写体としての対向基板を貼りつけてもよい。
【００９５】
また、ＥＬ素子を有する発光装置として代表される発光装置を作製する場合は、支持体を封止材として、外部から水分や酸素といった有機化合物層の劣化を促す物質が侵入することを防ぐように発光素子を外部から完全に遮断することが好ましい。また、ＥＬ素子を有する発光装置として代表される発光装置を作製する場合は、支持体だけでなく、転写体も同様、十分に外部から水分や酸素といった有機化合物層の劣化を促す物質が侵入することを防ぐことが好ましい。また、発光装置を作製する順序は、特に限定されず、発光素子を形成した後、支持体としてのプラスチック基板を貼りつけ、基板を剥離し、転写体としてのプラスチック基板を貼りつけてもよいし、発光素子を形成した後、基板を剥離して、第１の転写体としてのプラスチック基板を貼り付けた後、第２の転写体としてのプラスチック基板を貼りつけてもよい。
【００９６】
（実施の形態２）
本実施の形態は、被剥離層に接する下地絶縁層を設けて、窒化物層または金属層や基板からの不純物の拡散を防ぎつつ、基板を剥離する剥離手順を簡略に図２を用いて示す。
【００９７】
図２（Ａ）中、２０は基板、２１は窒化物層または金属層、２２は酸化物層、２３ａ、２３ｂは下地絶縁層、２４は被剥離層である。
【００９８】
図２（Ａ）において、基板２０はガラス基板、石英基板、セラミック基板などを用いることができる。また、シリコン基板、金属基板またはステンレス基板を用いても良い。
【００９９】
まず、図２（Ａ）に示すように基板２０上に窒化物層または金属層２１を形成する。窒化物層または金属層２１として、代表的な一例はＴｉ、Ａｌ、Ｔａ、Ｗ、Ｍｏ、Ｃｕ、Ｃｒ、Ｎｄ、Ｆｅ、Ｎｉ、Ｃｏ、Ｚｒ、Ｚｎ、Ｒｕ、Ｒｈ、Ｐｄ、Ｏｓ、Ｉｒ、Ｐｔから選ばれた元素、または前記元素を主成分とする合金材料若しくは化合物材料からなる単層、またはこれらの積層、或いは、これらの窒化物、例えば、窒化チタン、窒化タングステン、窒化タンタル、窒化モリブデンからなる単層、またはこれらの積層を用いればよい。
【０１００】
次いで、窒化物層または金属層２１上に酸化物層２２を形成する。酸化物層２２として、代表的な一例は酸化シリコン、酸化窒化シリコン、酸化金属材料を用いればよい。なお、酸化物層２２は、スパッタ法、プラズマＣＶＤ法、塗布法などのいずれの成膜方法を用いてもよい。
【０１０１】
本発明においては、この酸化物層２２の膜応力と、窒化物層または金属層２１の膜応力とを異ならせることが重要である。各々の膜厚は、１ｎｍ〜１０００ｎｍの範囲で適宜設定し、各々の膜応力を調節すればよい。また、図２では、プロセスの簡略化を図るため、基板２０に接して窒化物層または金属層２１を形成した例を示したが、基板２０と窒化物層または金属層２１との間に絶縁層や金属層を設け、基板２０との密着性を向上させてもよい。
【０１０２】
次いで、酸化物層２２上に下地絶縁層２３ａ、２３ｂを形成する。ここでは、プラズマＣＶＤ法で成膜温度４００℃、原料ガスＳｉＨ₄、ＮＨ₃、Ｎ₂Ｏから作製される酸化窒化シリコン膜２３ａ（組成比Ｓｉ＝３２％、Ｏ＝２７％、Ｎ＝２４％、Ｈ＝１７％）を５０nm（好ましくは１０〜２００nm）形成し、さらにプラズマＣＶＤ法で成膜温度４００℃、原料ガスＳｉＨ₄、Ｎ₂Ｏから作製される酸化窒化シリコン膜２３ｂ（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１００ｎｍ（好ましくは５０〜２００nm）の厚さに積層したが、特に限定されず、単層もしくは３層以上の積層であってもよい。
【０１０３】
次いで、下地絶縁層２３ｂ上に被剥離層２４を形成する。（図２（Ａ））
【０１０４】
このような２層の下地絶縁層２３ａ、２３ｂとした場合、被剥離層２４を形成するプロセスにおいて、窒化物層または金属層２１や基板２０からの不純物の拡散を防ぐことができる。また、下地絶縁層２３ａ、２３ｂにより酸化物層２２と被剥離層２４との密着性を向上させることもできる。
【０１０５】
また、窒化物層または金属層２１や酸化物層２２によって表面に凹凸が形成された場合、下地絶縁層を形成する前後に表面を平坦化してもよい。平坦化を行った方が、被剥離層２４においてカバレッジが良好となり、素子を含む被剥離層２４を形成する場合、素子特性が安定しやすいため好ましい。なお、この平坦化処理として、塗布膜（レジスト膜等）を形成した後エッチングなどを行って平坦化するエッチバック法や機械的化学的研磨法（ＣＭＰ法）等を用いればよい。
【０１０６】
次いで、窒化物層または金属層２１が設けられている基板２０を物理的手段により引き剥がす。（図２（Ｂ））酸化物層２２の膜応力と、窒化物層または金属層２１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。また、ここでは、被剥離層２４の機械的強度が十分であると仮定した例を示しているが、被剥離層２４の機械的強度が不十分である場合には、被剥離層２４を固定する支持体（図示しない）を貼りつけた後、剥離することが好ましい。
【０１０７】
こうして、下地絶縁層２２上に形成された被剥離層２４を基板２０から分離することができる。剥離後の状態を図２（Ｃ）に示す。
【０１０８】
また、剥離した後、引き剥がした被剥離層２４を転写体（図示しない）に貼り付けてもよい。
【０１０９】
また、本発明は様々な半導体装置の作製方法に用いることができる。特に、転写体や支持体をプラスチック基板とすることで、軽量化が図れる。
【０１１０】
液晶表示装置を作製する場合は、支持体を対向基板とし、シール材を接着材として用いて支持体を被剥離層に接着すればよい。この場合、被剥離層に設けられた素子は画素電極を有しており、該画素電極と、前記対向基板との間には液晶材料が充填されるようにする。また、液晶表示装置を作製する順序は、特に限定されず、支持体としての対向基板を貼りつけ、液晶を注入した後に基板を剥離して転写体としてのプラスチック基板を貼りつけてもよいし、画素電極を形成した後、基板を剥離し、第１の転写体としてのプラスチック基板を貼り付けた後、第２の転写体としての対向基板を貼りつけてもよい。
【０１１１】
また、ＥＬ素子を有する発光装置として代表される発光装置を作製する場合は、支持体を封止材として、外部から水分や酸素といった有機化合物層の劣化を促す物質が侵入することを防ぐように発光素子を外部から完全に遮断することが好ましい。また、ＥＬ素子を有する発光装置として代表される発光装置を作製する場合は、支持体だけでなく、転写体も同様、十分に外部から水分や酸素といった有機化合物層の劣化を促す物質が侵入することを防ぐことが好ましい。また、発光装置を作製する順序は、特に限定されず、発光素子を形成した後、支持体としてのプラスチック基板を貼りつけ、基板を剥離し、転写体としてのプラスチック基板を貼りつけてもよいし、発光素子を形成した後、基板を剥離して、第１の転写体としてのプラスチック基板を貼り付けた後、第２の転写体としてのプラスチック基板を貼りつけてもよい。
【０１１２】
（実施の形態３）
本実施の形態においては、実施の形態１に加えて、さらに剥離を助長させるため、レーザー光の照射または加熱処理を行う例を図４に示す。
【０１１３】
図４（Ａ）中、４０は基板、４１は窒化物層または金属層、４２は酸化物層、４３は被剥離層である。
【０１１４】
被剥離層４３まで形成する工程は、実施の形態１と同一であるので省略する。
【０１１５】
被剥離層４３を形成した後、レーザー光の照射を行う。（図３（Ａ））レーザー光としては、エキシマレーザー等の気体レーザーや、ＹＶＯ₄レーザーやＹＡＧレーザーなどの固体レーザーや、半導体レーザーを用いればよい。また、レーザー発振の形態は、連続発振、パルス発振のいずれでもよく、レーザービームの形状も線状、矩形状、円状、楕円状のいずれでもよい。また、使用する波長は、基本波、第２高調波、第３高調波のいずれでもよい。
【０１１６】
また、窒化物層または金属層４１として用いる材料は、レーザー光を吸収しやすい材料を用いることが望ましく、窒化チタンが好ましい。なお、レーザー光を通過させるため、基板４０は透光性を有している基板を用いる。
【０１１７】
次いで、窒化物層または金属層４１が設けられている基板４０を物理的手段により引き剥がす。（図４（Ｂ））酸化物層４２の膜応力と、窒化物層または金属層４１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。
【０１１８】
レーザー光を照射することによって、窒化物層または金属層４１と酸化物層４２との界面を加熱することにより、互いの膜応力を変化させて、剥離を助長することができ、さらに小さな力で剥離させることができる。また、ここでは、被剥離層４３の機械的強度が十分であると仮定した例を示しているが、被剥離層４３の機械的強度が不十分である場合には、被剥離層４３を固定する支持体（図示しない）を貼りつけた後、剥離することが好ましい。
【０１１９】
こうして、酸化物層４２上に形成された被剥離層４３を基板４０から分離することができる。剥離後の状態を図４（Ｃ）に示す。
【０１２０】
また、レーザー光に限定されず、ハロゲンランプ等の光源からの可視光、赤外線、紫外線、マイクロ波などを用いてもよい。
【０１２１】
また、レーザー光に代えて電気炉での加熱処理でもよい。
【０１２２】
また、支持体を接着する前、或いは、前記物理的手段により剥離する前に、加熱処理またはレーザー光の照射を行う処理を行ってもよい。
【０１２３】
また、本実施の形態は、実施の形態２と組み合わせることができる。
【０１２４】
（実施の形態４）
本実施の形態においては、実施の形態１に加えて、さらに剥離を助長させるため、粒状の酸化物を窒化物層または金属層と酸化物層との界面に設ける例を図５に示す。
【０１２５】
図５（Ａ）中、５０は基板、５１は窒化物層または金属層、５２ａは粒状の酸化物、５２ｂは酸化物層、５３は被剥離層である。
【０１２６】
窒化物層または金属層５１まで形成する工程は、実施の形態１と同一であるので省略する。
【０１２７】
窒化物層または金属層５１を形成した後、粒状の酸化物５２ａを形成する。粒状の酸化物５２ａとしては酸化金属材料、例えば、ＩＴＯ（酸化インジウム酸化スズ合金）、酸化インジウム酸化亜鉛合金（Ｉｎ₂Ｏ₃―ＺｎＯ）、酸化亜鉛（ＺｎＯ）等を用いればよい。
【０１２８】
次いで、粒状の酸化物５２ａを覆って酸化物層５２ｂを形成する。酸化物層５２ｂとして、代表的な一例は酸化シリコン、酸化窒化シリコン、酸化金属材料を用いればよい。なお、酸化物層２３ｂは、スパッタ法、プラズマＣＶＤ法、塗布法などのいずれの成膜方法を用いてもよい。
【０１２９】
次いで、酸化物層５２ｂ上に被剥離層５３を形成する。（図５（Ａ））
【０１３０】
次いで、窒化物層または金属層５１が設けられている基板５０を物理的手段により引き剥がす。（図５（Ｂ））酸化物層５２の膜応力と、窒化物層または金属層５１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。
【０１３１】
粒状の酸化物５２ｂを設けることによって、窒化物層または金属層５１と酸化物層５２との結合力を弱め、互いの密着性を変化させて、剥離を助長することができ、さらに小さな力で剥離させることができる。また、ここでは、被剥離層５３の機械的強度が十分であると仮定した例を示しているが、被剥離層５３の機械的強度が不十分である場合には、被剥離層５３を固定する支持体（図示しない）を貼りつけた後、剥離することが好ましい。
【０１３２】
こうして、酸化物層５２ｂ上に形成された被剥離層５３を基板５０から分離することができる。剥離後の状態を図５（Ｃ）に示す。
【０１３３】
また、本実施の形態は、実施の形態２、または実施の形態３と組み合わせることができる。
【０１３４】
以上の構成でなる本発明について、以下に示す実施例でもってさらに詳細な説明を行うこととする。
【０１３５】
（実施例）
［実施例１］
本発明の実施例を図６〜図８を用いて説明する。ここでは、同一基板上に画素部と、画素部の周辺に設ける駆動回路のＴＦＴ（ｎチャネル型ＴＦＴ及びｐチャネル型ＴＦＴ）を同時に作製する方法について詳細に説明する。
【０１３６】
まず、基板１００上に窒化物層または金属層１０１、酸化物層１０２、下地絶縁膜１０３を形成し、結晶構造を有する半導体膜を得た後、所望の形状にエッチング処理して島状に分離された半導体層１０４〜１０８を形成する。
【０１３７】
基板１００としては、ガラス基板（＃１７３７）を用いる。
【０１３８】
また、金属層１０１としては、Ｔｉ、Ａｌ、Ｔａ、Ｗ、Ｍｏ、Ｃｕ、Ｃｒ、Ｎｄ、Ｆｅ、Ｎｉ、Ｃｏ、Ｚｒ、Ｚｎ、Ｒｕ、Ｒｈ、Ｐｄ、Ｏｓ、Ｉｒ、Ｐｔから選ばれた元素、または前記元素を主成分とする合金材料若しくは化合物材料からなる単層、またはこれらの積層を用いればよい。さらに好ましくは、これらの窒化物、例えば、窒化チタン、窒化タングステン、窒化タンタル、窒化モリブデンからなる単層、またはこれらの積層を用いればよい。ここではスパッタ法で膜厚１００ｎｍの窒化チタン膜を用いる。
【０１３９】
また、酸化物層１０２としては、酸化シリコン材料または酸化金属材料からなる単層、またはこれらの積層を用いればよい。ここではスパッタ法で膜厚２００ｎｍの酸化シリコン膜を用いる。この金属層１０１と酸化物層１０２の結合力は熱処理には強く、膜剥がれ（ピーリングとも呼ばれる）などが生じないが、物理的手段で簡単に酸化物層の層内、あるいは界面において剥離することができる。
【０１４０】
また、下地絶縁膜１０３としては、プラズマＣＶＤ法で成膜温度４００℃、原料ガスＳｉＨ₄、ＮＨ₃、Ｎ₂Ｏから作製される酸化窒化シリコン膜１０３ａ（組成比Ｓｉ＝３２％、Ｏ＝２７％、Ｎ＝２４％、Ｈ＝１７％）を５０nm（好ましくは１０〜２００nm）形成する。次いで、表面をオゾン水で洗浄した後、表面の酸化膜を希フッ酸（１／１００希釈）で除去する。次いでプラズマＣＶＤ法で成膜温度４００℃、原料ガスＳｉＨ₄、Ｎ₂Ｏから作製される酸化窒化シリコン膜１０３ｂ（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１００ｎｍ（好ましくは５０〜２００nm）の厚さに積層形成し、さらに大気解放せずにプラズマＣＶＤ法で成膜温度３００℃、成膜ガスＳｉＨ₄で非晶質構造を有する半導体膜（ここではアモルファスシリコン膜）を５４ｎｍの厚さ（好ましくは２５〜８０ｎｍ）で形成する。
【０１４１】
本実施例では下地膜１０３を２層構造として示したが、前記絶縁膜の単層膜または２層以上積層させた構造として形成しても良い。また、半導体膜の材料に限定はないが、好ましくはシリコンまたはシリコンゲルマニウム（Ｓｉ_XＧｅ_1-X（Ｘ＝０．０００１〜０．０２））合金などを用い、公知の手段（スパッタ法、ＬＰＣＶＤ法、またはプラズマＣＶＤ法等）により形成すればよい。また、プラズマＣＶＤ装置は、枚葉式の装置でもよいし、バッチ式の装置でもよい。また、同一の成膜室で大気に触れることなく下地絶縁膜と半導体膜とを連続成膜してもよい。
【０１４２】
次いで、非晶質構造を有する半導体膜の表面を洗浄した後、オゾン水で表面に約２ｎｍの極薄い酸化膜を形成する。次いで、ＴＦＴのしきい値を制御するために微量な不純物元素（ボロンまたはリン）のドーピングを行う。ここでは、ジボラン（Ｂ₂Ｈ₆）を質量分離しないでプラズマ励起したイオンドープ法を用い、ドーピング条件を加速電圧１５ｋＶ、ジボランを水素で１％に希釈したガス流量３０ｓｃｃｍ、ドーズ量２×１０¹²／ｃｍ²で非晶質シリコン膜にボロンを添加した。
【０１４３】
次いで、重量換算で１０ppmのニッケルを含む酢酸ニッケル塩溶液をスピナーで塗布する。塗布に代えてスパッタ法でニッケル元素を全面に散布する方法を用いてもよい。
【０１４４】
次いで、加熱処理を行い結晶化させて結晶構造を有する半導体膜を形成する。この加熱処理は、電気炉の熱処理または強光の照射を用いればよい。電気炉の熱処理で行う場合は、５００℃〜６５０℃で４〜２４時間で行えばよい。ここでは脱水素化のための熱処理（５００℃、１時間）の後、結晶化のための熱処理（５５０℃、４時間）を行って結晶構造を有するシリコン膜を得る。なお、ここでは炉を用いた熱処理を用いて結晶化を行ったが、ランプアニール装置で結晶化を行ってもよい。なお、ここではシリコンの結晶化を助長する金属元素としてニッケルを用いた結晶化技術を用いたが、他の公知の結晶化技術、例えば固相成長法やレーザー結晶化法を用いてもよい。
【０１４５】
次いで、結晶構造を有するシリコン膜表面の酸化膜を希フッ酸等で除去した後、結晶化率を高め、結晶粒内に残される欠陥を補修するための第１のレーザー光（ＸｅＣｌ：波長３０８ｎｍ）の照射を大気中、または酸素雰囲気中で行う。レーザー光には波長４００nm以下のエキシマレーザ光や、ＹＡＧレーザの第２高調波、第３高調波を用いる。いずれにしても、繰り返し周波数１０〜１０００Hz程度のパルスレーザー光を用い、当該レーザー光を光学系にて１００〜５００mJ/cm²に集光し、９０〜９５％のオーバーラップ率をもって照射し、シリコン膜表面を走査させればよい。ここでは、繰り返し周波数３０Ｈｚ、エネルギー密度３９３mJ/cm²で第１のレーザー光の照射を大気中で行なう。なお、大気中、または酸素雰囲気中で行うため、第１のレーザー光の照射により表面に酸化膜が形成される。
【０１４６】
次いで、第１のレーザー光の照射により形成された酸化膜を希フッ酸で除去した後、第２のレーザー光の照射を窒素雰囲気、或いは真空中で行い、半導体膜表面を平坦化する。このレーザー光（第２のレーザー光）には波長４００nm以下のエキシマレーザー光や、ＹＡＧレーザーの第２高調波、第３高調波を用いる。第２のレーザー光のエネルギー密度は、第１のレーザー光のエネルギー密度より大きくし、好ましくは３０〜６０ｍＪ／ｃｍ²大きくする。ここでは、繰り返し周波数３０Ｈｚ、エネルギー密度４５３mJ/cm²で第２のレーザー光の照射を行ない、半導体膜表面における凹凸のＰ―Ｖ値（Peak to Valley、高さの最大値と最小値の差分）が５０ｎｍ以下となる。このＰ−Ｖ値は、ＡＦＭ（原子間力顕微鏡）により得られる。
【０１４７】
また、本実施例では第２のレーザー光の照射を全面に行ったが、オフ電流の低減は、画素部のＴＦＴに特に効果があるため、少なくとも画素部のみに選択的に照射する工程としてもよい。
【０１４８】
次いで、オゾン水で表面を１２０秒処理して合計１〜５ｎｍの酸化膜からなるバリア層を形成する。
【０１４９】
次いで、バリア層上にスパッタ法にてゲッタリングサイトとなるアルゴン元素を含む非晶質シリコン膜を膜厚１５０ｎｍで形成する。本実施例のスパッタ法による成膜条件は、成膜圧力を０．３Ｐａとし、ガス（Ａｒ）流量を５０（sccm）とし、成膜パワーを３ｋＷとし、基板温度を１５０℃とする。なお、上記条件での非晶質シリコン膜に含まれるアルゴン元素の原子濃度は、３×１０²⁰／ｃｍ³〜６×１０²⁰／ｃｍ³、酸素の原子濃度は１×１０¹⁹／ｃｍ³〜３×１０¹⁹／ｃｍ³である。その後、ランプアニール装置を用いて６５０℃、３分の熱処理を行いゲッタリングする。
【０１５０】
次いで、バリア層をエッチングストッパーとして、ゲッタリングサイトであるアルゴン元素を含む非晶質シリコン膜を選択的に除去した後、バリア層を希フッ酸で選択的に除去する。なお、ゲッタリングの際、ニッケルは酸素濃度の高い領域に移動しやすい傾向があるため、酸化膜からなるバリア層をゲッタリング後に除去することが望ましい。
【０１５１】
次いで、得られた結晶構造を有するシリコン膜（ポリシリコン膜とも呼ばれる）の表面にオゾン水で薄い酸化膜を形成した後、レジストからなるマスクを形成し、所望の形状にエッチング処理して島状に分離された半導体層１０４〜１０８を形成する。半導体層を形成した後、レジストからなるマスクを除去する。
【０１５２】
次いで、フッ酸を含むエッチャントで酸化膜を除去すると同時にシリコン膜の表面を洗浄した後、ゲート絶縁膜１０９となる珪素を主成分とする絶縁膜を形成する。本実施例では、プラズマＣＶＤ法により１１５ｎｍの厚さで酸化窒化シリコン膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）で形成する。
【０１５３】
次いで、図６（Ａ）に示すように、ゲート絶縁膜１０９上に膜厚２０〜１００ｎｍの第１の導電膜１１０ａと、膜厚１００〜４００ｎｍの第２の導電膜１１０ｂとを積層形成する。本実施例では、ゲート絶縁膜１０９上に膜厚５０ｎｍの窒化タンタル膜、膜厚３７０ｎｍのタングステン膜を順次積層する。
【０１５４】
第１の導電膜及び第２の導電膜を形成する導電性材料としてはＴａ、Ｗ、Ｔｉ、Ｍｏ、Ａｌ、Ｃｕから選ばれた元素、または前記元素を主成分とする合金材料もしくは化合物材料で形成する。また、第１の導電膜及び第２の導電膜としてリン等の不純物元素をドーピングした多結晶シリコン膜に代表される半導体膜や、、ＡｇＰｄＣｕ合金を用いてもよい。また、２層構造に限定されず、例えば、膜厚５０ｎｍのタングステン膜、膜厚５００ｎｍのアルミニウムとシリコンの合金（Ａｌ−Ｓｉ）膜、膜厚３０ｎｍの窒化チタン膜を順次積層した３層構造としてもよい。また、３層構造とする場合、第１の導電膜のタングステンに代えて窒化タングステンを用いてもよいし、第２の導電膜のアルミニウムとシリコンの合金（Ａｌ−Ｓｉ）膜に代えてアルミニウムとチタンの合金膜（Ａｌ−Ｔｉ）を用いてもよいし、第３の導電膜の窒化チタン膜に代えてチタン膜を用いてもよい。また、単層構造であってもよい。
【０１５５】
次に、図６（Ｂ）に示すように光露光工程によりレジストからなるマスク１１２〜１１７を形成し、ゲート電極及び配線を形成するための第１のエッチング処理を行う。第１のエッチング処理では第１及び第２のエッチング条件で行う。エッチングにはＩＣＰ（Inductively Coupled Plasma：誘導結合型プラズマ）エッチング法を用いると良い。ＩＣＰエッチング法を用い、エッチング条件（コイル型の電極に印加される電力量、基板側の電極に印加される電力量、基板側の電極温度等）を適宜調節することによって所望のテーパー形状に膜をエッチングすることができる。なお、エッチング用ガスとしては、Ｃｌ₂、ＢＣｌ₃、ＳｉＣｌ₄、ＣＣｌ₄などを代表とする塩素系ガスまたはＣＦ₄、ＳＦ₆、ＮＦ₃などを代表とするフッ素系ガス、またはＯ₂を適宜用いることができる。
【０１５６】
本実施例では、基板側（試料ステージ）にも１５０WのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。なお、基板側の電極面積サイズは、１２．５ｃｍ×１２．５ｃｍであり、コイル型の電極面積サイズ（ここではコイルの設けられた石英円板）は、直径２５ｃｍの円板である。この第１のエッチング条件によりＷ膜をエッチングして第１の導電層の端部をテーパー形状とする。第１のエッチング条件でのＷに対するエッチング速度は２００．３９ｎｍ／ｍｉｎ、ＴａＮに対するエッチング速度は８０．３２ｎｍ／ｍｉｎであり、ＴａＮに対するＷの選択比は約２．５である。また、この第１のエッチング条件によって、Ｗのテーパー角は、約２６°となる。この後、レジストからなるマスク１１２〜１１７を除去せずに第２のエッチング条件に変え、エッチング用ガスにＣＦ₄とＣｌ₂とを用い、それぞれのガス流量比を３０／３０（ｓｃｃｍ）とし、１Paの圧力でコイル型の電極に５００WのＲＦ（13.56MHz）電力を投入してプラズマを生成して約３０秒程度のエッチングを行った。基板側（試料ステージ）にも２０WのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。ＣＦ₄とＣｌ₂を混合した第２のエッチング条件ではＷ膜及びＴａＮ膜とも同程度にエッチングされる。第２のエッチング条件でのＷに対するエッチング速度は５８．９７ｎｍ／ｍｉｎ、ＴａＮに対するエッチング速度は６６．４３ｎｍ／ｍｉｎである。なお、ゲート絶縁膜上に残渣を残すことなくエッチングするためには、１０〜２０％程度の割合でエッチング時間を増加させると良い。
【０１５７】
上記第１のエッチング処理では、レジストからなるマスクの形状を適したものとすることにより、基板側に印加するバイアス電圧の効果により第１の導電層及び第２の導電層の端部がテーパー形状となる。このテーパー部の角度は１５〜４５°とすればよい。
【０１５８】
こうして、第１のエッチング処理により第１の導電層と第２の導電層から成る第１の形状の導電層１１９〜１２３（第１の導電層１１９ａ〜１２３ａと第２の導電層１１９ｂ〜１２３ｂ）を形成する。ゲート絶縁膜となる絶縁膜１０９は、１０〜２０nm程度エッチングされ、第１の形状の導電層１１９〜１２３で覆われない領域が薄くなったゲート絶縁膜１１８となる。
【０１５９】
次いで、レジストからなるマスクを除去せずに第２のエッチング処理を行う。ここでは、エッチング用ガスにＳＦ₆とＣｌ₂とＯ₂とを用い、それぞれのガス流量比を２４／１２／２４（ｓｃｃｍ）とし、１．３Paの圧力でコイル型の電極に７００WのＲＦ（13.56MHz）電力を投入してプラズマを生成してエッチングを２５秒行った。基板側（試料ステージ）にも１０WのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。第２のエッチング処理でのＷに対するエッチング速度は２２７．３ｎｍ／ｍｉｎ、ＴａＮに対するエッチング速度は３２．１ｎｍ／ｍｉｎであり、ＴａＮに対するＷの選択比は７．１であり、絶縁膜１１８であるＳｉＯＮに対するエッチング速度は３３．７ｎｍ／ｍｉｎであり、ＳｉＯＮに対するＷの選択比は６．８３である。このようにエッチングガス用ガスにＳＦ₆を用いた場合、絶縁膜１１８との選択比が高いので膜減りを抑えることができる。本実施例では絶縁膜１１８において約８ｎｍしか膜減りが起きない。
【０１６０】
この第２のエッチング処理によりＷのテーパー角は７０°となった。この第２のエッチング処理により第２の導電層１２６ｂ〜１３１ｂを形成する。一方、第１の導電層は、ほとんどエッチングされず、第１の導電層１２６ａ〜１３１ａとなる。なお、第１の導電層１２６ａ〜１３１ａは、第１の導電層１１９ａ〜１２４ａとほぼ同一サイズである。実際には、第１の導電層の幅は、第２のエッチング処理前に比べて約０．３μｍ程度、即ち線幅全体で０．６μｍ程度後退する場合もあるがほとんどサイズに変化がない。
【０１６１】
また、２層構造に代えて、膜厚５０ｎｍのタングステン膜、膜厚５００ｎｍのアルミニウムとシリコンの合金（Ａｌ−Ｓｉ）膜、膜厚３０ｎｍの窒化チタン膜を順次積層した３層構造とした場合、第１のエッチング処理の第１のエッチング条件としては、ＢＣｌ₃とＣｌ₂とＯ₂とを原料ガスに用い、それぞれのガス流量比を６５／１０／５（ｓｃｃｍ）とし、基板側（試料ステージ）に３００ＷのＲＦ（１３．５６ＭＨｚ）電力を投入し、１．２Ｐａの圧力でコイル型の電極に４５０ＷのＲＦ（１３．５６ＭＨｚ）電力を投入してプラズマを生成して１１７秒のエッチングを行えばよく、第１のエッチング処理の第２のエッチング条件としては、ＣＦ₄とＣｌ₂とＯ₂とを用い、それぞれのガス流量比を２５／２５／１０（ｓｃｃｍ）とし、基板側（試料ステージ）にも２０ＷのＲＦ（１３．５６ＭＨｚ）電力を投入し、１Ｐａの圧力でコイル型の電極に５００ＷのＲＦ（１３．５６ＭＨｚ）電力を投入してプラズマを生成して約３０秒程度のエッチングを行えばよく、第２のエッチング処理としてはＢＣｌ₃とＣｌ₂を用い、それぞれのガス流量比を２０／６０（sccm）とし、基板側（試料ステージ）には１００ＷのＲＦ（１３．５６ＭＨｚ）電力を投入し、１．２Ｐａの圧力でコイル型の電極に６００ＷのＲＦ（１３．５６ＭＨｚ）電力を投入してプラズマを生成してエッチングを行えばよい。
【０１６２】
次いで、レジストからなるマスクを除去した後、第１のドーピング処理を行って図６（Ｄ）の状態を得る。ドーピング処理はイオンドープ法、もしくはイオン注入法で行えば良い。イオンドープ法の条件はドーズ量を１．５×１０¹⁴atoms/cm²とし、加速電圧を６０〜１００ｋｅＶとして行う。ｎ型を付与する不純物元素として、典型的にはリン（Ｐ）または砒素（Ａｓ）を用いる。この場合、第１の導電層及び第２の導電層１２６〜１３０がｎ型を付与する不純物元素に対するマスクとなり、自己整合的に第１の不純物領域１３２〜１３６が形成される。第１の不純物領域１３２〜１３６には１×１０¹⁶〜１×１０¹⁷/cm³の濃度範囲でｎ型を付与する不純物元素を添加する。ここでは、第１の不純物領域と同じ濃度範囲の領域をｎ^--領域とも呼ぶ。
【０１６３】
なお、本実施例ではレジストからなるマスクを除去した後、第１のドーピング処理を行ったが、レジストからなるマスクを除去せずに第１のドーピング処理を行ってもよい。
【０１６４】
次いで、図７（Ａ）に示すようにレジストからなるマスク１３７〜１３９を形成し第２のドーピング処理を行う。マスク１３７は駆動回路のｐチャネル型ＴＦＴを形成する半導体層のチャネル形成領域及びその周辺の領域を保護するマスクであり、マスク１３８は駆動回路のｎチャネル型ＴＦＴの一つを形成する半導体層のチャネル形成領域及びその周辺の領域を保護するマスクであり、マスク１３９は画素部のＴＦＴを形成する半導体層のチャネル形成領域及びその周辺の領域と保持容量となる領域とを保護するマスクである。
【０１６５】
第２のドーピング処理におけるイオンドープ法の条件はドーズ量を１．５×１０¹⁵atoms/cm²とし、加速電圧を６０〜１００ｋｅＶとしてリン（Ｐ）をドーピングする。ここでは、第２の導電層１２６ｂ〜１２８ｂをマスクとして各半導体層に不純物領域が自己整合的に形成される。勿論、マスク１３７〜１３９で覆われた領域には添加されない。こうして、第２の不純物領域１４０〜１４２と、第３の不純物領域１４４が形成される。第２の不純物領域１４０〜１４２には１×１０²⁰〜１×１０²¹/cm³の濃度範囲でｎ型を付与する不純物元素を添加されている。ここでは、第２の不純物領域と同じ濃度範囲の領域をｎ⁺領域とも呼ぶ。
【０１６６】
また、第３の不純物領域は第１の導電層により第２の不純物領域よりも低濃度に形成され、１×１０¹⁸〜１×１０¹⁹/cm³の濃度範囲でｎ型を付与する不純物元素を添加されることになる。なお、第３の不純物領域は、テーパー形状である第１の導電層の部分を通過させてドーピングを行うため、テーパ−部の端部に向かって不純物濃度が増加する濃度勾配を有している。ここでは、第３の不純物領域と同じ濃度範囲の領域をｎ^-領域とも呼ぶ。また、マスク１３８、１３９で覆われた領域は、第２のドーピング処理で不純物元素が添加されず、第１の不純物領域１４６、１４７となる。
【０１６７】
次いで、レジストからなるマスク１３７〜１３９を除去した後、新たにレジストからなるマスク１４８〜１５０を形成して図７（Ｂ）に示すように第３のドーピング処理を行う。
【０１６８】
駆動回路において、上記第３のドーピング処理により、ｐチャネル型ＴＦＴを形成する半導体層および保持容量を形成する半導体層にｐ型の導電型を付与する不純物元素が添加された第４の不純物領域１５１、１５２及び第５の不純物領域１５３、１５４を形成する。
【０１６９】
また、第４の不純物領域１５１、１５２には１×１０²⁰〜１×１０²¹/cm³の濃度範囲でｐ型を付与する不純物元素が添加されるようにする。尚、第４の不純物領域１５１、１５２には先の工程でリン（Ｐ）が添加された領域（ｎ^--領域）であるが、ｐ型を付与する不純物元素の濃度がその１．５〜３倍添加されていて導電型はｐ型となっている。ここでは、第４の不純物領域と同じ濃度範囲の領域をｐ⁺領域とも呼ぶ。
【０１７０】
また、第５の不純物領域１５３、１５４は第２の導電層１２７ａのテーパー部と重なる領域に形成されるものであり、１×１０¹⁸〜１×１０²⁰/cm³の濃度範囲でｐ型を付与する不純物元素が添加されるようにする。ここでは、第５の不純物領域と同じ濃度範囲の領域をｐ^-領域とも呼ぶ。
【０１７１】
以上までの工程でそれぞれの半導体層にｎ型またはｐ型の導電型を有する不純物領域が形成される。導電層１２６〜１２９はＴＦＴのゲート電極となる。また、導電層１３０は画素部において保持容量を形成する一方の電極となる。さらに、導電層１３１は画素部においてソース配線を形成する。
【０１７２】
次いで、ほぼ全面を覆う絶縁膜（図示しない）を形成する。本実施例では、プラズマＣＶＤ法により膜厚５０ｎｍの酸化シリコン膜を形成した。勿論、この絶縁膜は酸化シリコン膜に限定されるものでなく、他のシリコンを含む絶縁膜を単層または積層構造として用いても良い。
【０１７３】
次いで、それぞれの半導体層に添加された不純物元素を活性化処理する工程を行う。この活性化工程は、ランプ光源を用いたラピッドサーマルアニール法（ＲＴＡ法）、或いはＹＡＧレーザーまたはエキシマレーザーを裏面から照射する方法、或いは炉を用いた熱処理、或いはこれらの方法のうち、いずれかと組み合わせた方法によって行う。
【０１７４】
また、本実施例では、上記活性化の前に絶縁膜を形成した例を示したが、上記活性化を行った後、絶縁膜を形成する工程としてもよい。
【０１７５】
次いで、窒化シリコン膜からなる第１の層間絶縁膜１５５を形成して熱処理（３００〜５５０℃で１〜１２時間の熱処理）を行い、半導体層を水素化する工程を行う。（図７（Ｃ））この工程は第１の層間絶縁膜１５５に含まれる水素により半導体層のダングリングボンドを終端する工程である。酸化シリコン膜からなる絶縁膜（図示しない）の存在に関係なく半導体層を水素化することができる。ただし、本実施例では、第２の導電層としてアルミニウムを主成分とする材料を用いているので、水素化する工程において第２の導電層が耐え得る熱処理条件とすることが重要である。水素化の他の手段として、プラズマ水素化（プラズマにより励起された水素を用いる）を行っても良い。
【０１７６】
次いで、第１の層間絶縁膜１５５上に有機絶縁物材料から成る第２の層間絶縁膜１５６を形成する。本実施例では膜厚１．６μｍのアクリル樹脂膜を形成する。次いで、ソース配線１３１に達するコンタクトホールと、導電層１２９、１３０に達するコンタクトホールと、各不純物領域に達するコンタクトホールを形成する。本実施例では複数のエッチング処理を順次行う。本実施例では第１の層間絶縁膜をエッチングストッパーとして第２の層間絶縁膜をエッチングした後、絶縁膜（図示しない）をエッチングストッパーとして第１の層間絶縁膜をエッチングしてから絶縁膜（図示しない）をエッチングした。
【０１７７】
その後、Ａｌ、Ｔｉ、Ｍｏ、Ｗなどを用いて配線及び画素電極を形成する。これらの電極及び画素電極の材料は、ＡｌまたはＡｇを主成分とする膜、またはそれらの積層膜等の反射性の優れた材料を用いることが望ましい。こうして、ソース電極またはドレイン電極１５７〜１６２、ゲート配線１６４、接続配線１６３、画素電極１６５が形成される。
【０１７８】
以上の様にして、ｎチャネル型ＴＦＴ２０１、ｐチャネル型ＴＦＴ２０２、ｎチャネル型ＴＦＴ２０３を有する駆動回路２０６と、ｎチャネル型ＴＦＴからなる画素ＴＦＴ２０４、保持容量２０５とを有する画素部２０７を同一基板上に形成することができる。（図８）本明細書中ではこのような基板を便宜上アクティブマトリクス基板と呼ぶ。
【０１７９】
画素部２０７において、画素ＴＦＴ２０４（ｎチャネル型ＴＦＴ）にはチャネル形成領域１６９、ゲート電極を形成する導電層１２９の外側に形成される第１の不純物領域（ｎ^--領域）１４７と、ソース領域またはドレイン領域として機能する第２の不純物領域（ｎ⁺領域）１４２、１７１を有している。また、保持容量２０５の一方の電極として機能する半導体層には第４の不純物領域１５２、第５の不純物領域１５４が形成されている。保持容量２０５は、絶縁膜（ゲート絶縁膜と同一膜）１１８を誘電体として、第２の電極１３０と、半導体層１５２、１５４、１７０とで形成されている。
【０１８０】
また、駆動回路２０６において、ｎチャネル型ＴＦＴ２０１（第１のｎチャネル型ＴＦＴ）はチャネル形成領域１６６、ゲート電極を形成する導電層１２６の一部と絶縁膜を介して重なる第３の不純物領域（ｎ^-領域）１４４とソース領域またはドレイン領域として機能する第２の不純物領域（ｎ⁺領域）１４０を有している。
【０１８１】
また、駆動回路２０６において、ｐチャネル型ＴＦＴ２０２にはチャネル形成領域１６７、ゲート電極を形成する導電層１２７の一部と絶縁膜を介して重なる第５不純物領域（ｐ^-領域）１５３とソース領域またはドレイン領域として機能する第４の不純物領域（ｐ⁺領域）１５１を有している。
【０１８２】
また、駆動回路２０６において、ｎチャネル型ＴＦＴ２０３（第２のｎチャネル型ＴＦＴ）にはチャネル形成領域１６８、ゲート電極を形成する導電層１２８の外側に第１の不純物領域（ｎ^--領域）１４６とソース領域またはドレイン領域として機能する第２の不純物領域（ｎ⁺領域）１４１を有している。
【０１８３】
これらのＴＦＴ２０１〜２０３を適宜組み合わせてシフトレジスタ回路、バッファ回路、レベルシフタ回路、ラッチ回路などを形成し、駆動回路２０６を形成すればよい。例えば、ＣＭＯＳ回路を形成する場合には、ｎチャネル型ＴＦＴ２０１とｐチャネル型ＴＦＴ２０２を相補的に接続して形成すればよい。
【０１８４】
特に、駆動電圧が高いバッファ回路には、ホットキャリア効果による劣化を防ぐ目的から、ｎチャネル型ＴＦＴ２０３の構造が適している。
【０１８５】
また、信頼性が最優先とされる回路には、ＧＯＬＤ構造であるｎチャネル型ＴＦＴ２０１の構造が適している。
【０１８６】
また、半導体膜表面の平坦化を向上させることによって信頼性を向上させることができるので、ＧＯＬＤ構造のＴＦＴにおいて、ゲート電極とゲート絶縁膜を介して重なる不純物領域の面積を縮小しても十分な信頼性を得ることができる。具体的にはＧＯＬＤ構造のＴＦＴにおいてゲート電極のテーパー部となる部分サイズを小さくしても十分な信頼性を得ることができる。
【０１８７】
また、ＧＯＬＤ構造のＴＦＴにおいてはゲート絶縁膜が薄くなると寄生容量が増加するが、ゲート電極（第１導電層）のテーパー部となる部分サイズを小さくして寄生容量を低減すれば、ｆ特性（周波数特性）も向上してさらなる高速動作が可能となり、且つ、十分な信頼性を有するＴＦＴとなる。
【０１８８】
なお、画素部２０７の画素ＴＦＴにおいても、第２のレーザー光の照射によりオフ電流の低減、およびバラツキの低減が実現される。
【０１８９】
また、本実施例では反射型の表示装置を形成するためのアクティブマトリクス基板を作製する例を示したが、画素電極を透明導電膜で形成すると、フォトマスクは１枚増えるものの、透過型の表示装置を形成することができる。
【０１９０】
また、本実施例ではガラス基板を用いたが、特に限定されず、石英基板、半導体基板、セラミックス基板、金属基板を用いることができる。
【０１９１】
また、図８の状態を得た後、酸化物層１０２上に設けたＴＦＴを含む層（被剥離層）の機械的強度が十分であれば、基板１００を引き剥がしてもよい。本実施例は、被剥離層の機械的強度が不十分であるので、被剥離層を固定する支持体（図示しない）を貼りつけた後、剥離することが好ましい。
【０１９２】
［実施例２］
本実施例では、実施例１で作製したアクティブマトリクス基板から、基板１００を剥離してプラスチック基板を貼り合わせてアクティブマトリクス型液晶表示装置を作製する工程を以下に説明する。説明には図９を用いる。
【０１９３】
図９（Ａ）において、４００は基板、４０１は窒化物層または金属層、４０２は酸化物層、４０３は下地絶縁層、４０４ａは駆動回路４１３の素子、４０４ｂは画素部４１４の素子４０４ｂ、４０５は画素電極である。ここで素子とは、アクティブマトリクス型の液晶表示装置において、画素のスイッチング素子として用いる半導体素子（典型的にはＴＦＴ）もしくはＭＩＭ素子等を指す。図９（Ａ）に示したアクティブマトリクス基板は図８に示したアクティブマトリクス基板を簡略化して示したものであり、図８中の基板１００は図９（Ａ）中の基板４００に対応している。同様に図９（Ａ）中の４０１は、図８中の１０１に、図９（Ａ）中の４０２は、図８中の１０２に、図９（Ａ）中の４０３は、図８中の１０３に、図９（Ａ）中の４０４ａは、図８中の２０１及び２０２に、図９（Ａ）中の４０４ｂは、図８中の２０４に、図９（Ａ）中の４０５は、図８中の１６５にそれぞれ対応している。
【０１９４】
まず、実施例１に従い、図８の状態のアクティブマトリクス基板を得た後、図８のアクティブマトリクス基板上に配向膜４０６ａを形成しラビング処理を行う。なお、本実施例では配向膜を形成する前に、アクリル樹脂膜等の有機樹脂膜をパターニングすることによって基板間隔を保持するための柱状のスペーサ（図示しない）を所望の位置に形成した。また、柱状のスペーサに代えて、球状のスペーサを基板全面に散布してもよい。
【０１９５】
次いで、支持体４０７となる対向基板を用意する。この対向基板には、着色層、遮光層が各画素に対応して配置されたカラーフィルタ（図示しない）が設けられている。また、駆動回路の部分にも遮光層を設けた。このカラーフィルタと遮光層とを覆う平坦化膜（図示しない）を設けた。次いで、平坦化膜上に透明導電膜からなる対向電極４０８を画素部に形成し、対向基板の全面に配向膜４０６ｂを形成し、ラビング処理を施した。
【０１９６】
そして、画素部と駆動回路が形成されたアクティブマトリクス基板４００と支持体４０７とを接着層４０９となるシール材で貼り合わせる。シール材にはフィラーが混入されていて、このフィラーと柱状スペーサによって均一な間隔を持って２枚の基板が貼り合わせられる。その後、両基板の間に液晶材料４１０を注入し、封止剤（図示せず）によって完全に封止する。（図９（Ｂ））液晶材料４１０には公知の液晶材料を用いれば良い。
【０１９７】
次いで、窒化物層または金属層４０１が設けられている基板４００を物理的手段により引き剥がす。（図９（Ｃ））酸化物層４０２の膜応力と、窒化物層または金属層４０１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。
【０１９８】
次いで、エポキシ樹脂などの接着層４１１により転写体４１２に貼り付ける。本実施例では、転写体４１２をプラスチックフィルム基板とすることで、軽量化を図る。
【０１９９】
このようにしてフレキシブルなアクティブマトリクス型液晶表示装置が完成する。そして、必要があれば、フレキシブルな基板４１２または対向基板を所望の形状に分断する。さらに、公知の技術を用いて偏光板（図示しない）等を適宜設けた。そして、公知の技術を用いてＦＰＣ（図示しない）を貼りつけた。
【０２００】
［実施例３］
実施例２では、支持体としての対向基板を貼りつけ、液晶を注入した後に基板を剥離して転写体としてのプラスチック基板を貼りつけた例を示したが、本実施例では、図８に示したアクティブマトリクス基板を形成した後、基板を剥離し、第１の転写体としてのプラスチック基板と、第２の転写体としてのプラスチック基板を貼りつけた例である。説明には図１０を用いる。
【０２０１】
図１０（Ａ）において、５００は基板、５０１は窒化物層または金属層、５０２は酸化物層、５０３は下地絶縁層、５０４ａは駆動回路５１４の素子、５０４ｂは画素部５１５の素子５０４ｂ、５０５は画素電極である。図１０（Ａ）に示したアクティブマトリクス基板は図８に示したアクティブマトリクス基板を簡略化して示したものであり、図８中の基板１００は図１０（Ａ）中の基板５００に対応している。同様に図１０（Ａ）中の５０１は、図８中の１０１に、図１０（Ａ）中の５０２は、図８中の１０２に、図１０（Ａ）中の５０３は、図８中の１０３に、図１０（Ａ）中の５０４ａは、図８中の２０１及び２０２に、図１０（Ａ）中の５０４ｂは、図８中の２０４に、図１０（Ａ）中の５０５は、図８中の１６５にそれぞれ対応している。
【０２０２】
まず、実施例１に従い、図８の状態のアクティブマトリクス基板を得た後、窒化物層または金属層５０１が設けられている基板５００を物理的手段により引き剥がす。（図１０（Ｂ））酸化物層５０２の膜応力と、窒化物層または金属層５０１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。
【０２０３】
次いで、エポキシ樹脂などの接着層５０６により転写体５０７（第１の転写体）に貼り付ける。本実施例では、転写体５０７をプラスチックフィルム基板とすることで、軽量化を図る。（図１０（Ｃ））
【０２０４】
次いで、配向膜５０８ａを形成しラビング処理を行う。なお、本実施例では配向膜を形成する前に、アクリル樹脂膜等の有機樹脂膜をパターニングすることによって基板間隔を保持するための柱状のスペーサ（図示しない）を所望の位置に形成した。また、柱状のスペーサに代えて、球状のスペーサを基板全面に散布してもよい。
【０２０５】
次いで、支持体５１０（第２の転写体）となる対向基板を用意する。この対向基板には、着色層、遮光層が各画素に対応して配置されたカラーフィルタ（図示しない）が設けられている。また、駆動回路の部分にも遮光層を設けた。このカラーフィルタと遮光層とを覆う平坦化膜（図示しない）を設けた。次いで、平坦化膜上に透明導電膜からなる対向電極５０９を画素部に形成し、対向基板の全面に配向膜５０８ｂを形成し、ラビング処理を施した。
【０２０６】
そして、画素部と駆動回路が接着されたプラスチックフィルム基板５０７と支持体５１０とを接着層５１２となるシール材で貼り合わせる。（図１０（Ｄ））シール材にはフィラーが混入されていて、このフィラーと柱状スペーサによって均一な間隔を持って２枚の基板が貼り合わせられる。その後、両基板の間に液晶材料５１３を注入し、封止剤（図示せず）によって完全に封止する。（図１０（Ｄ））液晶材料５１３には公知の液晶材料を用いれば良い。
【０２０７】
このようにしてフレキシブルなアクティブマトリクス型液晶表示装置が完成する。そして、必要があれば、フレキシブルな基板５０７または対向基板を所望の形状に分断する。さらに、公知の技術を用いて偏光板（図示しない）等を適宜設けた。そして、公知の技術を用いてＦＰＣ（図示しない）を貼りつけた。
【０２０８】
［実施例４］
実施例２または実施例３により得られた液晶モジュールの構成を図１１の上面図を用いて説明する。実施例２における基板４１２、または実施例３における基板５０７が基板３０１に対応する。
【０２０９】
基板３０１の中央には、画素部３０４が配置されている。画素部３０４の上側には、ソース信号線を駆動するためのソース信号線駆動回路３０２が配置されている。画素部３０４の左右には、ゲート信号線を駆動するためのゲート信号線駆動回路３０３が配置されている。本実施例に示した例では、ゲート信号線駆動回路３０３は画素部に対して左右対称配置としているが、これは片側のみの配置でも良く、液晶モジュールの基板サイズ等を考慮して、設計者が適宜選択すれば良い。ただし、回路の動作信頼性や駆動効率等を考えると、図１１に示した左右対称配置が望ましい。
【０２１０】
各駆動回路への信号の入力は、フレキシブルプリント基板（Flexible Print Circuit：ＦＰＣ）３０５から行われる。ＦＰＣ３０５は、基板３０１の所定の場所まで配置された配線に達するように、層間絶縁膜および樹脂膜にコンタクトホールを開口し、接続電極３０９を形成した後、異方性導電膜等を介して圧着される。本実施例においては、接続電極はＩＴＯを用いて形成した。
【０２１１】
駆動回路、画素部の周辺には、基板外周に沿ってシール剤３０７が塗布され、あらかじめフィルム基板上に形成されたスペーサ３１０によって一定のギャップ（基板３０１と対向基板３０６との間隔）を保った状態で、対向基板３０６が貼り付けられる。その後、シール剤３０７が塗布されていない部分より液晶材料が注入され、封止剤３０８によって密閉される。以上の工程により、液晶モジュールが完成する。
【０２１２】
また、ここでは全ての駆動回路をフィルム基板上に形成した例を示したが、駆動回路の一部に数個のＩＣを用いてもよい。
【０２１３】
また、本実施例は、実施例１と自由に組みあわせることが可能である。
【０２１４】
［実施例５］
実施例１では画素電極が反射性を有する金属材料で形成された反射型の表示装置の例を示したが、本実施例では画素電極を透光性を有する導電膜で形成した透過型の表示装置の例を示す。
【０２１５】
層間絶縁膜を形成する工程までは実施例１と同じであるので、ここでは省略する。実施例１に従ってＴＦＴおよび層間絶縁膜を形成した後、透光性を有する導電膜からなる画素電極６０１を形成する。透光性を有する導電膜としては、ＩＴＯ（酸化インジウム酸化スズ合金）、酸化インジウム酸化亜鉛合金（Ｉｎ₂Ｏ₃―ＺｎＯ）、酸化亜鉛（ＺｎＯ）等を用いればよい。
【０２１６】
その後、層間絶縁膜６００にコンタクトホールを形成する。次いで、画素電極と重なる接続電極６０２を形成する。この接続電極６０２は、コンタクトホールを通じてドレイン領域と接続されている。また、この接続電極と同時に他のＴＦＴのソース電極またはドレイン電極も形成する。
【０２１７】
また、ここでは全ての駆動回路を基板上に形成した例を示したが、駆動回路の一部に数個のＩＣを用いてもよい。
【０２１８】
以上のようにしてアクティブマトリクス基板が形成される。このアクティブマトリクス基板を用い、基板を剥離した後、プラスチック基板を貼り合わせ、実施例２〜４に従って液晶モジュールを作製し、バックライト６０４、導光板６０５を設け、カバー６０６で覆えば、図１２にその断面図の一部を示したようなアクティブマトリクス型液晶表示装置が完成する。なお、カバーと液晶モジュールは接着剤や有機樹脂を用いて貼り合わせる。また、プラスチック基板と対向基板を貼り合わせる際、枠で囲んで有機樹脂を枠と基板との間に充填して接着してもよい。また、透過型であるので偏光板６０３は、プラスチック基板と対向基板の両方に貼り付ける。
【０２１９】
また、本実施例は、実施例１乃至４と自由に組みあわせることが可能である。
【０２２０】
［実施例６］
本実施例では、プラスチック基板上に形成された有機発光素子を備えた発光装置を作製する例を図１３に示す。
【０２２１】
図１３（Ａ）において、６００は基板、６０１は窒化物層または金属層、６０２は酸化物層、６０３は下地絶縁層、６０４ａは駆動回路６１１の素子、６０４ｂ、６０４ｃは画素部６１２の素子、６０５はＥＬ素子（Organic Light Emitting Device）である。ここで素子とは、アクティブマトリクス型の発光装置ならば画素のスイッチング素子として用いる半導体素子（典型的にはＴＦＴ）もしくはＭＩＭ素子並びにＥＬ素子等を指す。そして、これらの素子を覆って、層間絶縁膜６０６を形成する。層間絶縁膜６０６は、成膜後の表面がより平坦であることが好ましい。なお、層間絶縁膜６０６は必ずしも設ける必要はない。
【０２２２】
なお、基板６００上に設ける６０１〜６０３は実施の形態２乃至４のいずれか一に従って形成すればよい。
【０２２３】
これらの素子（６０４ａ、６０４ｂ、６０４ｃを含む）は、上記実施例１のｎチャネル型ＴＦＴ２０１、上記実施例１のｐチャネル型ＴＦＴ２０２に従って作製すればよい。なお、ここでは一つの画素に２つのＴＦＴを用いた例を示したが、３つ、またはそれ以上のＴＦＴを用いてもよい。
【０２２４】
ＥＬ素子６０５は、電場を加えることで発生するルミネッセンス（Electroluminescence）が得られる有機化合物（有機発光材料）を含む層（以下、有機発光層と記す）と、陽極層と、陰極層とを有している。有機化合物におけるルミネッセンスには、一重項励起状態から基底状態に戻る際の発光（蛍光）と三重項励起状態から基底状態に戻る際の発光（リン光）とがあるが、本発明の発光装置は、上述した発光のうちの、いずれか一方の発光を用いていても良いし、または両方の発光を用いていても良い。なお、本明細書では、ＥＬ素子の陽極と陰極の間に形成された全ての層を有機発光層と定義する。有機発光層には具体的に、発光層、正孔注入層、電子注入層、正孔輸送層、電子輸送層等が含まれる。基本的にＥＬ素子は、陽極／発光層／陰極が順に積層された構造を有しており、この構造に加えて、陽極／正孔注入層／発光層／陰極や、陽極／正孔注入層／発光層／電子輸送層／陰極等の順に積層した構造を有していることもある。
【０２２５】
上記方法により、図１３（Ａ）の状態を得たら、接着層６０７により支持体６０８を貼り合わせる。（図１３（Ｂ））本実施例では支持体６０８としてプラスチック基板を用いる。具体的には、支持体として、厚さ１０μｍ以上の樹脂基板、例えばＰＥＳ（ポリエチレンサルファイル）、ＰＣ（ポリカーボネート）、ＰＥＴ（ポリエチレンテレフタレート）もしくはＰＥＮ（ポリエチレンナフタレート）を用いることができる。なお、ＥＬ素子から見て観測者側（発光装置の使用者側）に位置する場合、支持体６０８および接着層６０７は、光を透過する材料であることが必要である。
【０２２６】
次いで、窒化物層または金属層６０１が設けられている基板６００を物理的手段により引き剥がす。（図１３（Ｃ））酸化物層６０２の膜応力と、窒化物層または金属層６０１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。
【０２２７】
次いで、エポキシ樹脂などの接着層６０９により転写体６１０に貼り付ける。（図１３（Ｄ））本実施例では、転写体６１０をプラスチックフィルム基板とすることで、軽量化を図る。
【０２２８】
こうして、可撓性を有する支持体６０８、可撓性を有する転写体６１０によって挟まれたフレキシブルな発光装置を得ることができる。なお、支持体６０８と転写体６１０とを同一材料にすると、熱膨張係数が等しくなるので、温度変化による応力歪みの影響を受けにくくすることができる。
【０２２９】
そして、必要があれば、可撓性を有する支持体６０８、可撓性を有する転写体６１０を所望の形状に分断する。そして、公知の技術を用いてＦＰＣ（図示しない）を貼りつけた。
【０２３０】
［実施例７］
実施例６では、支持体を貼りつけた後、基板を剥離して転写体としてのプラスチック基板を貼りつけた例を示したが、本実施例では、基板を剥離した後、第１の転写体としてのプラスチック基板と、第２の転写体としてのプラスチック基板を貼りつけてＥＬ素子を備えた発光装置を作製する例である。説明には図１４を用いる。
【０２３１】
図１４（Ａ）において、７００は基板、７０１は窒化物層または金属層、７０２は酸化物層、７０３は下地絶縁層、７０４ａは駆動回路７１１の素子、７０４ｂ、７０４ｃは画素部７１２の素子、７０５はＥＬ素子（Organic Light Emitting Device）である。ここで素子とは、アクティブマトリクス型の発光装置ならば画素のスイッチング素子として用いる半導体素子（典型的にはＴＦＴ）もしくはＭＩＭ素子並びにＥＬ素子等を指す。そして、これらの素子を覆って、層間絶縁膜７０６を形成する。層間絶縁膜７０６は、成膜後の表面がより平坦であることが好ましい。なお、層間絶縁膜７０６は必ずしも設ける必要はない。
【０２３２】
なお、基板７００上に設ける７０１〜７０３は実施の形態２乃至４のいずれか一に従って形成すればよい。
【０２３３】
これらの素子（７０４ａ、７０４ｂ、７０４ｃを含む）は、上記実施例１のｎチャネル型ＴＦＴ２０１、上記実施例１のｐチャネル型ＴＦＴ２０２に従って作製すればよい。
【０２３４】
上記方法により、図１４（Ａ）の状態を得たら、窒化物層または金属層７０１が設けられている基板７００を物理的手段により引き剥がす。（図１４（Ｂ））酸化物層７０２の膜応力と、窒化物層または金属層７０１の膜応力が異なっているため、比較的小さな力で引き剥がすことができる。
【０２３５】
次いで、エポキシ樹脂などの接着層７０９により転写体（第１の転写体）７１０に貼り付ける。本実施例では、転写体７１０をプラスチックフィルム基板とすることで、軽量化を図る。
【０２３６】
次いで、接着層７０７により基材（第２の転写体）７０８を貼り合わせる。（図１４（Ｃ））本実施例では基材７０８としてプラスチック基板を用いる。具体的には、転写体７１０及び基材７０８として、厚さ１０μｍ以上の樹脂基板、例えばＰＥＳ（ポリエチレンサルファイル）、ＰＣ（ポリカーボネート）、ＰＥＴ（ポリエチレンテレフタレート）もしくはＰＥＮ（ポリエチレンナフタレート）を用いることができる。なお、ＥＬ素子から見て観測者側（発光装置の使用者側）に位置する場合、基材７０８および接着層７０７は、光を透過する材料であることが必要である。
【０２３７】
こうして、可撓性を有する基材７０８、可撓性を有する転写体７１０によって挟まれたフレキシブルな発光装置を得ることができる。なお、基材７０８と転写体７１０とを同一材料にすると、熱膨張係数が等しくなるので、温度変化による応力歪みの影響を受けにくくすることができる。
【０２３８】
そして、必要があれば、可撓性を有する基材７０８、可撓性を有する転写体７１０を所望の形状に分断する。そして、公知の技術を用いてＦＰＣ（図示しない）を貼りつけた。
【０２３９】
［実施例８］
実施例６または実施例７では、可撓性を有する基板によって挟まれたフレキシブルな発光装置を得る例を示したが、プラスチックからなる基板は、一般的に水分や酸素を透過しやすく、有機発光層はこれらのものによって劣化が促進されるので、発光装置の寿命が短くなりやすい。
【０２４０】
そこで本実施例では、プラスチック基板上に、酸素や水分がＥＬ素子の有機発光層に入り込むのを防ぐ複数の膜（以下、バリア膜）と、前記バリア膜どうしの間に前記バリア膜よりも応力の小さい層（応力緩和膜）を設ける。本明細書では、バリア膜と応力緩和膜を積層した膜を封止膜と呼ぶ。
【０２４１】
具体的には、無機物からなるバリア膜（以下、バリア膜と呼ぶ）を２層以上設けて、さらに該２層のバリア膜の間に樹脂を有する応力緩和膜（以下、応力緩和膜と呼ぶ）を設ける。そして、該３層以上の絶縁膜上にＥＬ素子を形成して密封することにより、発光装置を形成する。なお、実施例６または実施例７とは基板以外の構成は同一であるのでここでは省略する。
【０２４２】
図１５に示すように、フィルム基板８１０上にバリア膜を２層以上設けて、さらに該２層のバリア膜の間に応力緩和膜を設ける。その結果、フィルム基板８１０と第２接着層８０９の間に、該バリア膜と応力緩和膜を積層した封止膜が形成される。
【０２４３】
ここでは、フィルム基板８１０上にバリア膜８１１ａとして、窒化珪素からなる膜をスパッタを用いて成膜し、バリア膜８１１ａ上にポリイミドを有する応力緩和膜８１１ｂを成膜し、応力緩和膜８１１ｂ上にバリア膜８１１ｃとして、窒化珪素からなる膜をスパッタを用いて成膜する。バリア膜８１１ａ、応力緩和膜８１１ｂ、バリア膜８１１ｃを積層した膜を封止膜８１１と総称する。そして、該封止膜８１１が形成されたフィルム基板８１０を、第２接着層８０９を用いて、素子を含む被剥離層に貼り合わせればよい。
【０２４４】
同様に、フィルム基板８１２上にバリア膜８１４ａとして、窒化珪素からなる膜をスパッタを用いて成膜し、バリア膜８１４ａ上にポリイミドを有する応力緩和膜８１４ｂを成膜し、応力緩和膜８１４ｂ上にバリア膜８１４ｃとして、窒化珪素からなる膜をスパッタを用いて成膜する。バリア膜８１４ａ、応力緩和膜８１４ｂ、バリア膜８１４ｃを積層した膜を封止膜８１４と総称する。そして、該封止膜８１４が形成されたフィルム基板８１２を、第２接着層８０９を用いて、素子を含む被剥離層に貼り合わせればよい。
【０２４５】
なお、バリア膜は２層以上設けていれば良い。そしてバリア膜は、窒化珪素、窒化酸化珪素、酸化アルミニウム、窒化アルミニウム、窒化酸化アルミニウムまたは窒化酸化珪化アルミニウム（ＡｌＳｉＯＮ）を用いることができる。
【０２４６】
窒化酸化珪化アルミニウムは熱伝導度が比較的高いので、バリア膜に用いることで、素子で発生した熱を効率良く放熱することができる。
【０２４７】
また、応力緩和膜には、透光性を有する樹脂を用いることができる。代表的には、ポリイミド、アクリル、ポリアミド、ポリイミドアミド、ベンゾシクロブテンもしくはエポキシ樹脂等を用いることが可能である。なお、上述した以外の樹脂を用いることもできる。ここでは、熱重合するタイプのポリイミドを塗布後、焼成して形成する。
【０２４８】
窒化珪素は、アルゴンを導入し、基板温度を１５０℃に保ち、スパッタ圧力０．４Pa程度で成膜を行う。そしてターゲットとして珪素を用い、アルゴンの他に窒素及び水素を導入して成膜を行った。窒化酸化珪素の場合、アルゴンを導入し、基板温度を１５０℃に保ち、スパッタ圧力０．４Pa程度で成膜を行う。そしてターゲットとして珪素を用い、アルゴンの他に窒素、ニ酸化窒素及び水素を導入して成膜を行った。なおターゲットとして酸化珪素を用いても良い。
【０２４９】
バリア膜の膜厚は５０ｎｍ〜３μｍの範囲であることが望ましい。ここでは、窒化珪素を１μｍの膜厚で成膜した。
【０２５０】
なお、バリア膜の成膜方法はスパッタのみに限定されず、実施者が適宜設定することができる。例えば、ＬＰＣＶＤ法、プラズマＣＶＤ法等を用いて成膜しても良い。
【０２５１】
また、応力緩和膜の膜厚は、２００ｎｍ〜２μｍの範囲であることが望ましい。ここでは、ポリイミドを１μｍの膜厚で成膜した。
【０２５２】
実施例６における支持体６０８または転写体６１０、或いは実施例７における基材７０８または転写体７１０として、本実施例の封止膜が設けられたプラスチック基板を適用することによりＥＬ素子を完全に大気から遮断することができる。これにより酸化による有機発光材料の劣化をほぼ完全に抑制することができ、ＥＬ素子の信頼性を大幅に向上させることができる。
【０２５３】
［実施例９］
実施例６または実施例７により得られたＥＬ素子を有するモジュール、いわゆるＥＬモジュールの構成を図１６の上面図を用いて説明する。実施例７における転写体６１０、または実施例８における転写体７１０がフィルム基板９００に対応する。
【０２５４】
図１６（Ａ）は、ＥＬ素子を有するモジュール、いわゆるＥＬモジュールを示す上面図、図１６（Ｂ）は図１６（Ａ）をＡ−Ａ’で切断した断面図である。可撓性を有するフィルム基板９００（例えば、プラスチック基板等）に、画素部９０２、ソース側駆動回路９０１、及びゲート側駆動回路９０３を形成する。これらの画素部や駆動回路は、上記実施例に従えば得ることができる。また、９１８はシール材、９１９はＤＬＣ膜であり、画素部および駆動回路部はシール材９１８で覆われ、そのシール材は保護膜９１９で覆われている。さらに、接着材を用いてカバー材９２０で封止されている。カバー材９２０の形状および支持体の形状も特に限定されず、平面を有するもの、曲面を有するもの、可曲性を有するもの、フィルム状のものであってもよい。熱や外力などによる変形に耐えるためカバー材９２０はフィルム基板９００と同じ材質のもの、例えばプラスチック基板を用いることが望ましく、図１６に示す凹部形状（深さ３〜１０μｍ）に加工されたものを用いる。さらに加工して乾燥剤９２１が設置できる凹部（深さ５０〜２００μｍ）を形成することが望ましい。また、多面取りでＥＬモジュールを製造する場合、基板とカバー材とを貼り合わせた後、ＣＯ₂レーザー等を用いて端面が一致するように分断してもよい。
【０２５５】
また、ここでは図示しないが、用いる金属層（ここでは陰極など）の反射により背景が映り込むことを防ぐために、位相差板（λ／４板）や偏光板からなる円偏光板と呼ばれる円偏光手段を基板９００上に設けてもよい。
【０２５６】
なお、９０８はソース側駆動回路９０１及びゲート側駆動回路９０３に入力される信号を伝送するための配線であり、外部入力端子となるＦＰＣ（フレキシブルプリントサーキット）９０９からビデオ信号やクロック信号を受け取る。また、本実施例の発光装置は、デジタル駆動であってもよく、アナログ駆動であってもよく、ビデオ信号はデジタル信号であってもよいし、アナログ信号であってもよい。なお、ここではＦＰＣしか図示されていないが、このＦＰＣにはプリント配線基盤（ＰＷＢ）が取り付けられていても良い。本明細書における発光装置には、発光装置本体だけでなく、それにＦＰＣもしくはＰＷＢが取り付けられた状態をも含むものとする。また、これらの画素部や駆動回路と同一基板上に複雑な集積回路（メモリ、ＣＰＵ、コントローラ、Ｄ／Ａコンバータ等）を形成することも可能であるが、少ないマスク数での作製は困難である。従って、メモリ、ＣＰＵ、コントローラ、Ｄ／Ａコンバータ等を備えたＩＣチップを、ＣＯＧ（chip on glass）方式やＴＡＢ（tape automated bonding）方式やワイヤボンディング方法で実装することが好ましい。
【０２５７】
次に、断面構造について図１６（Ｂ）を用いて説明する。フィルム基板９００上に接着層を介して絶縁膜９１０が設けられ、絶縁膜９１０の上方には画素部９０２、ゲート側駆動回路９０３が形成されており、画素部９０２は電流制御用ＴＦＴ９１１とそのドレインに電気的に接続された画素電極９１２を含む複数の画素により形成される。なお、実施の形態１乃至４のいずれか一に従って、基板上に形成した被剥離層を剥離した後、フィルム基板９００が接着層で貼りつけられる。また、ゲート側駆動回路９０３はｎチャネル型ＴＦＴ９１３とｐチャネル型ＴＦＴ９１４とを組み合わせたＣＭＯＳ回路を用いて形成される。
【０２５８】
これらのＴＦＴ（９１１、９１３、９１４を含む）は、上記実施例１のｎチャネル型ＴＦＴ２０１、上記実施例１のｐチャネル型ＴＦＴ２０２に従って作製すればよい。
【０２５９】
なお、ＴＦＴとＥＬ素子の間に設ける絶縁膜としては、アルカリ金属イオンやアルカリ土金属イオン等の不純物イオンの拡散をブロックするだけでなく、積極的にアルカリ金属イオンやアルカリ土金属イオン等の不純物イオンを吸着する材料が好ましく、更には後のプロセス温度に耐えうる材料が適している。これらの条件に合う材料は、一例としてフッ素を多く含んだ窒化シリコン膜が挙げられる。窒化シリコン膜の膜中に含まれるフッ素濃度は、１×１０¹⁹／ｃｍ³以上、好ましくは窒化シリコン膜中でのフッ素の組成比を１〜５％とすればよい。窒化シリコン膜中のフッ素がアルカリ金属イオンやアルカリ土金属イオン等と結合し、膜中に吸着される。また、他の例としてアルカリ金属イオンやアルカリ土金属イオン等を吸着するアンチモン（Ｓｂ）化合物、スズ（Ｓｎ）化合物、またはインジウム（Ｉｎ）化合物からなる微粒子を含む有機樹脂膜、例えば、五酸化アンチモン微粒子（Ｓｂ₂Ｏ₅・ｎＨ₂Ｏ）を含む有機樹脂膜も挙げられる。なお、この有機樹脂膜は、平均粒径１０〜２０ｎｍの微粒子が含まれており、光透過性も非常に高い。この五酸化アンチモン微粒子で代表されるアンチモン化合物は、アルカリ金属イオン等の不純物イオンやアルカリ土金属イオンを吸着しやすい。
【０２６０】
また、ＴＦＴの活性層とＥＬ素子との間に設ける絶縁膜の他の材料としては、ＡｌＮ_XＯ_Yで示される層を用いてもよい。スパッタ法を用い、例えば、窒化アルミニウム（ＡｌＮ）ターゲットを用い、アルゴンガスと窒素ガスと酸素ガスを混合した雰囲気下にて成膜して得られるアルミニウムを含む窒化酸化物層（ＡｌＮ_XＯ_Yで示される層）は、窒素を２．５atm％〜４７．５atm％含む膜であり、水分や酸素をブロッキングすることができる効果に加え、熱伝導性が高く放熱効果を有し、さらには透光性が非常に高いという特徴を有している。加えて、アルカリ金属やアルカリ土類金属などの不純物がＴＦＴの活性層に入り込むのを防ぐことができる。
【０２６１】
特にＲＦスパッタ装置を用い、シリコンターゲットを用いて形成される窒化シリコン膜は、有機樹脂膜からなる層間絶縁膜のパッシベーション膜として適している。窒化シリコン膜は、有機樹脂膜の脱ガスを抑えることができ、さらに水分や酸素のブロッキングもできるため、有機化合物層のシュリンクとよばれる不良発生を抑えることができる。
【０２６２】
画素電極９１２はＥＬ素子の陽極として機能する。また、画素電極９１２の両端にはバンク９１５が形成され、画素電極９１２上にはＥＬ層９１６および発光素子の陰極９１７が形成される。バンク９１５としては無機絶縁膜または有機絶縁膜をパターニングすることによって得ることができ、カバレッジを良好なものとするため、バンク９１５の上端部または下端部に曲率を有する曲面が形成されるようにすることが好ましい。例えば、バンク９１５の材料としてポジ型の感光性アクリルを用いた場合、バンク９１５の上端部のみに曲率半径（０．２μｍ〜３μｍ）を有する曲面を持たせることが好ましい。また、バンク９１５として、感光性の光によってエッチャントに不溶解性となるネガ型、或いは光によってエッチャントに溶解性となるポジ型のいずれも使用することができる。
【０２６３】
ＥＬ層９１６としては、発光層、電荷輸送層または電荷注入層を自由に組み合わせてＥＬ層（発光及びそのためのキャリアの移動を行わせるための層）を形成すれば良い。例えば、低分子系有機ＥＬ材料や高分子系有機ＥＬ材料を用いればよい。また、ＥＬ層として一重項励起により発光（蛍光）する発光材料（シングレット化合物）からなる薄膜、または三重項励起により発光（リン光）する発光材料（トリプレット化合物）からなる薄膜を用いることができる。また、電荷輸送層や電荷注入層として炭化珪素等の無機材料を用いることも可能である。これらの有機ＥＬ材料や無機材料は公知の材料を用いることができる。
【０２６４】
陰極９１７は全画素に共通の配線としても機能し、接続配線９０８を経由してＦＰＣ９０９に電気的に接続されている。さらに、画素部９０２及びゲート側駆動回路９０３に含まれる素子は全て陰極９１７、シール材９１８、及び保護膜９１９で覆われている。
【０２６５】
なお、シール材９１８としては、できるだけ可視光に対して透明もしくは半透明な材料を用いるのが好ましい。また、シール材９１８はできるだけ水分や酸素を透過しない材料であることが望ましい。
【０２６６】
また、シール材９１８を用いて発光素子を完全に覆った後、すくなくとも図１６に示すようにＤＬＣ膜等からなる保護膜９１９をシール材９１８の表面（露呈面）に設けることが好ましい。また、基板の裏面を含む全面に保護膜を設けてもよい。ここで、外部入力端子（ＦＰＣ）が設けられる部分に保護膜が成膜されないように注意することが必要である。マスクを用いて保護膜が成膜されないようにしてもよいし、ＣＶＤ装置で用いるマスキングテープ等のテープで外部入力端子部分を覆うことで保護膜が成膜されないようにしてもよい。
【０２６７】
以上のような構造で発光素子をシール材９１８及び保護膜で封入することにより、発光素子を外部から完全に遮断することができ、外部から水分や酸素等のＥＬ層の酸化による劣化を促す物質が侵入することを防ぐことができる。加えて、保護膜として熱伝導性を有する膜（ＡｌＯＮ膜、ＡｌＮ膜など）を用いれば駆動させたときに生じる発熱を発散することができる。従って、信頼性の高い発光装置を得ることができる。
【０２６８】
また、画素電極を陰極とし、ＥＬ層と陽極を積層して図１６とは逆方向に発光する構成としてもよい。図１７にその一例を示す。なお、上面図は同一であるので省略する。
【０２６９】
図１７に示した断面構造について以下に説明する。フィルム基板１０００としては、プラスチック基板を用いる。なお、実施の形態１乃至４のいずれか一に従って、基板上に形成した被剥離層を剥離した後、フィルム基板１０００が接着層で貼りつけられる。フィルム基板１０００上に絶縁膜１０１０が設けられ、絶縁膜１０１０の上方には画素部１００２、ゲート側駆動回路１００３が形成されており、画素部１００２は電流制御用ＴＦＴ１０１１とそのドレインに電気的に接続された画素電極１０１２を含む複数の画素により形成される。また、ゲート側駆動回路１００３はｎチャネル型ＴＦＴ１０１３とｐチャネル型ＴＦＴ１０１４とを組み合わせたＣＭＯＳ回路を用いて形成される。
【０２７０】
画素電極１０１２は発光素子の陰極として機能する。また、画素電極１０１２の両端にはバンク１０１５が形成され、画素電極１０１２上にはＥＬ層１０１６および発光素子の陽極１０１７が形成される。
【０２７１】
陽極１０１７は全画素に共通の配線としても機能し、接続配線１００８を経由してＦＰＣ１００９に電気的に接続されている。さらに、画素部１００２及びゲート側駆動回路１００３に含まれる素子は全て陽極１０１７、シール材１０１８、及びＤＬＣ等からなる保護膜１０１９で覆われている。また、カバー材１０２１と基板１０００とを接着剤で貼り合わせた。また、カバー材には凹部を設け、乾燥剤１０２１を設置する。
【０２７２】
なお、シール材１０１８としては、できるだけ可視光に対して透明もしくは半透明な材料を用いるのが好ましい。また、シール材１０１８はできるだけ水分や酸素を透過しない材料であることが望ましい。
【０２７３】
また、図１７では、画素電極を陰極とし、ＥＬ層と陽極を積層したため、発光方向は図１７に示す矢印の方向となっている。
【０２７４】
また、ここでは図示しないが、用いる金属層（ここでは陰極となる画素電極など）の反射により背景が映り込むことを防ぐために、位相差板（λ／４板）や偏光板からなる円偏光板と呼ばれる円偏光手段をカバー材１０２０上に設けてもよい。
【０２７５】
本実施例では、実施例１で得られる電気特性、信頼性ともに高いＴＦＴを用いるため、従来の素子に比べて信頼性の高い発光素子を形成することができる。また、そのような発光素子を有する発光装置を表示部として用いることにより高性能な電気器具を得ることができる。
【０２７６】
なお、本実施例は実施例１、実施例７、実施例８、または実施例９と自由に組み合わせることが可能である。
【０２７７】
［実施例１０］
本発明を実施して様々なモジュール（アクティブマトリクス型液晶モジュール、パッシブ型液晶モジュール、アクティブマトリクス型ＥＬモジュール、パッシブ型ＥＬモジュール、アクティブマトリクス型ＥＣモジュール）を完成させることができる。即ち、本発明を実施することによって、それらを組み込んだ全ての電子機器が完成される。
【０２７８】
その様な電子機器としては、ビデオカメラ、デジタルカメラ、ヘッドマウントディスプレイ（ゴーグル型ディスプレイ）、カーナビゲーション、プロジェクタ、カーステレオ、パーソナルコンピュータ、携帯情報端末（モバイルコンピュータ、携帯電話または電子書籍等）などが挙げられる。それらの一例を図１８、図１９に示す。
【０２７９】
図１８（Ａ）はパーソナルコンピュータであり、本体２００１、画像入力部２００２、表示部２００３、キーボード２００４等を含む。
【０２８０】
図１８（Ｂ）はビデオカメラであり、本体２１０１、表示部２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６等を含む。
【０２８１】
図１８（Ｃ）はモバイルコンピュータ（モービルコンピュータ）であり、本体２２０１、カメラ部２２０２、受像部２２０３、操作スイッチ２２０４、表示部２２０５等を含む。
【０２８２】
図１８（Ｄ）はプログラムを記録した記録媒体（以下、記録媒体と呼ぶ）を用いるプレーヤーであり、本体２４０１、表示部２４０２、スピーカ部２４０３、記録媒体２４０４、操作スイッチ２４０５等を含む。なお、このプレーヤーは記録媒体としてＤＶＤ（Ｄｉｇｔｉａｌ Ｖｅｒｓａｔｉｌｅ Ｄｉｓｃ）、ＣＤ等を用い、音楽鑑賞や映画鑑賞やゲームやインターネットを行うことができる。
【０２８３】
図１８（Ｅ）はデジタルカメラであり、本体２５０１、表示部２５０２、接眼部２５０３、操作スイッチ２５０４、受像部（図示しない）等を含む。
【０２８４】
図１９（Ａ）は携帯電話であり、本体２９０１、音声出力部２９０２、音声入力部２９０３、表示部２９０４、操作スイッチ２９０５、アンテナ２９０６、画像入力部（ＣＣＤ、イメージセンサ等）２９０７等を含む。
【０２８５】
図１９（Ｂ）は携帯書籍（電子書籍）であり、本体３００１、表示部３００２、３００３、記憶媒体３００４、操作スイッチ３００５、アンテナ３００６等を含む。
【０２８６】
図１９（Ｃ）はディスプレイであり、本体３１０１、支持台３１０２、表示部３１０３等を含む。
【０２８７】
ちなみに図１９（Ｃ）に示すディスプレイは中小型または大型のもの、例えば５〜２０インチの画面サイズのものである。また、このようなサイズの表示部を形成するためには、基板の一辺が１ｍのものを用い、多面取りを行って量産することが好ましい。
【０２８８】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電子機器の作製方法に適用することが可能である。また、本実施例の電子機器は実施例１〜９のどのような組み合わせからなる構成を用いても実現することができる。
【０２８９】
【発明の効果】
本発明は、物理的手段によって基板から剥離するため、半導体層への損傷なく、素子の信頼性を向上できる。
【０２９０】
また、本発明は、小さな面積を有する被剥離層の剥離だけでなく、大きな面積を有する被剥離層を全面に渡って歩留まりよく剥離することが可能である。
【０２９１】
加えて、本発明は、物理的手段で容易に剥離、例えば人間の手で引き剥がすことが可能であるため、量産に適したプロセスと言える。また、量産する際に被剥離層を引き剥がすための製造装置を作製した場合、大型の製造装置も安価に作製することができる。
【図面の簡単な説明】
【図１】 実施の形態１を説明する図である。
【図２】 実施の形態２を説明する図である。
【図３】 実験を説明する図である。
【図４】 実施の形態３を説明する図である。
【図５】 実施の形態４を説明する図である。
【図６】 アクティブマトリクス基板の作製工程を示す図。
【図７】 アクティブマトリクス基板の作製工程を示す図。
【図８】 アクティブマトリクス基板を示す図。
【図９】 実施例２を説明する図である。
【図１０】 実施例３を説明する図である。
【図１１】 実施例４を説明する図である。
【図１２】 実施例５を説明する図である。
【図１３】 実施例６を説明する図である。
【図１４】 実施例７を説明する図である。
【図１５】 実施例８を説明する図である。
【図１６】 実施例９を説明する図である。
【図１７】 実施例９を説明する図である。
【図１８】 電子機器の一例を示す図。
【図１９】 電子機器の一例を示す図。
【図２０】 部分的に剥離させた境界の断面TEM写真図及び模式図。
【図２１】 剥離した酸化シリコン膜表面のＴＸＲＦ測定結果を示すグラフ。
【図２２】 石英基板上に成膜されたＷ膜表面のＴＸＲＦ測定結果を示すグラフ。（リファレンス）
【図２３】 石英基板表面のＴＸＲＦ測定結果を示すグラフ。（リファレンス）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for peeling a layer to be peeled, and particularly to a method for peeling a layer to be peeled including various elements. In addition, the present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) in which a peeled layer to be peeled is attached to a substrate and transferred, and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal module, a light-emitting device typified by an EL module, and an electronic apparatus in which such a device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.
[0004]
Various applications using such an image display device are expected, but the use for portable devices is attracting attention. Currently, many glass substrates and quartz substrates are used, but they have the disadvantage of being easily broken and heavy. Further, in mass production, it is difficult to increase the size of a glass substrate or a quartz substrate, which is not suitable. Therefore, attempts have been made to form TFT elements on a flexible substrate, typically a flexible plastic film.
[0005]
However, since the heat resistance of the plastic film is low, the maximum temperature of the process has to be lowered, and as a result, TFTs having better electrical characteristics cannot be formed when formed on a glass substrate. Therefore, a high-performance liquid crystal display device or light emitting element using a plastic film has not been realized.
[0006]
Further, a peeling method has already been proposed in which a layer to be peeled existing on a substrate via a separation layer is peeled from the substrate. For example, the techniques described in JP-A-10-125929 and JP-A-10-125931 are provided with a separation layer made of amorphous silicon (or polysilicon) and irradiated with laser light through a substrate. By releasing hydrogen contained in the amorphous silicon, a void is generated to separate the substrate. In addition, Japanese Patent Application Laid-Open No. 10-125930 uses this technique to complete a liquid crystal display device by attaching a peeled layer (referred to as a transferred layer in the publication) to a plastic film.
[0007]
However, in the above method, it is essential to use a substrate with high translucency, which gives a sufficient energy to pass through the substrate and to release hydrogen contained in amorphous silicon. There is a problem that light irradiation is required and damages the peeled layer. In addition, in the above method, when an element is manufactured on the separation layer, if high-temperature heat treatment or the like is performed in the element manufacturing process, hydrogen contained in the separation layer is diffused and reduced, and the separation layer is irradiated with laser light. However, there is a risk that peeling will not be performed sufficiently. Therefore, in order to maintain the amount of hydrogen contained in the separation layer, there is a problem that the process after the formation of the separation layer is limited. In addition, the above publication describes that a light shielding layer or a reflective layer is provided in order to prevent damage to the layer to be peeled, but in that case, it is difficult to manufacture a transmissive liquid crystal display device. In addition, with the above method, it is difficult to peel off a layer to be peeled having a large area.
[0008]
[Problems to be solved by the invention]
The present invention has been made in view of the above-mentioned problems, and the present invention provides a peeling method that does not damage the peeled layer, and not only peels off the peeled layer having a small area, but also provides a large area. It is an object to make it possible to peel the layer to be peeled over the entire surface.
[0009]
Another object of the present invention is to provide a peeling method that does not limit the heat treatment temperature, the type of the substrate, and the like in the formation of the peeled layer.
[0010]
It is another object of the present invention to provide a lightweight semiconductor device and a manufacturing method thereof by attaching a layer to be peeled to various base materials. In particular, a light-weight semiconductor device and a manufacturing method thereof are provided by attaching various elements such as TFT (a thin film diode, a photoelectric conversion element made of a silicon PIN junction or a silicon resistance element) to a flexible film. Is an issue.
[0011]
[Means for Solving the Problems]
The inventors have made a number of experiments and examinations, and provided a nitride layer, preferably a metal nitride layer provided on the substrate, an oxide layer in contact with the metal nitride layer, and an oxide layer. When film formation or heat treatment at 500 ° C. or higher is performed on the film, no process abnormality such as film peeling (peeling) occurs, but physical means, typically mechanical force is applied (for example, human The present inventors have found a peeling method that can be easily separated cleanly in the layer of the oxide layer or at the interface by peeling off by hand).
[0012]
That is, the bonding force between the nitride layer and the oxide layer has a strength that can withstand thermal energy, but the film stress differs between the nitride layer and the oxide layer. Since it has a stress strain between the material layers, it is weak to mechanical energy and is optimal for peeling. The inventors of the present invention refer to a peeling process for peeling using film stress in this way as a stress peel-off process.
[0013]
Note that in this specification, the internal stress of a film (referred to as film stress) means that when an arbitrary cross section is considered inside a film formed on a substrate, one side of the cross section exerts on the other side. This is the force per unit cross-sectional area. It can be said that the internal stress is more or less necessarily present in a thin film formed by vacuum deposition, sputtering, vapor phase growth or the like. The maximum value is 10 ⁹ N / m ² To reach. The internal stress value varies depending on the material of the thin film, the substance of the substrate, the formation conditions of the thin film, and the like. Further, the internal stress value also changes by performing heat treatment.
[0014]
Also, the state in which the force acting on the other party is pulled through the unit cross-sectional area perpendicular to the substrate surface is called the tensile state, the internal stress at that time is called the tensile stress, and the state in the pushing direction is called the compressed state. Internal stress is called compressive stress. In this specification, the tensile stress is positive (+) and the compressive stress is negative (-) as shown in the graphs and tables.
[0015]
Configuration 1 of the invention relating to the peeling method disclosed in the present specification is:
A peeling method for peeling a layer to be peeled from a substrate,
A nitride layer is provided on the substrate, and a layer to be peeled including at least an oxide layer in contact with the nitride layer is formed on the substrate provided with the nitride layer, and then the layer to be peeled is formed. It is a peeling method characterized in that the layer is peeled off from the substrate provided with the nitride layer in the layer of the oxide layer or at the interface by physical means.
[0016]
Further, the support 2 may be peeled after being bonded with an adhesive, and the structure 2 of the invention related to the peeling method disclosed in the present specification is
A peeling method for peeling a layer to be peeled from a substrate,
A nitride layer is provided on the substrate, and a layer to be peeled including at least an oxide layer in contact with the nitride layer is formed on the substrate provided with the nitride layer, and the layer to be peeled is formed After bonding the support to
In the peeling method, the layer to be peeled bonded to the support is peeled off from the substrate provided with the nitride layer in the layer of the oxide layer or at the interface by physical means.
[0017]
Moreover, in the said structure 2, in order to further promote peeling, you may irradiate a heat processing or a laser beam before adhering the said support body. In this case, a material that absorbs laser light may be selected for the nitride layer, and the interface between the nitride layer and the oxide layer may be heated to facilitate peeling. However, when laser light is used, a light-transmitting substrate is used.
[0018]
In each of the above configurations, the nitride layer may be provided with another layer between the substrate and the nitride layer, such as an insulating layer or a metal layer. However, in order to simplify the process, the nitride layer is formed on the substrate. It is preferable to form a nitride layer in contact therewith.
[0019]
Further, instead of the nitride layer, a metal layer, preferably a metal nitride layer may be used, a metal layer provided on the substrate, preferably a metal nitride layer is provided, and an oxide layer is further provided in contact with the metal nitride layer, Even when a film formation process or a heat treatment at 500 ° C. or higher is performed, film separation (peeling) does not occur, and it can be easily separated cleanly within the oxide layer or at the interface by physical means.
[0020]
The configuration 3 of the invention related to the peeling method disclosed in this specification is:
A peeling method for peeling a layer to be peeled from a substrate,
A metal layer is provided on the substrate, and a layer to be peeled including at least an oxide layer in contact with the metal layer is formed on the substrate on which the metal layer is provided. It is a peeling method characterized by peeling from the substrate provided with the metal layer in the layer of the oxide layer or at the interface by physical means.
[0021]
Further, the support 4 may be peeled after being bonded with an adhesive, and the constitution 4 of the invention relating to the peeling method disclosed in the present specification is
A peeling method for peeling a layer to be peeled from a substrate,
A metal layer is provided on the substrate, and a layer to be peeled including at least an oxide layer in contact with the metal layer is formed on the substrate provided with the metal layer, and a support is provided on the layer to be peeled. After gluing
In the peeling method, the layer to be peeled adhered to the support is peeled from the substrate provided with the metal layer in a layer of the oxide layer or at an interface by a physical means.
[0022]
Also in the above-described configuration 4, in order to further promote peeling, heat treatment or laser light irradiation may be performed before bonding the support. In this case, a material that absorbs laser light may be selected for the metal layer, and the interface between the metal layer and the oxide layer may be heated to facilitate peeling. However, when laser light is used, a light-transmitting substrate is used.
[0023]
In this specification, a physical means is a means recognized not by chemistry but by physics, and specifically, a mechanical means or a mechanical means having a process that can be reduced to the laws of mechanics. , Means to change some mechanical energy (mechanical energy).
[0024]
However, in any of the configurations 2 and 4, it is necessary to make the bonding force between the oxide layer and the metal layer smaller than the bonding strength with the support when peeling off by physical means. is there.
[0025]
In the configuration 3 or the configuration 4, the metal layer includes Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, It is characterized by being a single layer made of an element selected from Ir and Pt, an alloy material or a compound material containing the element as a main component, or a laminate of these metals or mixtures.
[0026]
In the configuration 3 or the configuration 4, the metal layer may be provided with another layer such as an insulating layer between the substrate and the metal layer. However, in order to simplify the process, the metal layer is in contact with the substrate. It is preferable to form a metal layer.
[0027]
In the present invention, not only a light-transmitting substrate but any substrate, for example, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a metal substrate can be used, and a layer to be peeled provided on the substrate Can be peeled off.
[0028]
In each of the above structures, the oxide layer is a single layer made of a silicon oxide material or a metal oxide material, or a laminate thereof.
[0029]
In each of the above structures, in order to further promote peeling, heat treatment or laser light irradiation may be performed before peeling by the physical means.
[0030]
In addition, a semiconductor device can be manufactured by attaching (transferring) a layer to be peeled provided on a substrate to a transfer body by using the peeling method of the present invention, and the invention relates to a method for manufacturing a semiconductor device. The configuration of
Forming a nitride layer on the substrate;
Forming an oxide layer on the nitride layer;
Forming an insulating layer on the oxide layer;
Forming an element on the insulating layer;
After bonding the support to the element, peeling the support from the substrate by physical means in the layer of the oxide layer or at the interface;
A method for manufacturing a semiconductor device, comprising: attaching a transfer body to the insulating layer or the oxide layer, and sandwiching the element between the support and the transfer body.
[0031]
In the above structure, in order to further promote peeling, heat treatment or laser light irradiation may be performed before the support is bonded. In this case, a material that absorbs laser light may be selected for the nitride layer, and the interface between the nitride and the oxide layer may be heated to facilitate peeling. However, when laser light is used, a light-transmitting substrate is used.
[0032]
In addition, in order to facilitate separation, a granular oxide may be provided over the nitride layer, and an oxide layer covering the granular oxide may be provided to facilitate separation. Is
Forming a nitride layer on the substrate;
Forming a granular oxide on the nitride layer;
Forming an oxide layer covering the oxide;
Forming an insulating layer on the oxide layer;
Forming an element on the insulating layer;
After bonding the support to the element, peeling the support from the substrate by physical means in the layer of the oxide layer or at the interface;
A method for manufacturing a semiconductor device, comprising: attaching a transfer body to the insulating layer or the oxide layer, and sandwiching the element between the support and the transfer body.
[0033]
Further, the configuration of the invention relating to another method for manufacturing a semiconductor device is as follows:
Forming a layer containing a metal material on a substrate;
Forming an oxide layer on the layer containing the metal material;
Forming an insulating layer on the oxide layer;
Forming an element on the insulating layer;
After bonding the support to the element, peeling the support from the substrate by physical means in the layer of the oxide layer or at the interface;
A method for manufacturing a semiconductor device, comprising: attaching a transfer body to the insulating layer or the oxide layer, and sandwiching the element between the support and the transfer body.
[0034]
In the above structure, in order to further promote peeling, heat treatment or laser light irradiation may be performed before the support is bonded. In this case, a material that absorbs laser light may be selected for the metal layer, and the interface between the metal layer and the oxide layer may be heated to facilitate peeling. However, when laser light is used, a light-transmitting substrate is used.
[0035]
In addition, in order to promote separation, a granular oxide may be provided over a layer containing a metal material, and an oxide layer may be provided to cover the granular oxide. The composition of the invention is:
Forming a layer containing a metal material on a substrate;
Forming a granular oxide on the layer containing the metal material;
Forming an oxide layer covering the oxide;
Forming an insulating layer on the oxide layer;
Forming an element on the insulating layer;
After bonding the support to the element, peeling the support from the substrate by physical means in the layer of the oxide layer or at the interface;
A method for manufacturing a semiconductor device, comprising: attaching a transfer body to the insulating layer or the oxide layer, and sandwiching the element between the support and the transfer body.
[0036]
In the above structure, the layer containing the metal material is preferably a nitride, and the metal material includes Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, It is an element selected from Zn, Ru, Rh, Pd, Os, Ir, Pt, or a single layer made of an alloy material or a compound material containing the element as a main component, or a laminate of these metals or mixtures. It is said.
[0037]
In addition, it is also possible to fabricate a semiconductor device by peeling the layer to be peeled provided on the substrate by using the peeling method of the present invention and then attaching it to the first transfer body or the second transfer body. The structure of the invention related to the method for manufacturing a semiconductor device
Forming a layer containing a metal material on a substrate;
Forming an oxide layer on the layer containing the metal material;
Forming an insulating layer on the oxide layer;
Forming an element on the insulating layer;
Peeling from the substrate by physical means in the layer of the oxide layer or at the interface;
Adhering a first transfer body to the insulating layer or oxide layer;
A method for manufacturing a semiconductor device, comprising: adhering a second transfer member to the element and sandwiching the element between the first transfer member and the second transfer member.
[0038]
In the above structure, the layer containing the metal material is preferably a nitride, and the metal material includes Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, It is an element selected from Zn, Ru, Rh, Pd, Os, Ir, Pt, or a single layer made of an alloy material or a compound material containing the element as a main component, or a laminate of these metals or mixtures. It is said.
[0039]
Further, the configuration of the invention relating to another method for manufacturing a semiconductor device is as follows:
Forming a nitride layer on the substrate;
Forming an oxide layer on the nitride layer;
Forming an insulating layer on the oxide layer;
Forming an element on the insulating layer;
Peeling from the substrate by physical means in the layer of the oxide layer or at the interface;
Adhering a first transfer body to the insulating layer or oxide layer;
A method for manufacturing a semiconductor device, comprising: adhering a second transfer member to the element and sandwiching the element between the first transfer member and the second transfer member.
[0040]
In each of the above structures related to the method for manufacturing the semiconductor device, the oxide layer is a single layer made of a silicon oxide material or a metal oxide material, or a stacked layer thereof.
[0041]
In each of the above structures related to the method for manufacturing a semiconductor device, a heat treatment or a laser light irradiation treatment may be performed before peeling by the physical means in order to further promote peeling.
[0042]
Further, in each of the above structures related to the method for manufacturing a semiconductor device, the element is a thin film transistor having a semiconductor layer as an active layer, and the step of forming the semiconductor layer includes heat treatment of a semiconductor layer having an amorphous structure or The semiconductor layer is characterized by being crystallized by treatment with laser light irradiation to form a semiconductor layer having a crystal structure.
[0043]
Note that in this specification, the transfer body is to be bonded to the layer to be peeled after being peeled, and is not particularly limited, and may be a base material having any composition such as plastic, glass, metal, ceramics and the like. Further, in the present specification, the support is for adhering to the layer to be peeled when peeling by physical means, and is not particularly limited, and any composition such as plastic, glass, metal, ceramics, etc. A substrate may be used. Further, the shape of the transfer body and the shape of the support are not particularly limited, and may be a flat surface, a curved surface, a bendable shape, or a film shape. If weight reduction is the top priority, a film-like plastic substrate such as polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetherether Plastic substrates such as ketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), and polyimide are preferable.
[0044]
In each of the above structures related to the method for manufacturing the semiconductor device, when a liquid crystal display device is manufactured, the support body may be bonded to the layer to be peeled using the support body as a counter substrate and a sealant as an adhesive material. In this case, the element provided in the peeling layer has a pixel electrode, and a liquid crystal material is filled between the pixel electrode and the counter substrate.
[0045]
In each of the above structures related to the method for manufacturing a semiconductor device, when a light-emitting device typified by a light-emitting device having an EL element is manufactured, an organic compound layer such as moisture or oxygen is externally used as a support. It is preferable to completely block the light emitting element from the outside so as to prevent a substance that promotes deterioration from entering. Further, if weight reduction is the top priority, a film-like plastic substrate is preferable. However, since the effect of preventing the entry of substances that promote deterioration of the organic compound layer such as moisture and oxygen from the outside is weak, for example, a support If the first insulating film, the second insulating film, and the third insulating film are provided on the top to sufficiently prevent a substance that promotes deterioration of the organic compound layer such as moisture and oxygen from entering from the outside. Good. However, the second insulating film (stress relieving film) sandwiched between the first insulating film (barrier film) and the third insulating film (barrier film) includes the first insulating film and the first insulating film. The film stress is made smaller than that of the third insulating film.
[0046]
In the case of manufacturing a light-emitting device typified by a light-emitting device having an EL element, not only the support but also the transfer body similarly includes the first insulating film, the second insulating film, and the third insulating film. It is preferable to prevent the invasion of substances that promote the deterioration of the organic compound layer such as moisture and oxygen from the outside.
[0047]
(Experiment 1)
Here, an oxide layer was provided in contact with the nitride layer or the metal layer, and the following experiment was performed in order to confirm whether the layer to be peeled provided on the oxide layer could be peeled from the substrate.
[0048]
First, a stack as shown in FIG. 3A is formed over a substrate.
[0049]
As the substrate 30, a glass substrate (# 1737) was used. Further, an aluminum-silicon alloy layer 31 having a thickness of 300 nm was formed on the substrate 30 by sputtering. Next, a titanium nitride layer 32 having a thickness of 100 nm was formed on the aluminum-silicon alloy layer 31 by sputtering.
[0050]
Next, a silicon oxide layer 33 was formed to a thickness of 200 nm by sputtering. The silicon oxide layer 33 is formed by using an RF sputtering apparatus, a silicon oxide target (diameter: 30.5 cm), a substrate temperature of 150 ° C., a deposition pressure of 0.4 Pa, a deposition power of 3 kW, an argon flow rate / The oxygen flow rate was set to 35 sccm / 15 sccm.
[0051]
Next, a base insulating layer is formed on the silicon oxide layer 33 by plasma CVD. As a base insulating layer, a film formation temperature of 300 ° C. by a plasma CVD method, a source gas SiH _Four , NH _Three , N ₂ A silicon oxynitride film 34a made of O (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) was formed to a thickness of 50 nm. Next, after cleaning the surface with ozone water, the oxide film on the surface is removed with dilute hydrofluoric acid (1/100 dilution). Next, a film formation temperature of 300 ° C. and a source gas SiH by plasma CVD _Four , N ₂ A silicon oxynitride film 34b made of O (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is laminated to a thickness of 100 nm, and further plasma is released without being released to the atmosphere. Deposition temperature 300 ° C by CVD method, deposition gas SiH _Four A semiconductor layer having an amorphous structure (here, an amorphous silicon layer 35) was formed to a thickness of 54 nm. (Fig. 3 (A)
[0052]
Next, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization to form a semiconductor film having a crystal structure (here, the polysilicon layer 36). Here, after the heat treatment for dehydrogenation (500 ° C., 1 hour), the heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. . Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.
[0053]
Next, an epoxy resin was used as the adhesive layer 37, and a film substrate 38 (here, polyethylene terephthalate (PET)) was attached to the polysilicon layer 36. (Figure 3 (C))
[0054]
After obtaining the state of FIG. 3C, the film substrate 38 and the substrate 30 were pulled by a human hand so as to be separated. It was confirmed that at least the titanium nitride and the aluminum-silicon alloy layer remained on the peeled substrate 30. From this experiment, it is expected that peeling occurs in the layer of silicon oxide 33 or at the interface.
[0055]
In this manner, an oxide layer is provided in contact with a nitride layer or a metal layer, and the layer to be peeled is peeled off from the substrate 30 by peeling off the layer to be peeled over the oxide layer. it can.
[0056]
(Experiment 2)
In order to identify where the peeling was performed, an experiment was conducted in which the peeling was performed partially by the peeling method of the present invention and the cross section near the boundary was examined.
[0057]
A glass substrate (# 1737) was used as the substrate. Further, a titanium nitride layer having a thickness of 100 nm was formed on the substrate by sputtering.
[0058]
Next, a silicon oxide layer having a thickness of 200 nm was formed by sputtering. The silicon oxide layer was formed using an RF sputtering apparatus, a silicon oxide target (diameter: 30.5 cm), a substrate temperature of 150 ° C., a deposition pressure of 0.4 Pa, a deposition power of 3 kW, and an argon flow rate / oxygen. The flow rate was 35 sccm / 15 sccm.
[0059]
Next, a base insulating layer is formed over the silicon oxide layer by a plasma CVD method. As a base insulating layer, a film formation temperature of 300 ° C. by a plasma CVD method, a source gas SiH _Four , NH _Three , N ₂ A silicon oxynitride film made of O (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) was formed to a thickness of 50 nm. Next, after cleaning the surface with ozone water, the oxide film on the surface is removed with dilute hydrofluoric acid (1/100 dilution). Next, a film formation temperature of 300 ° C. and a source gas SiH by plasma CVD method _Four , N ₂ A silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) formed from O is laminated to a thickness of 100 nm, and further plasma CVD without releasing to the atmosphere Film forming temperature 300 ° C., film forming gas SiH _Four A semiconductor layer having an amorphous structure (here, an amorphous silicon layer) was formed to a thickness of 54 nm.
[0060]
Next, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization, so that a semiconductor film having a crystal structure (here, a polysilicon layer) is formed. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) was performed to obtain a silicon film having a crystal structure.
[0061]
Next, the adhesive tape was attached to a part of the polysilicon layer, and pulled by a human hand so that the adhesive tape and the substrate were separated. As a result, only the part where the adhesive tape was applied was peeled off and transferred to the tape. A TEM photograph at the peeling boundary on the substrate side is shown in FIG. 20 (A), and a schematic diagram thereof is shown in FIG. 20 (B).
[0062]
As shown in FIG. 20, the titanium nitride layer remains on the entire surface of the glass substrate, and the portion transferred by applying the tape is transferred cleanly and laminated (SiO 2 by sputtering). ₂ The films, insulating films (1) and (2), polysilicon film) by the PCVD method are gone. From these facts, titanium nitride layer and SiO by sputtering ₂ It can be seen that peeling occurs at the interface with the film.
[0063]
(Experiment 3)
Here, when the material of the nitride layer or the metal layer is TiN, W, or WN, an oxide layer (silicon oxide: film thickness: 200 nm) is provided in contact with the nitride layer or the metal layer, and provided on the oxide layer. In order to confirm whether the peeled layer can be peeled from the substrate, the following experiment was conducted.
[0064]
As sample 1, a TiN film having a thickness of 100 nm was formed on a glass substrate by sputtering, and then a silicon oxide film having a thickness of 200 nm was formed by sputtering. After the formation of the silicon oxide film, lamination and crystallization were performed as in Experiment 1.
[0065]
As sample 2, W was formed with a thickness of 50 nm on a glass substrate by sputtering, and then a silicon oxide film with a thickness of 200 nm was formed by sputtering. After the formation of the silicon oxide film, lamination and crystallization were performed as in Experiment 1.
[0066]
As Sample 3, a WN film having a thickness of 50 nm was formed on a glass substrate by sputtering, and then a silicon oxide film having a thickness of 200 nm was formed by sputtering. After the formation of the silicon oxide film, lamination and crystallization were performed as in Experiment 1.
[0067]
Samples 1 to 3 were formed in this way, and an experiment was conducted to determine whether or not the adhesive tape was adhered to the layer to be peeled off. The results are shown in Table 1.
[0068]
[Table 1]

[0069]
Further, the internal stress before and after the heat treatment (550 ° C., 4 hours) was measured for each of the silicon oxide film, the TiN film, and the W film. The results are shown in Table 2.
[0070]
[Table 2]

[0071]
Note that the silicon oxide film was measured by sputtering on a silicon substrate to a thickness of 400 nm, and the TiN film and W film were formed by sputtering on a glass substrate to a thickness of 400 nm. After film formation, the internal stress was measured, and then a silicon oxide film was laminated as a cap film. After heat treatment, the cap film was removed by etching, and the internal stress was measured again. Two samples were prepared for each measurement.
[0072]
In the W film, the compressive stress (about −7 × 10 ⁹ (Dyne / cm ² )), But the tensile stress (about 8 × 10 ⁹ ~ 9x10 ⁹ (Dyne / cm ² )) And the peeled state was good. With respect to the TiN film, the stress hardly changed before and after the heat treatment, and the tensile stress (about 3.9 × 10 ⁹ ~ 4.5 × 10 ⁹ (Dyne / cm ² )). In addition, with respect to the silicon oxide film, the stress hardly changes before and after the heat treatment, and the compressive stress (about −9.4 × 10 ⁸ ~ -1.3 × 10 ⁹ (Dyne / cm ² )).
[0073]
From these results, the peeling phenomenon is related to the adhesion due to various factors, but particularly has a deep relationship with the internal stress, and when the oxide layer is formed on the nitride layer or the metal layer, the nitride layer or It can be seen that the layer to be peeled can be peeled over the entire surface from the interface between the metal layer and the oxide layer.
[0074]
(Experiment 4)
In order to examine the dependency of the heating temperature, the following experiment was conducted.
[0075]
As a sample, a sputtering method was used to form a W film (tungsten film) with a film thickness of 50 nm on a glass substrate, and then a sputtering method (using a silicon target, an argon gas flow rate of 10 sccm, an oxygen gas flow rate of 30 sccm, and a deposition pressure of 0 (4 Pa, sputtering power 3 kW, substrate temperature 300 ° C.), a silicon oxide film having a thickness of 200 nm was formed. Next, as in Experiment 1, a base insulating layer (silicon oxynitride film 50 nm and silicon oxynitride film 100 nm) and an amorphous silicon film are formed to a thickness of 54 nm by plasma CVD.
[0076]
Next, after performing heat treatment by changing the heating temperature conditions, the quartz substrate is attached to the surface of the amorphous silicon film (or polysilicon film) using an adhesive, and the quartz substrate and the glass substrate are bonded by a human hand. It was pulled so that it could be separated, and it was examined whether it could be peeled off. Condition 1 of heating temperature is 500 ° C., 1 hour, Condition 2 is 450 ° C., 1 hour, Condition 3 is 425 ° C., 1 hour, Condition 4 is 410 ° C., 1 hour, Condition 5 is 400 ° C., 1 hour, Condition 6 was 350 ° C. for 1 hour.
[0077]
As a result of the experiment, the samples of conditions 1 to 4 could be peeled, but the samples of conditions 5 and 6 could not be peeled. Therefore, in the peeling method of the present invention, it is preferable to perform heat treatment at least at 410 ° C. or higher. The temperature of 410 ° C. or higher is a temperature at which hydrogen is released from the film or diffuses into the film.
[0078]
Further, when peeled, the W film remains on the entire surface of the glass substrate, and is laminated on the quartz substrate (SiO 2 by sputtering). ₂ The film, the insulating films (1) and (2) by the PCVD method, and the amorphous silicon film) are transferred. Transferred SiO ₂ The result of measuring the film surface with TXRF is shown in FIG. 21, and when measured with AFM, the surface roughness Rz (30 points) was 5.44 nm. Further, FIG. 22 shows the result of measuring the surface of a 50 nm W film formed on a quartz substrate as a reference by TXRF. When measured by AFM, the surface roughness Rz (30 points) was 22.8 nm. FIG. 23 shows the result of measuring only the quartz substrate by TXRF. 21 and 22 have the same W (tungsten) peak, the transferred SiO ₂ It can be seen that a minute metal material (here, W) is adhered to the film surface.
[0079]
The configuration of the present invention disclosed in this specification is as follows.
The layer to be peeled bonded to the support with an adhesive has a silicon oxide film, and is a semiconductor device having a small amount of metal material between the silicon oxide film and the adhesive.
[0080]
In the above configuration, the metal material is selected from W, Ti, Al, Ta, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt. It is an element or an alloy material or a compound material containing the element as a main component.
[0081]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0082]
(Embodiment 1)
A typical peeling procedure using the present invention will be briefly described with reference to FIG.
[0083]
In FIG. 1A, 10 is a substrate, 11 is a nitride layer or metal layer, 12 is an oxide layer, and 13 is a layer to be peeled.
[0084]
In FIG. 1A, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 10. Further, a silicon substrate, a metal substrate, or a stainless steel substrate may be used.
[0085]
First, as shown in FIG. 1A, a nitride layer or a metal layer 11 is formed on a substrate 10. Typical examples of the nitride layer or the metal layer 11 include Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, A single layer made of an element selected from Pt, or an alloy material or a compound material containing the element as a main component, or a laminate thereof, or a nitride thereof, for example, titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride A single layer made of or a laminate of these may be used.
[0086]
Next, an oxide layer 12 is formed on the nitride layer or metal layer 11. As a typical example of the oxide layer 12, silicon oxide, silicon oxynitride, or a metal oxide material may be used. Note that the oxide layer 12 may be formed by any film formation method such as sputtering, plasma CVD, or coating.
[0087]
In the present invention, it is important to make the film stress of the oxide layer 12 different from the film stress of the nitride layer or the metal layer 11. Each film thickness may be appropriately set within a range of 1 nm to 1000 nm, and each film stress may be adjusted. 1 shows an example in which the nitride layer or the metal layer 11 is formed in contact with the substrate 10 in order to simplify the process. However, an insulation between the substrate 10 and the nitride layer or the metal layer 11 is shown. A layer or a metal layer may be provided to improve the adhesion with the substrate 10.
[0088]
Next, a layer to be peeled 13 is formed on the oxide layer 12. (FIG. 1 (A)) The layer to be peeled 13 may be a layer including various elements typified by TFTs (thin film diodes, photoelectric conversion elements made of silicon PIN junctions, and silicon resistance elements). Further, heat treatment within a range that the substrate 10 can withstand can be performed. In the present invention, even if the film stress of the oxide layer 12 and the film stress of the nitride layer or the metal layer 11 are different, the film is not peeled off by the heat treatment in the manufacturing process of the layer to be peeled 13.
[0089]
Next, the substrate 10 provided with the nitride layer or the metal layer 11 is peeled off by physical means. (FIG. 1 (B)) Since the film stress of the oxide layer 12 and the film stress of the nitride layer or the metal layer 11 are different, it can be peeled off with a relatively small force. In this example, it is assumed that the mechanical strength of the peelable layer 13 is sufficient. However, when the mechanical strength of the peelable layer 13 is insufficient, the peelable layer 13 is fixed. It is preferable to peel off after attaching a support (not shown).
[0090]
Thus, the layer to be peeled 13 formed on the oxide layer 12 can be separated from the substrate 10. The state after peeling is shown in FIG.
[0091]
In the experiment, even when the metal layer 11 is a tungsten film 10 nm and the oxide layer 12 is a silicon oxide film 200 nm by sputtering, peeling can be confirmed by the peeling method of the present invention. As a result, even if the silicon oxide film is 100 nm by sputtering, peeling can be confirmed by the peeling method of the present invention. Even when the metal layer 11 has a tungsten film of 50 nm and the oxide layer 12 has a silicon oxide film of 400 nm formed by sputtering, peeling can be confirmed by the peeling method of the present invention.
[0092]
Further, after peeling, the peeled layer 13 to be peeled may be attached to a transfer body (not shown).
[0093]
Further, the present invention can be used for various manufacturing methods of semiconductor devices. In particular, the weight can be reduced by using a plastic substrate as the transfer body or the support.
[0094]
In the case of manufacturing a liquid crystal display device, the support may be attached to the layer to be peeled using the support as a counter substrate and a sealant as an adhesive. In this case, an element provided in the layer to be peeled has a pixel electrode, and a liquid crystal material is filled between the pixel electrode and the counter substrate. The order in which the liquid crystal display device is manufactured is not particularly limited, and a counter substrate as a support may be attached, and after injecting liquid crystal, the substrate may be peeled off and a plastic substrate as a transfer member may be attached. After the pixel electrode is formed, the substrate may be peeled off, a plastic substrate as a first transfer body may be attached, and then a counter substrate as a second transfer body may be attached.
[0095]
In the case of manufacturing a light-emitting device typified by a light-emitting device having an EL element, a support is used as a sealing material so that a substance that promotes deterioration of an organic compound layer such as moisture or oxygen can be prevented from entering from the outside. It is preferable to completely block the light emitting element from the outside. In the case of manufacturing a light-emitting device typified by a light-emitting device having an EL element, not only a support but also a transfer body similarly penetrates a substance that sufficiently promotes deterioration of an organic compound layer such as moisture and oxygen from the outside. It is preferable to prevent this. The order of manufacturing the light-emitting device is not particularly limited, and after forming the light-emitting element, a plastic substrate as a support may be attached, the substrate may be peeled off, and a plastic substrate as a transfer member may be attached. After the light emitting element is formed, the substrate may be peeled off and a plastic substrate as a first transfer body may be attached, and then a plastic substrate as a second transfer body may be attached.
[0096]
(Embodiment 2)
In this embodiment mode, a base insulating layer that is in contact with a layer to be peeled is provided to prevent diffusion of impurities from a nitride layer, a metal layer, or a substrate, and a peeling procedure for peeling the substrate is simply shown in FIG. .
[0097]
In FIG. 2A, 20 is a substrate, 21 is a nitride layer or metal layer, 22 is an oxide layer, 23a and 23b are base insulating layers, and 24 is a layer to be peeled.
[0098]
In FIG. 2A, the substrate 20 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Further, a silicon substrate, a metal substrate, or a stainless steel substrate may be used.
[0099]
First, a nitride layer or a metal layer 21 is formed on the substrate 20 as shown in FIG. Typical examples of the nitride layer or metal layer 21 include Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, A single layer made of an element selected from Pt, or an alloy material or a compound material containing the element as a main component, or a laminate thereof, or a nitride thereof, for example, titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride A single layer made of or a laminate of these may be used.
[0100]
Next, an oxide layer 22 is formed on the nitride layer or metal layer 21. As a typical example of the oxide layer 22, silicon oxide, silicon oxynitride, or a metal oxide material may be used. Note that the oxide layer 22 may be formed by any film formation method such as sputtering, plasma CVD, or coating.
[0101]
In the present invention, it is important to make the film stress of the oxide layer 22 different from the film stress of the nitride layer or the metal layer 21. Each film thickness may be appropriately set within a range of 1 nm to 1000 nm, and each film stress may be adjusted. 2 shows an example in which the nitride layer or the metal layer 21 is formed in contact with the substrate 20 in order to simplify the process. However, an insulation is provided between the substrate 20 and the nitride layer or the metal layer 21. A layer or a metal layer may be provided to improve the adhesion with the substrate 20.
[0102]
Next, base insulating layers 23 a and 23 b are formed over the oxide layer 22. Here, the film formation temperature is 400 ° C. by the plasma CVD method, and the source gas SiH. _Four , NH _Three , N ₂ A silicon oxynitride film 23a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) formed from O is formed to a thickness of 50 nm (preferably 10 to 200 nm), and further by plasma CVD. Deposition temperature 400 ° C, source gas SiH _Four , N ₂ A silicon oxynitride film 23b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) made of O was laminated to a thickness of 100 nm (preferably 50 to 200 nm). The layer is not particularly limited, and may be a single layer or a laminate of three or more layers.
[0103]
Next, the layer to be peeled 24 is formed over the base insulating layer 23b. (Fig. 2 (A))
[0104]
When such two base insulating layers 23a and 23b are used, diffusion of impurities from the nitride layer or metal layer 21 or the substrate 20 can be prevented in the process of forming the layer 24 to be peeled. In addition, the adhesion between the oxide layer 22 and the layer to be peeled 24 can be improved by the base insulating layers 23a and 23b.
[0105]
In the case where irregularities are formed on the surface by the nitride layer or the metal layer 21 or the oxide layer 22, the surface may be planarized before and after the base insulating layer is formed. It is preferable to perform planarization when the layer to be peeled 24 has good coverage, and when the layer to be peeled 24 including elements is formed, the element characteristics are easily stabilized. Note that as this planarization treatment, an etch-back method in which a coating film (resist film or the like) is formed and then planarized by etching or the like, a mechanical chemical polishing method (CMP method), or the like may be used.
[0106]
Next, the substrate 20 provided with the nitride layer or the metal layer 21 is peeled off by physical means. (FIG. 2B) Since the film stress of the oxide layer 22 and the film stress of the nitride layer or the metal layer 21 are different, the oxide layer 22 can be peeled off with a relatively small force. In this example, it is assumed that the mechanical strength of the peelable layer 24 is sufficient. However, when the mechanical strength of the peelable layer 24 is insufficient, the peelable layer 24 is fixed. It is preferable to peel off after attaching a support (not shown).
[0107]
In this way, the layer to be peeled 24 formed on the base insulating layer 22 can be separated from the substrate 20. The state after peeling is shown in FIG.
[0108]
Further, after peeling off, the peeled off layer 24 may be attached to a transfer body (not shown).
[0109]
Further, the present invention can be used for various manufacturing methods of semiconductor devices. In particular, the weight can be reduced by using a plastic substrate as the transfer body or the support.
[0110]
In the case of manufacturing a liquid crystal display device, the support may be attached to the layer to be peeled using the support as a counter substrate and a sealant as an adhesive. In this case, an element provided in the layer to be peeled has a pixel electrode, and a liquid crystal material is filled between the pixel electrode and the counter substrate. The order in which the liquid crystal display device is manufactured is not particularly limited, and a counter substrate as a support may be attached, and after injecting liquid crystal, the substrate may be peeled off and a plastic substrate as a transfer member may be attached. After the pixel electrode is formed, the substrate may be peeled off, a plastic substrate as a first transfer body may be attached, and then a counter substrate as a second transfer body may be attached.
[0111]
In the case of manufacturing a light-emitting device typified by a light-emitting device having an EL element, a support is used as a sealing material so that a substance that promotes deterioration of an organic compound layer such as moisture or oxygen can be prevented from entering from the outside. It is preferable to completely block the light emitting element from the outside. In the case of manufacturing a light-emitting device typified by a light-emitting device having an EL element, not only a support but also a transfer body similarly penetrates a substance that sufficiently promotes deterioration of an organic compound layer such as moisture and oxygen from the outside. It is preferable to prevent this. The order of manufacturing the light-emitting device is not particularly limited, and after forming the light-emitting element, a plastic substrate as a support may be attached, the substrate may be peeled off, and a plastic substrate as a transfer member may be attached. After the light emitting element is formed, the substrate may be peeled off and a plastic substrate as a first transfer body may be attached, and then a plastic substrate as a second transfer body may be attached.
[0112]
(Embodiment 3)
In this embodiment, in addition to Embodiment 1, an example in which laser light irradiation or heat treatment is performed to further promote separation is illustrated in FIG.
[0113]
In FIG. 4A, 40 is a substrate, 41 is a nitride layer or metal layer, 42 is an oxide layer, and 43 is a layer to be peeled.
[0114]
Since the process to form the layer 43 to be peeled is the same as that in Embodiment 1, it is omitted.
[0115]
After the peeled layer 43 is formed, laser light irradiation is performed. (FIG. 3 (A)) As the laser light, a gas laser such as an excimer laser, or YVO _Four A solid-state laser such as a laser or a YAG laser, or a semiconductor laser may be used. The laser oscillation may be either continuous oscillation or pulse oscillation, and the laser beam may be linear, rectangular, circular, or elliptical. The wavelength used may be any of the fundamental wave, the second harmonic, and the third harmonic.
[0116]
The material used for the nitride layer or the metal layer 41 is desirably a material that easily absorbs laser light, and titanium nitride is preferable. In addition, in order to let a laser beam pass, the board | substrate which has translucency is used for the board | substrate 40. FIG.
[0117]
Next, the substrate 40 provided with the nitride layer or the metal layer 41 is peeled off by physical means. (FIG. 4B) Since the film stress of the oxide layer 42 and the film stress of the nitride layer or the metal layer 41 are different, they can be peeled off with a relatively small force.
[0118]
By irradiating the laser beam, the interface between the nitride layer or the metal layer 41 and the oxide layer 42 is heated, thereby changing the film stress of each other and promoting peeling. Can be peeled off. In this example, it is assumed that the mechanical strength of the peelable layer 43 is sufficient. However, when the mechanical strength of the peelable layer 43 is insufficient, the peelable layer 43 is fixed. It is preferable to peel off after attaching a support (not shown).
[0119]
Thus, the layer 43 to be peeled formed on the oxide layer 42 can be separated from the substrate 40. The state after peeling is shown in FIG.
[0120]
Further, the present invention is not limited to laser light, and visible light, infrared light, ultraviolet light, microwaves, or the like from a light source such as a halogen lamp may be used.
[0121]
Further, heat treatment in an electric furnace may be used instead of the laser beam.
[0122]
In addition, a heat treatment or a laser light irradiation treatment may be performed before the support is bonded or before peeling by the physical means.
[0123]
Further, this embodiment mode can be combined with Embodiment Mode 2.
[0124]
(Embodiment 4)
In this embodiment, in addition to Embodiment 1, in order to further promote separation, an example in which a granular oxide is provided at an interface between a nitride layer or a metal layer and an oxide layer is illustrated in FIG.
[0125]
In FIG. 5A, 50 is a substrate, 51 is a nitride layer or metal layer, 52a is a granular oxide, 52b is an oxide layer, and 53 is a layer to be peeled.
[0126]
The process of forming the nitride layer or the metal layer 51 is the same as that of the first embodiment, and therefore will be omitted.
[0127]
After forming the nitride layer or metal layer 51, the granular oxide 52a is formed. As the granular oxide 52a, a metal oxide material, for example, ITO (indium tin oxide alloy), indium oxide zinc oxide alloy (In ₂ O _Three —ZnO), zinc oxide (ZnO), or the like may be used.
[0128]
Next, an oxide layer 52b is formed to cover the granular oxide 52a. As a typical example of the oxide layer 52b, silicon oxide, silicon oxynitride, or a metal oxide material may be used. Note that the oxide layer 23b may use any film formation method such as a sputtering method, a plasma CVD method, or a coating method.
[0129]
Next, the layer to be peeled 53 is formed over the oxide layer 52b. (Fig. 5 (A))
[0130]
Next, the substrate 50 provided with the nitride layer or the metal layer 51 is peeled off by physical means. (FIG. 5B) Since the film stress of the oxide layer 52 and the film stress of the nitride layer or the metal layer 51 are different, the oxide layer 52 can be peeled off with a relatively small force.
[0131]
By providing the granular oxide 52b, it is possible to weaken the bonding force between the nitride layer or metal layer 51 and the oxide layer 52, to change the adhesion between them, and to promote peeling, with a smaller force. Can be peeled off. In this example, it is assumed that the mechanical strength of the layer to be peeled 53 is sufficient, but when the mechanical strength of the layer to be peeled 53 is insufficient, the layer to be peeled 53 is fixed. It is preferable to peel off after attaching a support (not shown).
[0132]
Thus, the layer 53 to be peeled formed on the oxide layer 52b can be separated from the substrate 50. The state after peeling is shown in FIG.
[0133]
Further, this embodiment mode can be combined with Embodiment Mode 2 or Embodiment Mode 3.
[0134]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0135]
(Example)
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail.
[0136]
First, a nitride layer or a metal layer 101, an oxide layer 102, and a base insulating film 103 are formed over a substrate 100 to obtain a semiconductor film having a crystal structure, and then etched into a desired shape to be separated into islands. The formed semiconductor layers 104 to 108 are formed.
[0137]
As the substrate 100, a glass substrate (# 1737) is used.
[0138]
The metal layer 101 is an element selected from Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt. Alternatively, a single layer made of an alloy material or a compound material containing the element as a main component, or a stacked layer thereof may be used. More preferably, a single layer of these nitrides, for example, titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride, or a stacked layer thereof may be used. Here, a titanium nitride film having a thickness of 100 nm is used by sputtering.
[0139]
As the oxide layer 102, a single layer formed of a silicon oxide material or a metal oxide material, or a stacked layer thereof may be used. Here, a silicon oxide film having a thickness of 200 nm is used by a sputtering method. The bonding force between the metal layer 101 and the oxide layer 102 is strong during heat treatment and does not cause film peeling (also called peeling), but can be easily peeled off within the oxide layer or at the interface by physical means. Can do.
[0140]
In addition, as the base insulating film 103, a film formation temperature of 400 ° C. and a source gas SiH are formed by plasma CVD. _Four , NH _Three , N ₂ A silicon oxynitride film 103a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) formed from O is formed to a thickness of 50 nm (preferably 10 to 200 nm). Next, after cleaning the surface with ozone water, the oxide film on the surface is removed with dilute hydrofluoric acid (1/100 dilution). Next, the film formation temperature is 400 ° C. by the plasma CVD method, and the source gas SiH _Four , N ₂ A silicon oxynitride film 103b made of O (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is stacked to a thickness of 100 nm (preferably 50 to 200 nm), Furthermore, the film deposition temperature is 300 ° C. and the film deposition gas SiH is formed by plasma CVD without opening to the atmosphere. _Four A semiconductor film having an amorphous structure (here, an amorphous silicon film) is formed with a thickness of 54 nm (preferably 25 to 80 nm).
[0141]
Although the base film 103 is shown as a two-layer structure in this embodiment, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are stacked. The material of the semiconductor film is not limited, but preferably silicon or silicon germanium (Si _X Ge _1-X (X = 0.0001 to 0.02)) An alloy or the like may be used and may be formed by a known means (such as sputtering, LPCVD, or plasma CVD). The plasma CVD apparatus may be a single wafer type apparatus or a batch type apparatus. Alternatively, the base insulating film and the semiconductor film may be successively formed without being exposed to the air in the same film formation chamber.
[0142]
Next, after cleaning the surface of the semiconductor film having an amorphous structure, an extremely thin oxide film of about 2 nm is formed on the surface with ozone water. Next, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold value of the TFT. Here, diborane (B ₂ H ₆ ) Using a plasma-excited ion doping method without mass separation, a doping condition of an acceleration voltage of 15 kV, diborane diluted to 1% with hydrogen, a gas flow rate of 30 sccm, a dose of 2 × 10 ¹² / Cm ² Then, boron was added to the amorphous silicon film.
[0143]
Next, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used.
[0144]
Next, heat treatment is performed for crystallization, so that a semiconductor film having a crystal structure is formed. For this heat treatment, heat treatment in an electric furnace or irradiation with strong light may be used. When the heat treatment is performed in an electric furnace, the heat treatment may be performed at 500 ° C. to 650 ° C. for 4 to 24 hours. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. Note that although crystallization is performed here using heat treatment using a furnace, crystallization may be performed using a lamp annealing apparatus. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.
[0145]
Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, a first laser beam (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in the crystal grains ) Is performed in the air or in an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of a YAG laser are used. In any case, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is 100 to 500 mJ / cm in an optical system. ² And the surface of the silicon film may be scanned by irradiating with an overlap rate of 90 to 95%. Here, repetition frequency 30Hz, energy density 393mJ / cm ² Then, the first laser beam is irradiated in the atmosphere. Note that an oxide film is formed on the surface by irradiation with the first laser light because it is performed in the air or in an oxygen atmosphere.
[0146]
Next, after removing the oxide film formed by irradiation with the first laser beam with dilute hydrofluoric acid, irradiation with the second laser beam is performed in a nitrogen atmosphere or in a vacuum to flatten the surface of the semiconductor film. As this laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of a YAG laser are used. The energy density of the second laser beam is larger than the energy density of the first laser beam, preferably 30 to 60 mJ / cm. ² Enlarge. Here, repetition frequency 30Hz, energy density 453mJ / cm ² Then, the second laser beam is irradiated, and the PV value (Peak to Valley, difference between the maximum value and the minimum value) of the unevenness on the surface of the semiconductor film becomes 50 nm or less. This PV value is obtained by an AFM (atomic force microscope).
[0147]
In this embodiment, the second laser beam is irradiated on the entire surface. However, since the reduction of the off-current is particularly effective for the TFT in the pixel portion, it is possible to selectively irradiate at least the pixel portion. Good.
[0148]
Next, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm.
[0149]
Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 150 nm on the barrier layer by a sputtering method. The film formation conditions by the sputtering method of this embodiment are as follows: the film formation pressure is 0.3 Pa, the gas (Ar) flow rate is 50 (sccm), the film formation power is 3 kW, and the substrate temperature is 150 ° C. Note that the atomic concentration of the argon element contained in the amorphous silicon film under the above conditions is 3 × 10 ²⁰ / Cm ^Three ~ 6 × 10 ²⁰ / Cm ^Three The atomic concentration of oxygen is 1 × 10 ¹⁹ / Cm ^Three ~ 3x10 ¹⁹ / Cm ^Three It is. Thereafter, heat treatment is performed at 650 ° C. for 3 minutes using a lamp annealing apparatus to perform gettering.
[0150]
Next, the amorphous silicon film containing an argon element as a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.
[0151]
Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of resist is formed and etched into a desired shape to form islands. The separated semiconductor layers 104 to 108 are formed. After the semiconductor layer is formed, the resist mask is removed.
[0152]
Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component and serving as the gate insulating film 109 is formed. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed to a thickness of 115 nm by plasma CVD.
[0153]
Next, as illustrated in FIG. 6A, a first conductive film 110 a with a thickness of 20 to 100 nm and a second conductive film 110 b with a thickness of 100 to 400 nm are stacked over the gate insulating film 109. In this embodiment, a tantalum nitride film with a thickness of 50 nm and a tungsten film with a thickness of 370 nm are sequentially stacked on the gate insulating film 109.
[0154]
The conductive material for forming the first conductive film and the second conductive film is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Form. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked. Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.
[0155]
Next, as shown in FIG. 6B, resists 112 to 117 are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. For etching, an ICP (Inductively Coupled Plasma) etching method may be used. Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. As an etching gas, Cl ₂ , BCl _Three , SiCl _Four , CCl _Four Chlorine gas or CF represented by _Four , SF ₆ , NF _Three Fluorine gas such as O ₂ Can be used as appropriate.
[0156]
In this embodiment, 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, the quartz disk provided with the coil) is a disk having a diameter of 25 cm. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered. Under the first etching conditions, the etching rate with respect to W is 200.39 nm / min, the etching rate with respect to TaN is 80.32 nm / min, and the selection ratio of W with respect to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition. Thereafter, the resist masks 112 to 117 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ The gas flow ratio is 30/30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and etching for about 30 seconds. Went. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0157]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.
[0158]
Thus, the first shape conductive layers 119 to 123 (first conductive layers 119 a to 123 a and second conductive layers 119 b to 123 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. The insulating film 109 to be a gate insulating film is etched by about 10 to 20 nm to become a gate insulating film 118 in which a region not covered with the first shape conductive layers 119 to 123 is thinned.
[0159]
Next, a second etching process is performed without removing the resist mask. Here, SF is used as the etching gas. ₆ And Cl ₂ And O ₂ The gas flow ratio is 24/12/24 (sccm), and 700 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.3 Pa to generate plasma and perform etching. 25 seconds. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selection ratio of W with respect to TaN is 7.1, and the SiON that is the insulating film 118 The etching rate with respect to is 33.7 nm / min, and the selective ratio of W to SiON is 6.83. In this way, SF is used as the etching gas. ₆ Is used, the selectivity with respect to the insulating film 118 is high, so that film loss can be suppressed. In this embodiment, the insulating film 118 is reduced only by about 8 nm.
[0160]
By this second etching process, the taper angle of W became 70 °. The second conductive layers 126b to 131b are formed by this second etching process. On the other hand, the first conductive layer is hardly etched and becomes the first conductive layers 126a to 131a. Note that the first conductive layers 126a to 131a are approximately the same size as the first conductive layers 119a to 124a. In actuality, the width of the first conductive layer may be about 0.3 μm, that is, the entire line width may recede by about 0.6 μm compared to before the second etching process, but there is almost no change in size.
[0161]
In place of the two-layer structure, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum and silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked, As the first etching condition of the first etching process, BCl _Three And Cl ₂ And O ₂ Are used as source gases, each gas flow rate ratio is 65/10/5 (sccm), 300 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and the coil is operated at a pressure of 1.2 Pa. 450 W RF (13.56 MHz) power is applied to the electrode of the mold to generate plasma and perform etching for 117 seconds. The second etching condition of the first etching process is CF _Four And Cl ₂ And O ₂ Each gas flow rate ratio is 25/25/10 (sccm), 20 W RF (13.56 MHz) power is supplied to the substrate side (sample stage), and a coil type electrode is applied at a pressure of 1 Pa. An RF (13.56 MHz) power of 500 W is applied to generate plasma, and etching may be performed for about 30 seconds. As the second etching process, BCl is used. _Three And Cl ₂ Each gas flow rate ratio is 20/60 (sccm), 100 W RF (13.56 MHz) power is supplied to the substrate side (sample stage), and 600 W is applied to the coil-type electrode at a pressure of 1.2 Pa. RF (13.56 MHz) power may be input to generate plasma and perform etching.
[0162]
Next, after removing the resist mask, a first doping process is performed to obtain the state of FIG. The doping process may be performed by ion doping or ion implantation. The condition of the ion doping method is that the dose is 1.5 × 10 ¹⁴ atoms / cm ² The acceleration voltage is set to 60 to 100 keV. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. In this case, the first conductive layer and the second conductive layers 126 to 130 serve as a mask for the impurity element imparting n-type, and the first impurity regions 132 to 136 are formed in a self-aligning manner. The first impurity regions 132 to 136 have 1 × 10 ¹⁶ ~ 1x10 ¹⁷ /cm ^Three An impurity element imparting n-type is added in a concentration range of. Here, a region having the same concentration range as the first impurity region is n ^- Also called a region.
[0163]
In this embodiment, the first doping process is performed after removing the resist mask, but the first doping process may be performed without removing the resist mask.
[0164]
Next, as shown in FIG. 7A, masks 137 to 139 made of resist are formed, and a second doping process is performed. The mask 137 is a mask for protecting the channel formation region of the semiconductor layer for forming the p-channel TFT of the driver circuit and its peripheral region, and the mask 138 is for the semiconductor layer for forming one of the n-channel TFT of the driver circuit. The mask 139 is a mask for protecting the channel formation region and its peripheral region, and the mask 139 is a mask for protecting the channel formation region of the semiconductor layer forming the TFT of the pixel portion, its peripheral region, and the region serving as a storage capacitor.
[0165]
The condition of the ion doping method in the second doping process is that the dose is 1.5 × 10 5. ¹⁵ atoms / cm ² Then, phosphorus (P) is doped with an acceleration voltage of 60 to 100 keV. Here, impurity regions are formed in a self-aligned manner in each semiconductor layer using the second conductive layers 126b to 128b as masks. Of course, it is not added to the region covered with the masks 137 to 139. Thus, second impurity regions 140 to 142 and a third impurity region 144 are formed. The second impurity regions 140 to 142 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting n-type is added in a concentration range of. Here, a region having the same concentration range as the second impurity region is n ⁺ Also called a region.
[0166]
The third impurity region is formed at a lower concentration than the second impurity region by the first conductive layer, and is 1 × 10 6. ¹⁸ ~ 1x10 ¹⁹ /cm ^Three An impurity element imparting n-type is added in a concentration range of. Note that the third impurity region has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion because doping is performed by passing the portion of the first conductive layer having a tapered shape. . Here, a region having the same concentration range as the third impurity region is n ^- Also called a region. In addition, the regions covered with the masks 138 and 139 become the first impurity regions 146 and 147 without being doped with the impurity element in the second doping process.
[0167]
Next, after removing the resist masks 137 to 139, new resist masks 148 to 150 are formed, and a third doping process is performed as shown in FIG. 7B.
[0168]
In the driver circuit, a fourth impurity region 151 in which an impurity element imparting p-type conductivity is added to the semiconductor layer forming the p-channel TFT and the semiconductor layer forming the storage capacitor by the third doping process. , 152 and fifth impurity regions 153, 154 are formed.
[0169]
The fourth impurity regions 151 and 152 have 1 × 10 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting p-type is added in a concentration range of. Note that the fourth impurity regions 151 and 152 are regions (n) to which phosphorus (P) is added in the previous step. ^- The concentration of the impurity element imparting p-type is 1.5 to 3 times that of the impurity element, and the conductivity type is p-type. Here, a region having the same concentration range as the fourth impurity region is represented by p. ⁺ Also called a region.
[0170]
The fifth impurity regions 153 and 154 are formed in a region overlapping with the tapered portion of the second conductive layer 127a. ¹⁸ ~ 1x10 ²⁰ /cm ^Three An impurity element imparting p-type is added in a concentration range of. Here, a region having the same concentration range as the fifth impurity region is represented by p. ^- Also called a region.
[0171]
Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer. The conductive layers 126 to 129 become TFT gate electrodes. The conductive layer 130 serves as one electrode forming a storage capacitor in the pixel portion. Further, the conductive layer 131 forms a source wiring in the pixel portion.
[0172]
Next, an insulating film (not shown) that covers substantially the entire surface is formed. In this example, a 50 nm-thickness silicon oxide film was formed by plasma CVD. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.
[0173]
Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.
[0174]
Further, in this embodiment, an example in which an insulating film is formed before the activation is shown, but an insulating film may be formed after the activation.
[0175]
Next, a first interlayer insulating film 155 made of a silicon nitride film is formed and subjected to a heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to hydrogenate the semiconductor layer. (FIG. 7C) This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 155. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. However, in this embodiment, since the material containing aluminum as a main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0176]
Next, a second interlayer insulating film 156 made of an organic insulating material is formed on the first interlayer insulating film 155. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole reaching the source wiring 131, a contact hole reaching the conductive layers 129 and 130, and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed. In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using the insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). Not etched).
[0177]
Thereafter, wirings and pixel electrodes are formed using Al, Ti, Mo, W, or the like. As materials for these electrodes and pixel electrodes, it is desirable to use a material having excellent reflectivity such as a film mainly composed of Al or Ag, or a laminated film thereof. Thus, the source or drain electrodes 157 to 162, the gate wiring 164, the connection wiring 163, and the pixel electrode 165 are formed.
[0178]
As described above, the pixel portion 207 including the driving circuit 206 including the n-channel TFT 201, the p-channel TFT 202, and the n-channel TFT 203, the pixel TFT 204 including the n-channel TFT, and the storage capacitor 205 is formed over the same substrate. Can be formed. (FIG. 8) In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0179]
In the pixel portion 207, the pixel TFT 204 (n-channel TFT) includes a channel formation region 169 and a first impurity region (n formed outside the conductive layer 129 forming the gate electrode). ^- Region) 147 and a second impurity region (n that functions as a source region or a drain region) ⁺ Region) 142 and 171. A fourth impurity region 152 and a fifth impurity region 154 are formed in the semiconductor layer functioning as one electrode of the storage capacitor 205. The storage capacitor 205 is formed of the second electrode 130 and the semiconductor layers 152, 154, and 170 using the insulating film (the same film as the gate insulating film) 118 as a dielectric.
[0180]
In the driver circuit 206, the n-channel TFT 201 (first n-channel TFT) includes a third impurity region (a first n-channel TFT) that overlaps with a channel formation region 166 and part of the conductive layer 126 forming a gate electrode with an insulating film interposed therebetween. n ^- Region) 144 and a second impurity region (n that functions as a source region or a drain region) ⁺ Region) 140.
[0181]
Further, in the driver circuit 206, the p-channel TFT 202 includes a channel formation region 167 and a fifth impurity region (p that overlaps with a part of the conductive layer 127 forming the gate electrode through an insulating film). ^- Region) 153 and a fourth impurity region (p) functioning as a source region or a drain region ⁺ Region) 151.
[0182]
In the driver circuit 206, the n-channel TFT 203 (second n-channel TFT) includes a channel formation region 168 and a first impurity region (n ^- Region) 146 and a second impurity region (n that functions as a source region or a drain region) ⁺ Region) 141.
[0183]
A driving circuit 206 may be formed by appropriately combining these TFTs 201 to 203 to form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like. For example, in the case of forming a CMOS circuit, an n-channel TFT 201 and a p-channel TFT 202 may be complementarily connected.
[0184]
In particular, the structure of the n-channel TFT 203 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.
[0185]
In addition, the structure of the n-channel TFT 201 having a GOLD structure is suitable for a circuit in which reliability is given the highest priority.
[0186]
In addition, since the reliability can be improved by improving the planarization of the surface of the semiconductor film, it is sufficient to reduce the area of the impurity region overlapping with the gate electrode and the gate insulating film in the GOLD structure TFT. Reliability can be obtained. Specifically, sufficient reliability can be obtained even if the size of the portion that becomes the tapered portion of the gate electrode is reduced in the GOLD structure TFT.
[0187]
Further, in the GOLD structure TFT, the parasitic capacitance increases as the gate insulating film becomes thin. However, if the parasitic capacitance is reduced by reducing the size of the portion that becomes the tapered portion of the gate electrode (first conductive layer), the f characteristic ( (Frequency characteristics) is improved, and a higher speed operation is possible, and a TFT having sufficient reliability is obtained.
[0188]
Note that also in the pixel TFT of the pixel portion 207, reduction of off-state current and variation are realized by irradiation with the second laser light.
[0189]
In this embodiment, an example of manufacturing an active matrix substrate for forming a reflective display device is shown. However, when a pixel electrode is formed of a transparent conductive film, a photomask is increased by one, but a transmissive display is provided. A device can be formed.
[0190]
Further, although a glass substrate is used in this embodiment, it is not particularly limited, and a quartz substrate, a semiconductor substrate, a ceramic substrate, or a metal substrate can be used.
[0191]
Further, after obtaining the state of FIG. 8, the substrate 100 may be peeled off if the mechanical strength of the layer including the TFT (the layer to be peeled) provided over the oxide layer 102 is sufficient. In this example, since the mechanical strength of the layer to be peeled is insufficient, it is preferable to peel off after attaching a support (not shown) for fixing the layer to be peeled.
[0192]
[Example 2]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device by peeling the substrate 100 from the active matrix substrate manufactured in Embodiment 1 and bonding a plastic substrate will be described below. FIG. 9 is used for the description.
[0193]
In FIG. 9A, 400 is a substrate, 401 is a nitride layer or metal layer, 402 is an oxide layer, 403 is a base insulating layer, 404a is an element of the driver circuit 413, 404b is an element 404b or 405 of the pixel portion 414. Is a pixel electrode. Here, an element refers to a semiconductor element (typically a TFT) or an MIM element used as a switching element of a pixel in an active matrix liquid crystal display device. The active matrix substrate shown in FIG. 9A is a simplified version of the active matrix substrate shown in FIG. 8, and the substrate 100 in FIG. 8 corresponds to the substrate 400 in FIG. 9A. Yes. Similarly, 401 in FIG. 9A is 101 in FIG. 8, 402 in FIG. 9A is 102 in FIG. 8, 403 in FIG. 9A is in FIG. 103, 404a in FIG. 9A, 201 and 202 in FIG. 8, 404b in FIG. 9A, 204 in FIG. 8, and 405 in FIG. 8 corresponds to 165 of 8, respectively.
[0194]
First, after obtaining the active matrix substrate in the state of FIG. 8 according to Example 1, an alignment film 406a is formed on the active matrix substrate of FIG. 8 and a rubbing process is performed. In this embodiment, before forming the alignment film, a columnar spacer (not shown) for holding the substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0195]
Next, a counter substrate to be a support body 407 is prepared. The counter substrate is provided with a color filter (not shown) in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light shielding layer was also provided in the drive circuit portion. A flattening film (not shown) covering the color filter and the light shielding layer was provided. Next, a counter electrode 408 made of a transparent conductive film was formed over the planarizing film in the pixel portion, an alignment film 406b was formed over the entire surface of the counter substrate, and a rubbing process was performed.
[0196]
Then, the active matrix substrate 400 over which the pixel portion and the driver circuit are formed and the support 407 are attached to each other with a sealant that becomes the adhesive layer 409. A filler is mixed in the sealing material, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 410 is injected between both substrates and completely sealed with a sealant (not shown). (FIG. 9B) A known liquid crystal material may be used for the liquid crystal material 410.
[0197]
Next, the substrate 400 provided with the nitride layer or the metal layer 401 is peeled off by physical means. (FIG. 9C) Since the film stress of the oxide layer 402 and the film stress of the nitride layer or the metal layer 401 are different, the oxide layer 402 can be peeled off with a relatively small force.
[0198]
Next, it is attached to the transfer body 412 with an adhesive layer 411 such as an epoxy resin. In this embodiment, the transfer body 412 is a plastic film substrate to reduce the weight.
[0199]
In this way, a flexible active matrix liquid crystal display device is completed. If necessary, the flexible substrate 412 or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate (not shown) or the like was appropriately provided using a known technique. And FPC (not shown) was affixed using the well-known technique.
[0200]
[Example 3]
In Example 2, an example was shown in which a counter substrate as a support was attached, a liquid crystal was injected, the substrate was peeled off, and a plastic substrate as a transfer member was attached. In this example, FIG. In this example, after the active matrix substrate is formed, the substrate is peeled off, and the plastic substrate as the first transfer body and the plastic substrate as the second transfer body are attached. FIG. 10 is used for the description.
[0201]
In FIG. 10A, 500 is a substrate, 501 is a nitride layer or metal layer, 502 is an oxide layer, 503 is a base insulating layer, 504a is an element of the driver circuit 514, 504b is an element 504b or 505 of the pixel portion 515. Is a pixel electrode. The active matrix substrate shown in FIG. 10A is a simplified version of the active matrix substrate shown in FIG. 8, and the substrate 100 in FIG. 8 corresponds to the substrate 500 in FIG. 10A. Yes. Similarly, 501 in FIG. 10A is 101 in FIG. 8, 502 in FIG. 10A is 102 in FIG. 8, 503 in FIG. 10A is in FIG. 103, 504a in FIG. 10A is 201 and 202 in FIG. 8, 504b in FIG. 10A is 204 in FIG. 8, 505 in FIG. 8 corresponds to 165 of 8, respectively.
[0202]
First, after obtaining the active matrix substrate in the state of FIG. 8 according to Example 1, the substrate 500 provided with the nitride layer or the metal layer 501 is peeled off by physical means. (FIG. 10B) Since the film stress of the oxide layer 502 and the film stress of the nitride layer or the metal layer 501 are different, the oxide layer 502 can be peeled off with a relatively small force.
[0203]
Next, the transfer body 507 (first transfer body) is pasted with an adhesive layer 506 such as an epoxy resin. In this embodiment, the transfer body 507 is a plastic film substrate to reduce the weight. (Fig. 10 (C))
[0204]
Next, an alignment film 508a is formed and a rubbing process is performed. In this embodiment, before forming the alignment film, a columnar spacer (not shown) for holding the substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0205]
Next, a counter substrate to be a support 510 (second transfer member) is prepared. The counter substrate is provided with a color filter (not shown) in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light shielding layer was also provided in the drive circuit portion. A flattening film (not shown) covering the color filter and the light shielding layer was provided. Next, a counter electrode 509 made of a transparent conductive film was formed over the planarization film in the pixel portion, an alignment film 508b was formed over the entire surface of the counter substrate, and a rubbing process was performed.
[0206]
Then, the plastic film substrate 507 to which the pixel portion and the driving circuit are bonded and the support 510 are bonded to each other with a sealant that becomes the adhesive layer 512. (FIG. 10D) A filler is mixed in the sealing material, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 513 is injected between both substrates and completely sealed with a sealant (not shown). (FIG. 10D) A known liquid crystal material may be used for the liquid crystal material 513.
[0207]
In this way, a flexible active matrix liquid crystal display device is completed. Then, if necessary, the flexible substrate 507 or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate (not shown) or the like was appropriately provided using a known technique. And FPC (not shown) was affixed using the well-known technique.
[0208]
[Example 4]
The structure of the liquid crystal module obtained in Example 2 or Example 3 will be described with reference to the top view of FIG. The substrate 412 in the second embodiment or the substrate 507 in the third embodiment corresponds to the substrate 301.
[0209]
A pixel portion 304 is disposed at the center of the substrate 301. A source signal line driver circuit 302 for driving the source signal line is disposed above the pixel portion 304. On the left and right sides of the pixel portion 304, gate signal line driving circuits 303 for driving the gate signal lines are arranged. In the example shown in this embodiment, the gate signal line driver circuit 303 is arranged symmetrically with respect to the pixel portion, but this may be arranged only on one side, and the designer may consider the size of the substrate of the liquid crystal module. May be appropriately selected. However, considering the operation reliability and driving efficiency of the circuit, the symmetrical arrangement shown in FIG. 11 is desirable.
[0210]
A signal is input to each drive circuit from a flexible printed circuit (FPC) 305. The FPC 305 opens a contact hole in the interlayer insulating film and the resin film so as to reach the wiring arranged up to a predetermined place on the substrate 301, forms a connection electrode 309, and then crimps it through an anisotropic conductive film or the like. Is done. In this example, the connection electrode was formed using ITO.
[0211]
A sealant 307 is applied to the periphery of the driving circuit and the pixel portion along the outer periphery of the substrate, and a predetermined gap (a space between the substrate 301 and the counter substrate 306) is maintained by the spacer 310 formed on the film substrate in advance. In this state, the counter substrate 306 is attached. Thereafter, a liquid crystal material is injected from a portion where the sealant 307 is not applied, and is sealed with the sealant 308. The liquid crystal module is completed through the above steps.
[0212]
Although an example in which all the drive circuits are formed on the film substrate is shown here, several ICs may be used as a part of the drive circuit.
[0213]
Further, this embodiment can be freely combined with the first embodiment.
[0214]
[Example 5]
In Example 1, an example of a reflective display device in which a pixel electrode is formed of a reflective metal material is shown. However, in this embodiment, a transmissive display in which a pixel electrode is formed of a light-transmitting conductive film. An example of an apparatus is shown.
[0215]
Since the steps up to the formation of the interlayer insulating film are the same as those in the first embodiment, they are omitted here. After the TFT and the interlayer insulating film are formed according to Embodiment 1, a pixel electrode 601 made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium tin oxide alloy), indium oxide zinc oxide alloy (In ₂ O _Three —ZnO), zinc oxide (ZnO), or the like may be used.
[0216]
Thereafter, contact holes are formed in the interlayer insulating film 600. Next, a connection electrode 602 which overlaps with the pixel electrode is formed. The connection electrode 602 is connected to the drain region through a contact hole. In addition, the source electrode or drain electrode of another TFT is formed simultaneously with this connection electrode.
[0217]
Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.
[0218]
An active matrix substrate is formed as described above. Using this active matrix substrate, after peeling off the substrate, a plastic substrate is bonded, a liquid crystal module is manufactured according to Examples 2 to 4, a backlight 604 and a light guide plate 605 are provided, and covered with a cover 606. FIG. An active matrix type liquid crystal display device as shown in a part of the sectional view is completed. Note that the cover and the liquid crystal module are bonded together using an adhesive or an organic resin. In addition, when the plastic substrate and the counter substrate are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded. Further, since it is a transmissive type, the polarizing plate 603 is attached to both the plastic substrate and the counter substrate.
[0219]
In addition, this embodiment can be freely combined with Embodiments 1 to 4.
[0220]
[Example 6]
In this embodiment, an example of manufacturing a light-emitting device including an organic light-emitting element formed over a plastic substrate is shown in FIG.
[0221]
In FIG. 13A, 600 is a substrate, 601 is a nitride layer or metal layer, 602 is an oxide layer, 603 is a base insulating layer, 604a is an element of the driver circuit 611, 604b and 604c are elements of the pixel portion 612, Reference numeral 605 denotes an EL element (Organic Light Emitting Device). Here, an element refers to a semiconductor element (typically a TFT), an MIM element, an EL element, or the like used as a switching element of a pixel in an active matrix light-emitting device. Then, an interlayer insulating film 606 is formed so as to cover these elements. The interlayer insulating film 606 preferably has a flatter surface after film formation. Note that the interlayer insulating film 606 is not necessarily provided.
[0222]
Note that 601 to 603 provided over the substrate 600 may be formed according to any one of Embodiments 2 to 4.
[0223]
These elements (including 604a, 604b, and 604c) may be manufactured according to the n-channel TFT 201 of the first embodiment and the p-channel TFT 202 of the first embodiment. Although an example in which two TFTs are used for one pixel is shown here, three or more TFTs may be used.
[0224]
The EL element 605 includes a layer containing an organic compound (organic light emitting material) from which luminescence generated by applying an electric field is obtained (hereinafter referred to as an organic light emitting layer), an anode layer, and a cathode layer. ing. Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used. In the present specification, all layers formed between the anode and the cathode of the EL element are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the EL element has a structure in which an anode / light emitting layer / cathode is laminated in order, and in addition to this structure, an anode / hole injection layer / light emitting layer / cathode and an anode / hole injection layer. In some cases, the light emitting layer / the electron transporting layer / the cathode are laminated in this order.
[0225]
When the state shown in FIG. 13A is obtained by the above method, the support 608 is attached to the adhesive layer 607. (FIG. 13B) In this embodiment, a plastic substrate is used as the support 608. Specifically, a resin substrate having a thickness of 10 μm or more, such as PES (polyethylene sulfide), PC (polycarbonate), PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) can be used as the support. Note that the support 608 and the adhesive layer 607 are required to be materials that transmit light when positioned on the observer side (the user side of the light-emitting device) as viewed from the EL element.
[0226]
Next, the substrate 600 provided with the nitride layer or the metal layer 601 is peeled off by physical means. (FIG. 13C) Since the film stress of the oxide layer 602 and the film stress of the nitride layer or the metal layer 601 are different, the oxide layer 602 can be peeled off with a relatively small force.
[0227]
Next, it is attached to the transfer body 610 with an adhesive layer 609 such as an epoxy resin. (FIG. 13D) In this embodiment, the transfer body 610 is a plastic film substrate to reduce the weight.
[0228]
Thus, a flexible light-emitting device sandwiched between the flexible support 608 and the flexible transfer body 610 can be obtained. Note that, when the support 608 and the transfer body 610 are made of the same material, the thermal expansion coefficients are equal, and therefore, the influence of stress strain due to a temperature change can be reduced.
[0229]
If necessary, the flexible support 608 and the flexible transfer body 610 are divided into desired shapes. And FPC (not shown) was affixed using the well-known technique.
[0230]
[Example 7]
In Example 6, an example in which the substrate was peeled off and a plastic substrate as a transfer member was attached after the support was attached was shown, but in this example, the first transfer member was peeled off after the substrate was peeled off. And a plastic substrate as a second transfer body are attached to each other to manufacture a light-emitting device including an EL element. FIG. 14 is used for the description.
[0231]
In FIG. 14A, 700 is a substrate, 701 is a nitride layer or metal layer, 702 is an oxide layer, 703 is a base insulating layer, 704a is an element of the driver circuit 711, 704b and 704c are elements of the pixel portion 712, Reference numeral 705 denotes an EL element (Organic Light Emitting Device). Here, an element refers to a semiconductor element (typically a TFT), an MIM element, an EL element, or the like used as a switching element of a pixel in an active matrix light-emitting device. Then, an interlayer insulating film 706 is formed so as to cover these elements. The interlayer insulating film 706 preferably has a flatter surface after film formation. Note that the interlayer insulating film 706 is not necessarily provided.
[0232]
Note that 701 to 703 provided over the substrate 700 may be formed according to any one of Embodiments 2 to 4.
[0233]
These elements (including 704a, 704b, and 704c) may be manufactured according to the n-channel TFT 201 of the first embodiment and the p-channel TFT 202 of the first embodiment.
[0234]
After obtaining the state of FIG. 14A by the above method, the substrate 700 provided with the nitride layer or the metal layer 701 is peeled off by physical means. (FIG. 14B) Since the film stress of the oxide layer 702 and the film stress of the nitride layer or the metal layer 701 are different, the oxide layer 702 can be peeled off with a relatively small force.
[0235]
Next, it is attached to a transfer body (first transfer body) 710 with an adhesive layer 709 such as an epoxy resin. In this embodiment, the transfer body 710 is a plastic film substrate to reduce the weight.
[0236]
Next, a base material (second transfer body) 708 is bonded to the adhesive layer 707. (FIG. 14C) In this embodiment, a plastic substrate is used as the base material 708. Specifically, a resin substrate having a thickness of 10 μm or more, for example, PES (polyethylene sulfide), PC (polycarbonate), PET (polyethylene terephthalate), or PEN (polyethylene naphthalate) is used as the transfer body 710 and the base material 708. Can do. Note that the base material 708 and the adhesive layer 707 are required to be materials that transmit light when positioned on the observer side (the light emitting device user side) as viewed from the EL element.
[0237]
Thus, a flexible light-emitting device sandwiched between the flexible substrate 708 and the flexible transfer body 710 can be obtained. Note that, when the base material 708 and the transfer body 710 are made of the same material, the thermal expansion coefficients are equal to each other, so that it is difficult to be affected by stress distortion due to temperature change.
[0238]
If necessary, the flexible substrate 708 and the flexible transfer body 710 are divided into desired shapes. And FPC (not shown) was affixed using the well-known technique.
[0239]
[Example 8]
In Example 6 or Example 7, an example of obtaining a flexible light-emitting device sandwiched between flexible substrates has been shown. However, a substrate made of plastic generally easily transmits moisture and oxygen, and emits organic light. Since the deterioration of the layers is promoted by these layers, the lifetime of the light emitting device tends to be shortened.
[0240]
Therefore, in this embodiment, a stress is applied between a plurality of films (hereinafter referred to as barrier films) that prevent oxygen and moisture from entering the organic light emitting layer of the EL element on the plastic substrate and between the barrier films. A small layer (stress relaxation film) is provided. In this specification, a film in which a barrier film and a stress relaxation film are stacked is referred to as a sealing film.
[0241]
Specifically, two or more barrier films made of an inorganic material (hereinafter referred to as a barrier film) are provided, and a stress relaxation film (hereinafter referred to as a stress relaxation film) having a resin between the two barrier films. Is provided. Then, an EL element is formed on the three or more insulating films and sealed, thereby forming a light emitting device. Since the configuration other than the substrate is the same as that of Example 6 or Example 7, the description thereof is omitted here.
[0242]
As shown in FIG. 15, two or more barrier films are provided on a film substrate 810, and a stress relaxation film is further provided between the two barrier films. As a result, a sealing film in which the barrier film and the stress relaxation film are laminated is formed between the film substrate 810 and the second adhesive layer 809.
[0243]
Here, a film made of silicon nitride is formed as a barrier film 811a on the film substrate 810 by sputtering, a stress relaxation film 811b including polyimide is formed on the barrier film 811a, and the stress relaxation film 811b is formed. As the barrier film 811c, a film made of silicon nitride is formed by sputtering. A film in which the barrier film 811a, the stress relaxation film 811b, and the barrier film 811c are stacked is collectively referred to as a sealing film 811. Then, the film substrate 810 over which the sealing film 811 is formed may be attached to a layer to be peeled including an element using the second adhesive layer 809.
[0244]
Similarly, a film made of silicon nitride is formed as a barrier film 814a on the film substrate 812 by sputtering, a stress relaxation film 814b containing polyimide is formed on the barrier film 814a, and the stress relaxation film 814b is formed. As the barrier film 814c, a film made of silicon nitride is formed by sputtering. A film in which the barrier film 814a, the stress relaxation film 814b, and the barrier film 814c are stacked is collectively referred to as a sealing film 814. Then, the film substrate 812 over which the sealing film 814 is formed may be attached to a layer to be peeled including elements using the second adhesive layer 809.
[0245]
Note that two or more barrier films may be provided. As the barrier film, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum nitride oxide, or aluminum nitride oxide silicide (AlSiON) can be used.
[0246]
Since aluminum nitride oxide silicide has a relatively high thermal conductivity, the heat generated in the element can be efficiently dissipated by using it for the barrier film.
[0247]
For the stress relaxation film, a light-transmitting resin can be used. Typically, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene, epoxy resin, or the like can be used. Resins other than those described above can also be used. Here, it is formed by applying a thermal polymerization type polyimide and baking it.
[0248]
Silicon nitride is formed by introducing argon, maintaining the substrate temperature at 150 ° C., and a sputtering pressure of about 0.4 Pa. Then, silicon was used as a target, and film formation was performed by introducing nitrogen and hydrogen in addition to argon. In the case of silicon nitride oxide, argon is introduced, the substrate temperature is kept at 150 ° C., and film formation is performed at a sputtering pressure of about 0.4 Pa. Then, silicon was used as a target, and a film was formed by introducing nitrogen, nitric oxide and hydrogen in addition to argon. Note that silicon oxide may be used as a target.
[0249]
The film thickness of the barrier film is desirably in the range of 50 nm to 3 μm. Here, silicon nitride was formed to a thickness of 1 μm.
[0250]
Note that the method for forming the barrier film is not limited to sputtering, but can be set as appropriate by the practitioner. For example, the film may be formed using an LPCVD method, a plasma CVD method, or the like.
[0251]
The thickness of the stress relaxation film is desirably in the range of 200 nm to 2 μm. Here, a polyimide film was formed to a thickness of 1 μm.
[0252]
By applying the plastic substrate provided with the sealing film of this embodiment as the support 608 or transfer body 610 in Embodiment 6 or the base material 708 or transfer body 710 in Embodiment 7, the EL element is completely removed from the atmosphere. Can be cut off from. Thereby, the deterioration of the organic light emitting material due to oxidation can be suppressed almost completely, and the reliability of the EL element can be greatly improved.
[0253]
[Example 9]
The structure of a module having an EL element obtained in Example 6 or Example 7, that is, a so-called EL module will be described with reference to a top view of FIG. The transfer body 610 in Example 7 or the transfer body 710 in Example 8 corresponds to the film substrate 900.
[0254]
FIG. 16A is a top view illustrating a so-called EL module having an EL element, and FIG. 16B is a cross-sectional view taken along line AA ′ in FIG. A pixel portion 902, a source side driver circuit 901, and a gate side driver circuit 903 are formed on a flexible film substrate 900 (eg, a plastic substrate). These pixel portions and driving circuits can be obtained according to the above embodiment. Reference numeral 918 denotes a sealing material, and 919 denotes a DLC film. The pixel portion and the driving circuit portion are covered with a sealing material 918, and the sealing material is covered with a protective film 919. Further, it is sealed with a cover material 920 using an adhesive. The shape of the cover material 920 and the shape of the support are not particularly limited, and the cover material 920 may have a flat surface, a curved surface, a bendable shape, or a film shape. In order to withstand deformation due to heat or external force, the cover material 920 is preferably made of the same material as the film substrate 900, for example, a plastic substrate, and is processed into a concave shape (depth of 3 to 10 μm) shown in FIG. Use. Further, it is desirable to form a recess (depth 50 to 200 μm) where the desiccant 921 can be installed by processing. In addition, when manufacturing an EL module by multi-chamfering, after bonding the substrate and the cover material, the CO ₂ You may cut | disconnect so that an end surface may correspond using a laser etc.
[0255]
Although not shown here, in order to prevent the background from being reflected due to the reflection of the metal layer used (here, the cathode or the like), circularly polarized light called a circularly polarizing plate made of a phase difference plate (λ / 4 plate) or a polarizing plate is used. Means may be provided on the substrate 900.
[0256]
Reference numeral 908 denotes wiring for transmitting signals input to the source side driver circuit 901 and the gate side driver circuit 903, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 909 serving as an external input terminal. The light emitting device of this embodiment may be digitally driven or analogly driven, and the video signal may be a digital signal or an analog signal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto. In addition, it is possible to form a complicated integrated circuit (memory, CPU, controller, D / A converter, etc.) on the same substrate as these pixel portions and drive circuits, but it is difficult to manufacture with a small number of masks. is there. Therefore, it is preferable to mount an IC chip including a memory, a CPU, a controller, a D / A converter, and the like by a COG (chip on glass) method, a TAB (tape automated bonding) method, or a wire bonding method.
[0257]
Next, a cross-sectional structure is described with reference to FIG. An insulating film 910 is provided over the film substrate 900 via an adhesive layer, and a pixel portion 902 and a gate side driving circuit 903 are formed above the insulating film 910. The pixel portion 902 includes a current control TFT 911 and its drain. A plurality of pixels including a pixel electrode 912 electrically connected to the pixel electrode 912 are formed. Note that, after the layer to be peeled formed on the substrate is peeled according to any one of Embodiments 1 to 4, the film substrate 900 is attached with an adhesive layer. The gate side driver circuit 903 is formed using a CMOS circuit in which an n-channel TFT 913 and a p-channel TFT 914 are combined.
[0258]
These TFTs (including 911, 913, and 914) may be manufactured according to the n-channel TFT 201 of the first embodiment and the p-channel TFT 202 of the first embodiment.
[0259]
The insulating film provided between the TFT and the EL element not only blocks the diffusion of impurity ions such as alkali metal ions and alkaline earth metal ions, but also actively impurities such as alkali metal ions and alkaline earth metal ions. Materials that adsorb ions are preferred, and materials that can withstand subsequent process temperatures are suitable. An example of a material that meets these conditions is a silicon nitride film containing a large amount of fluorine. The concentration of fluorine contained in the silicon nitride film is 1 × 10 ¹⁹ / Cm ^Three As described above, the fluorine composition ratio in the silicon nitride film is preferably 1 to 5%. Fluorine in the silicon nitride film is combined with alkali metal ions, alkaline earth metal ions, etc., and is adsorbed in the film. As another example, an organic resin film containing fine particles made of an antimony (Sb) compound, a tin (Sn) compound, or an indium (In) compound that adsorbs alkali metal ions, alkaline earth metal ions, etc., for example, antimony pentoxide Fine particles (Sb ₂ O _Five ・ NH ₂ An organic resin film containing O) is also included. This organic resin film contains fine particles having an average particle diameter of 10 to 20 nm and has a very high light transmittance. The antimony compound represented by the antimony pentoxide fine particles easily adsorbs impurity ions such as alkali metal ions and alkaline earth metal ions.
[0260]
As another material of the insulating film provided between the active layer of the TFT and the EL element, AlN _X O _Y You may use the layer shown by these. A sputtering method is used, for example, an aluminum nitride (AlN) target, and an aluminum nitride oxide layer (AlN) obtained by forming a film in an atmosphere in which argon gas, nitrogen gas, and oxygen gas are mixed. _X O _Y Is a film containing 2.5 atm% to 47.5 atm% of nitrogen, in addition to the effect of blocking moisture and oxygen, has a high thermal conductivity and a heat dissipation effect, and further has a permeability. It has the feature that the light property is very high. In addition, impurities such as alkali metals and alkaline earth metals can be prevented from entering the active layer of the TFT.
[0261]
In particular, a silicon nitride film formed using an RF sputtering apparatus and using a silicon target is suitable as a passivation film for an interlayer insulating film made of an organic resin film. Since the silicon nitride film can suppress degassing of the organic resin film and can also block moisture and oxygen, occurrence of defects called shrinking of the organic compound layer can be suppressed.
[0262]
The pixel electrode 912 functions as an anode of the EL element. A bank 915 is formed on both ends of the pixel electrode 912, and an EL layer 916 and a cathode 917 of a light emitting element are formed on the pixel electrode 912. The bank 915 can be obtained by patterning an inorganic insulating film or an organic insulating film, and a curved surface having a curvature is formed at the upper end portion or the lower end portion of the bank 915 in order to improve the coverage. It is preferable. For example, when positive photosensitive acrylic is used as the material of the bank 915, it is preferable that only the upper end portion of the bank 915 has a curved surface having a curvature radius (0.2 μm to 3 μm). As the bank 915, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.
[0263]
As the EL layer 916, an EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular organic EL material or a high molecular organic EL material may be used. In addition, a thin film made of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film made of a light emitting material (phosphorescence) that emits light (phosphorescence) by triplet excitation can be used as the EL layer. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0264]
The cathode 917 also functions as a wiring common to all pixels, and is electrically connected to the FPC 909 via the connection wiring 908. Further, all elements included in the pixel portion 902 and the gate side driver circuit 903 are covered with a cathode 917, a sealant 918, and a protective film 919.
[0265]
Note that as the sealant 918, a material that is as transparent or translucent as possible to visible light is preferably used. Further, the sealant 918 is desirably a material that does not transmit moisture and oxygen as much as possible.
[0266]
Further, after the light emitting element is completely covered with the sealant 918, it is preferable to provide a protective film 919 made of a DLC film or the like on the surface (exposed surface) of the sealant 918 as shown in FIG. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to pay attention so that a protective film is not formed on the portion where the external input terminal (FPC) is provided. The protective film may be prevented from being formed using a mask, or the protective film may be prevented from being formed by covering the external input terminal portion with a tape such as a masking tape used in a CVD apparatus.
[0267]
By encapsulating the light emitting element with the sealing material 918 and the protective film with the structure as described above, the light emitting element can be completely shut off from the outside, and a substance that promotes deterioration due to oxidation of the EL layer such as moisture or oxygen from the outside. Can be prevented from entering. In addition, if a film having thermal conductivity (such as an AlON film or an AlN film) is used as the protective film, heat generated when driven can be dissipated. Therefore, a highly reliable light-emitting device can be obtained.
[0268]
Alternatively, the pixel electrode may be a cathode, and an EL layer and an anode may be stacked to emit light in the direction opposite to that in FIG. An example is shown in FIG. Since the top view is the same, it is omitted.
[0269]
The cross-sectional structure shown in FIG. 17 will be described below. A plastic substrate is used as the film substrate 1000. Note that according to any one of Embodiments 1 to 4, after the layer to be peeled formed on the substrate is peeled off, the film substrate 1000 is attached with an adhesive layer. An insulating film 1010 is provided over the film substrate 1000, and a pixel portion 1002 and a gate side driving circuit 1003 are formed above the insulating film 1010. The pixel portion 1002 is electrically connected to the current control TFT 1011 and its drain. The pixel electrode 1012 is formed by a plurality of pixels. The gate side driver circuit 1003 is formed using a CMOS circuit in which an n-channel TFT 1013 and a p-channel TFT 1014 are combined.
[0270]
The pixel electrode 1012 functions as a cathode of the light emitting element. A bank 1015 is formed at both ends of the pixel electrode 1012, and an EL layer 1016 and an anode 1017 of a light emitting element are formed on the pixel electrode 1012.
[0271]
The anode 1017 also functions as a wiring common to all pixels, and is electrically connected to the FPC 1009 through the connection wiring 1008. Further, all elements included in the pixel portion 1002 and the gate side driver circuit 1003 are covered with an anode 1017, a sealant 1018, and a protective film 1019 made of DLC or the like. Further, the cover material 1021 and the substrate 1000 were bonded together with an adhesive. Further, the cover material is provided with a recess, and a desiccant 1021 is provided.
[0272]
Note that as the sealant 1018, it is preferable to use a material that is as transparent or translucent as possible to visible light. The sealing material 1018 is desirably a material that does not transmit moisture and oxygen as much as possible.
[0273]
In FIG. 17, since the pixel electrode is a cathode and the EL layer and the anode are stacked, the light emission direction is the direction of the arrow shown in FIG.
[0274]
Although not shown here, a circularly polarizing plate made of a retardation plate (λ / 4 plate) or a polarizing plate is used in order to prevent the background from being reflected by the reflection of the metal layer used (here, the pixel electrode serving as the cathode). May be provided on the cover material 1020.
[0275]
In this embodiment, a TFT with high electrical characteristics and high reliability obtained in Embodiment 1 is used, so that a light-emitting element with higher reliability than a conventional element can be formed. In addition, a high-performance electric appliance can be obtained by using a light-emitting device having such a light-emitting element as a display portion.
[0276]
Note that this embodiment can be freely combined with Embodiment 1, Embodiment 7, Embodiment 8, or Embodiment 9.
[0277]
[Example 10]
By implementing the present invention, various modules (active matrix liquid crystal module, passive liquid crystal module, active matrix EL module, passive EL module, active matrix EC module) can be completed. That is, by implementing the present invention, all electronic devices incorporating them are completed.
[0278]
Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.
[0279]
FIG. 18A shows a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like.
[0280]
FIG. 18B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like.
[0281]
FIG. 18C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like.
[0282]
FIG. 18D shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.
[0283]
FIG. 18E shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like.
[0284]
FIG. 19A shows a cellular phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, an image input portion (CCD, image sensor, etc.) 2907, and the like.
[0285]
FIG. 19B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like.
[0286]
FIG. 19C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.
[0287]
Incidentally, the display shown in FIG. 19C is a medium or small size display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate having a side of 1 m and perform mass production by performing multiple chamfering.
[0288]
As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-9.
[0289]
【The invention's effect】
Since the present invention peels from the substrate by physical means, the reliability of the element can be improved without damage to the semiconductor layer.
[0290]
Further, according to the present invention, not only the layer to be peeled having a small area but also the layer to be peeled having a large area can be peeled over the entire surface with a high yield.
[0291]
In addition, the present invention is a process suitable for mass production because it can be easily peeled off by physical means, for example, peeled off by a human hand. Further, in the case where a manufacturing apparatus for peeling off a layer to be peeled is manufactured in mass production, a large manufacturing apparatus can be manufactured at low cost.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating Embodiment 1;
FIG. 2 is a diagram illustrating Embodiment 2;
FIG. 3 is a diagram illustrating an experiment.
4 is a diagram illustrating Embodiment 3. FIG.
FIG. 5 is a diagram for explaining a fourth embodiment;
FIGS. 6A and 6B are diagrams illustrating a manufacturing process of an active matrix substrate. FIGS.
FIGS. 7A and 7B are diagrams illustrating a manufacturing process of an active matrix substrate. FIGS.
FIG. 8 shows an active matrix substrate.
9 is a diagram illustrating Example 2. FIG.
10 is a diagram illustrating Example 3. FIG.
FIG. 11 is a diagram for explaining Example 4;
12 is a diagram illustrating Example 5. FIG.
13 is a diagram for explaining Example 6. FIG.
14 is a diagram illustrating Example 7. FIG.
15 is a diagram for explaining an eighth embodiment. FIG.
16 is a diagram illustrating Example 9. FIG.
FIG. 17 is a diagram illustrating Example 9.
FIG 18 illustrates an example of an electronic device.
FIG 19 illustrates an example of an electronic device.
FIG. 20 is a cross-sectional TEM photograph and schematic diagram of a partially peeled boundary.
FIG. 21 is a graph showing a TXRF measurement result on the surface of a peeled silicon oxide film.
FIG. 22 is a graph showing TXRF measurement results on the surface of a W film formed on a quartz substrate. (reference)
FIG. 23 is a graph showing TXRF measurement results on the surface of a quartz substrate. (reference)

Claims (16)

Forming a titanium nitride layer on a glass substrate;
Forming a silicon oxide layer on the titanium nitride layer;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
After bonding a support to the element, a device for peeling the element from the glass substrate by a human hand or the element is used to form an interface within the silicon oxide layer or the interface between the titanium nitride layer and the silicon oxide layer. Peeling off at
A method for manufacturing a semiconductor device, wherein a transfer member is bonded to the silicon oxide layer, and the element is sandwiched between the support and the transfer member. Forming a titanium nitride layer on a glass substrate;
Forming a granular metal oxide material on the titanium nitride layer;
Forming a silicon oxide layer covering the granular metal oxide material;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
After bonding a support to the element, a device for peeling the element from the glass substrate by a human hand or the element is used to form an interface within the silicon oxide layer or the interface between the titanium nitride layer and the silicon oxide layer. Peeling off at
A method for manufacturing a semiconductor device, wherein a transfer member is bonded to the silicon oxide layer, and the element is sandwiched between the support and the transfer member. Forming a tungsten nitride layer on a glass substrate;
Forming a silicon oxide layer on the tungsten nitride layer;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
After bonding a support to the element, a device for peeling the element from a human hand or the element from the glass substrate is used , or the interface between the tungsten nitride layer and the silicon oxide layer in the silicon oxide layer. Peeling off at
A method for manufacturing a semiconductor device, wherein a transfer member is bonded to the silicon oxide layer, and the element is sandwiched between the support and the transfer member. Forming a tungsten nitride layer on a glass substrate;
Forming a granular metal oxide material on the tungsten nitride layer;
Forming a silicon oxide layer covering the granular metal oxide material;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
After bonding a support to the element, a device for peeling the element from a human hand or the element from the glass substrate is used , or the interface between the tungsten nitride layer and the silicon oxide layer in the silicon oxide layer. Peeling off at
A method for manufacturing a semiconductor device, wherein a transfer member is bonded to the silicon oxide layer, and the element is sandwiched between the support and the transfer member. Forming a tungsten layer on the glass substrate,
Forming a silicon oxide layer on the tungsten layer;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
After bonding a support to the element, a device for peeling the element from a human hand or the element from the glass substrate can be used in the silicon oxide layer or at the interface between the tungsten layer and the silicon oxide layer. Exfoliate,
A method for manufacturing a semiconductor device, wherein a transfer member is bonded to the silicon oxide layer, and the element is sandwiched between the support and the transfer member. Forming a tungsten layer on the glass substrate,
Forming a granular metal oxide material on the tungsten layer;
Forming a silicon oxide layer covering the granular metal oxide material;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
After bonding a support to the element, a device for peeling the element from a human hand or the element from the glass substrate can be used in the silicon oxide layer or at the interface between the tungsten layer and the silicon oxide layer. Exfoliate,
A method for manufacturing a semiconductor device, wherein a transfer member is bonded to the silicon oxide layer, and the element is sandwiched between the support and the transfer member.   7. The method for manufacturing a semiconductor device according to claim 2, 4 or 6, wherein ITO, indium zinc oxide alloy, or zinc oxide is used as the metal oxide material.   8. The method for manufacturing a semiconductor device according to claim 1, wherein the support is a substrate made of plastic, glass, metal, or ceramics.   9. The method for manufacturing a semiconductor device according to claim 1, wherein the transfer body is a substrate made of plastic, glass, metal, or ceramics.   8. The method according to claim 1, wherein the support body and the transfer body are film-like plastic substrates, respectively, and a first insulating film and a second insulating film are formed on the support body and the transfer body. Each of the second insulating films sandwiched between the first insulating film and the third insulating film includes the first insulating film and the third insulating film. A method for manufacturing a semiconductor device, wherein a film stress is smaller than that of a film. In any one of claims 1 to 10, wherein the support is a counter substrate facing the transfer member, wherein the element has a pixel electrode, the liquid crystal between the pixel electrode and the opposing substrate A method for manufacturing a semiconductor device, which is filled with a material. Forming a titanium nitride layer on a glass substrate;
Forming a silicon oxide layer on the titanium nitride layer;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
The device is peeled off in the silicon oxide layer or at the interface between the titanium nitride layer and the silicon oxide layer by using a human hand or a device for peeling the device from the glass substrate,
Bonding a first transfer body to the silicon oxide layer;
A method for manufacturing a semiconductor device, comprising: attaching a second transfer member to the element; and sandwiching the element between the first transfer member and the second transfer member. Forming a tungsten nitride layer on a glass substrate;
Forming a silicon oxide layer on the tungsten nitride layer;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
The device is peeled off in the silicon oxide layer or at the interface between the tungsten nitride layer and the silicon oxide layer by using a human hand or a device for peeling the device from the glass substrate,
Bonding a first transfer body to the silicon oxide layer;
A method for manufacturing a semiconductor device, comprising: attaching a second transfer member to the element; and sandwiching the element between the first transfer member and the second transfer member. Forming a tungsten layer on the glass substrate,
Forming a silicon oxide layer on the tungsten layer;
Forming an insulating layer on the silicon oxide layer;
Forming an element on the insulating layer;
The device is peeled off in the silicon oxide layer or at the interface between the tungsten layer and the silicon oxide layer by using a human hand or a device for peeling the device from the glass substrate,
Bonding a first transfer body to the silicon oxide layer;
A method for manufacturing a semiconductor device, comprising: attaching a second transfer member to the element; and sandwiching the element between the first transfer member and the second transfer member. In any one of claims 1 to 14, wherein the device is a method for manufacturing a semiconductor device which is a thin film transistor. 16. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is a stacked layer of silicon oxynitride films.

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