JPS607149A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To implement longitudinal wiring, by providing a deep hole or a through hole, which is deeper than functional elements or the wirings, at a part where the functional elements or the wiring is not formed, on a semiconductor substrate, in the surface of which the functional elements and the wiring are formed. CONSTITUTION:In the surface of a semiconductor substrate 1, functional elements 5, 6 and 6' are formed. A deep hole 2 or a through hole, which is deeper than the elements 5, 6 and 6' are provided at a part other than the elements. An insulating wall 9 is formed on the hole 2. Then a conductive material 8 is formed at least on the film 9. By using a conductive material, a flat wiring 10, which connects the elements 5, 6 and 6' and a longitudinal wiring or between said elements and other functional elements, is formed. Since the hole 2, wherein metal for wiring is embedded, is provided on the substrate 1, the longitudinal wiring, which electrically connects both surfaces of the semiconductor substrate or electrically connects the layers, can be provided.

Description

[Detailed description of the invention] The present invention relates to transistors, diodes, and resistors.

The present invention relates to a method of manufacturing a semiconductor device on which functional elements such as capacitors and wiring connecting these elements are mounted. More specifically, the present invention relates to a method of providing a hole filled with metal for wiring in a semiconductor substrate used in the semiconductor device.

In conventional semiconductor integrated circuits, functional elements are arranged in a plane on one (1) surface of a semiconductor substrate, and wiring is performed between each functional element to construct a desired system or to achieve a desired operational function. was satisfied.

However, in order to make these integrated circuits larger and more functional, it is necessary to expand from the conventional planar arrangement to a three-dimensional arrangement. For example, if a sensor for detecting light, pressure, temperature, etc. is provided on one side of a semiconductor substrate, and a circuit for signal processing of the sensor output is provided on the other side, a monolithic
Miniaturization and multifunctionalization of sensor integrated circuits, etc. are achieved. Another example is an integrated circuit structure in which a plurality of conventional semiconductor integrated circuits are stacked one on top of the other. Such an integrated circuit not only provides high integration, but also provides excellent performance such as increased signal processing capacity, increased signal processing speed, and multiple functions.

In order to realize these integrated circuits, vertical wiring is required to electrically connect both sides of a semiconductor substrate or to electrically connect each layer.

The present invention provides (2) a method for forming holes in a semiconductor substrate used for an integrated circuit to realize the above-mentioned vertical wiring.

According to the present invention, a hole or a through hole deeper than the depth of the element or wiring is provided in a portion of a semiconductor substrate having functional elements and wiring formed on the surface where the element or wiring is not provided, and an inner wall of the hole or through hole is provided. There is obtained a method for manufacturing a semiconductor device characterized in that an insulating film is formed on the surface of the insulating film, and a conductive material is formed on at least the surface of the insulating film.

Hereinafter, the present invention will be explained in detail using the drawings.

1 to 5 show the flow of the manufacturing process according to the present invention. FIG. 1 is a cross-sectional view of a portion of an MO8 integrated circuit manufactured by a known manufacturing method. 1 is a semiconductor substrate made of silicon or the like; 3 is a first insulating layer made of silicon dioxide or the like forming an element isolation region; 5 is a gate electrode of an MO8 field effect transistor (MOSFET) formed of conductive polysilicon or the like; 6 and 6'
is the source or drain of the MOSFET formed of a low resistance diffusion layer having conductivity opposite to that of the semiconductor substrate 1;
is a gate insulating film (3) made of silicon dioxide or the like. 4 is a second insulating layer made of silicon dioxide or the like that protects the MOSFET and the like. Using the structure shown in FIG. 1, if a portion of the second insulating layer N4 and the first insulating layer 3 are sequentially opened, and then a portion of the semiconductor substrate 1 in the opening is removed,
A hole 2 as shown in FIG. 2 is formed. The depth of this hole 2 is deeper than the source and drain of the MO8'F"ET. As an example of a method for forming the opening, when the insulating layers 3 and 4 are made of silicon dioxide, a photolithography patterned by photolithography is used. Examples of methods include wet etching using phosphoric acid or the like using a resist or the like as a mask, or dry etching using carbon tetrachloride gas.An example of a method for removing the semiconductor substrate 1 from the opening is the method described in the above-mentioned 1. Using the second insulating layer as a mask, wet etching is performed using a mixed solution of 7-methic acid, nitric acid, and acetic acid, or by carbon tetrachloride gas using the photoresist or the first and second insulating layers as a mask. One method is dry etching.

Next, as shown in FIG. 3, an insulating film 9 made of silicon dioxide or the like is formed on the side and bottom surfaces of the hole 2. Insulation (4) The film 9 can be formed using a thermal oxidation method, a method in which thermal oxidation is carried out simultaneously with intrusion oxidation, which is a process for controlling the depth of the low-resistance diffusion layer, or a chemical vapor deposition method using silicon dioxide, etc. (CVD method) is used. Thereafter, as shown in FIG. 4, a conductive material 8 such as aluminum is filled into the hole 2 covered with the insulating film 9. An example of this is the selective etching of conductive materials. In this method, first, a photoresist or the like is spin-coated on a conductive material such as aluminum that is thickly formed over the entire surface using a sputtering method or the like. As a result, the film thickness of the photoresist in the hole 2 portion becomes thicker than in other portions. Therefore, if the photoresist is uniformly dry-etched, the photoresist in the hole 2 portion remains and the photoresist in other portions is removed.

Finally, by etching the conductive material using the remaining photoresist as a mask, the conductive material 8 is etched inside the hole 2.
can be embedded. In addition to this, it is also possible to leave the conductive material only in the holes 2 by using ordinary photo-etching techniques. In this case, depending on the size of the hole (5), the conductive material may be formed only on the side and bottom surfaces of hole 2, and hole 2 may not be completely filled. Functionality is satisfied.

Furthermore, as shown in FIG. 5, the source of the MOSFET.

A contact hole is formed to electrically connect the drain or gate to a planar wiring to be described later, and a conductive material is used to connect the MO8FET and the vertical wiring or the MO8F.
Planar wiring 10 connecting ET and other functional elements is formed. As an example of a method of opening a contact hole, 4
If and 7 are silicon dioxide, for example, a method of etching with a hydrofluoric acid-based etching solution using a photoresist patterned by photolithography as a mask is used. In addition, as an example of a method for forming the planar wiring 10, a conductive material such as aluminum formed by a sputtering method or the like is heated using phosphoric acid using a photoresist patterned using a photolithography technique as a mask. A method of etching is used.

After completing the above steps, as shown in FIG. 6, the semiconductor substrate 1 made of silicon or the like is removed from the back surface to form a structure in which a hole 2 made of an insulating film (6) 9 and a conductive material 8 protrudes. At this time, in order to maintain the strength of the thinned substrate, if necessary, a support substrate such as a sapphire substrate is attached to the surface of the structure shown in FIG. 5 using wax or adhesive. Examples of substrate removal methods include wet etching using a mixed solution of hydronic acid, nitric acid, acetic acid, etc., polishing using an ammonia-based solution, or a combination thereof. Furthermore, as shown in FIG. 7, the insulating film 9 made of silicon dioxide or the like on the bottom surface of the hole 2 is removed using a hydrofluoric acid-based etching solution. As a result, a vertical wiring made of the conductive material 8 is formed which penetrates the front and back sides of the thinned semiconductor substrate 1 and is insulated from the semiconductor substrate 1 by the insulating film 9. In the process of forming the hole 2 in FIG. 2, if the hole is made into a through hole by punching the hole using an ultrasonic drill or a laser drill, the steps after the etching step from the back side of the semiconductor substrate 1 can be completed. The structure shown in FIG. 7 can be obtained without going through the process.

As one application example of the present invention, FIG. 8 shows a schematic diagram (7) of an integrated circuit in which functional elements and the like are integrated on the front and back sides of a semiconductor substrate. 21 is a semiconductor substrate, and 22 and 23 are a first active layer and a second active layer, respectively, of functional elements such as transistors, diodes, capacitors, and resistors, or circuits containing a plurality of these. 24 is a vertical wiring made of a conductive material such as aluminum, and 25 is an insulating film that insulates the vertical wiring and the semiconductor substrate 21. Reference numerals 26 and 27 denote a first planar wiring and a second planar wiring made of aluminum or the like, which connect 22 and 24 and 23 and 24, respectively. As shown in FIG. 8, the first active layer and the second active layer are electrically connected through wirings 26, 24, and 27. That is, since it is equivalent to two integrated circuits being formed on one semiconductor substrate, the packaging density is twice as high as that of conventional integrated circuits. Another application example of FIG. 8 is a structure in which a sensor for detecting light, pressure, humidity, etc. is provided in the first active layer 22, and a signal processing circuit for processing this detection signal is provided in the second active layer 423. be. For example, in the case of a humidity sensor, the conductivity (8) of a pair of facing electrodes made of polysilicon, etc., and the styrene/sodium sulfonate filled between these electrodes changes depending on the humidity. A configuration may be considered in which a polymer material is used as a first active layer and a signal processing circuit that detects and amplifies the change in conductivity is used as a second active layer. In the humidity sensor integrated circuit having such a structure, the semiconductor substrate 21 acts as a moisture prevention wall.
The signal processing circuit is not subject to fluctuation or deterioration due to humidity. Not only for humidity sensors but also for other sensors, the sensor integrated circuit with the structure shown in Figure 8 is completely unaffected by the object to be detected (light, pressure, humidity, etc.) and its signal processing circuit is mounted on the same semiconductor substrate. Since it can be formed into a large size, it can be made smaller and multifunctional.

As another example of application of the present invention, FIG. 9 shows an integrated circuit having a structure in which a semiconductor device formed as in the above embodiment and a semiconductor integrated circuit formed by a conventional method are superimposed.

101 is the first layer semiconductor substrate, 102 is MO8FE
T (7) Gate insulating film, 103 is the gate electrode of MOSFET, 1 (14, 105 is the source of MO8FB'r,
Or it's a drain. 106 and 107 are each 1
This is the first layer of planar wiring connected to 05.104.

120 is an insulating (9) layer that insulates 106, 107 and 101. On the other hand, 201 is a second layer semiconductor substrate, 20
2 is the gate insulating film of MO8F'ET, 203 is MOS-
Gate electrodes 204 and 205 of the FET are the source or drain of the MOSFET. 206 and 207 are second layer planar wirings connected to 205 and 204, respectively. Further, 220 is an insulating layer that insulates 206, 207, and 201. Further, 210 is a vertical wiring made of conductive material;
211 is an insulating film that insulates 210 and 201. 10
Reference numeral 8 denotes a metal bump made of gold or the like, which is provided to facilitate adhesion between 210 and 108. Also, 110 is 102.
103°104, 105.106 and 107 are protected,
It is a thin film made of diamond or the like that provides insulation between these and 201 and also functions as a heat dissipator. The second layer semiconductor substrate 2 formed through the manufacturing process from FIG. 1 to FIG. 7
01 is aligned with the semiconductor substrate 101,
Both are bonded using a method such as diffusion welding.

For example, if aluminum is used for 107 and 210 and gold is used for the metal bump 108, if 101 and 201 are heated to 300°C and pressed together with a pressure of about 60 kg/cm or more, the vicinity of the boundary between 210 and 107 will be adhesively welded. Been,
(10) The first layer and the second layer are adhered. As shown in FIG. 7, the source or drain 104 of the first layer MOSFET and the source or drain 204 of the second layer MOSFET are electrically connected, and a three-dimensional M
It has an O8FET arrangement structure.

For example, the first layer MOS F'E'] is an n-channel MO8-FBT, and the second layer is a p-channel MO8FE.
Let it be T. Further, by connecting 103 and 203 with vertical wiring manufactured in the same process as 210, a CMOS inverter circuit can be realized. Furthermore, on top of the second layer, the third and fourth layers were manufactured in almost the same process as the 2Nth layer.

By overlapping ..., large-scale integrated circuits can be realized.

In the above description of the present invention from FIGS. 1 to 7, the already known method of manufacturing an MO8FET integrated circuit was used as an example. The present invention can also be applied to circuits. Moreover, the application examples of the present invention are also only examples, and the invention is not limited to these applications. Furthermore, in the above embodiment,
Although a semiconductor substrate uniformly doped with impurities is used, the present invention is not limited to this. For example, if a functional element is formed on a semiconductor film epitaxially formed on a low-resistance substrate, and one type is formed so as to reach the substrate, the substrate can be easily removed.

[Brief explanation of drawings]

1 to 5 are schematic cross-sectional views for explaining an example of the flow of the manufacturing process according to the present invention. 1 is a semiconductor substrate, 2 is a hole formed on the semiconductor substrate, 3
and 3' are the first insulating layers. 5. 6, 6' and 7 are the gate electrode, source or drain, and gate insulating film of the MOSFET, respectively. 4 is a second insulating film, 8 is a conductive material, 9 is an insulating layer, and 10 is a planar wiring. 6 and 7 are schematic cross-sectional views for explaining an example of a method for forming vertical wiring that penetrates the front and back sides of the semiconductor substrate 1. FIG. FIG. 8 is a schematic cross-sectional view of the first application example of the present invention. FIG. 9 is a schematic cross-sectional view of a second application example of the present invention. 101 is the first layer semiconductor substrate, 102, 103゜10
4 and 105 are a gate insulating film, a gate electrode, a source, a drain, and 1 which constitute the first layer MOSFET, respectively.
06.107 is the first #th planar wiring, and 121 is an insulating layer between the first layer of the semiconductor substrate and the planar wiring. Further, 201 is a second layer semiconductor substrate, 202, 203
゜204 and 205 are the gate insulating film and gate electrode, 206 and 207, respectively, which constitute the second # MOSFET.
221 is a second layer of planar wiring, and 221 is an insulating layer that insulates the second layer of the semiconductor substrate and the planar wiring. 210 is a vertical wiring insulated from 201 by an insulation M211. 10B is a metal bump, and 110 is a thin film filled between layers. (13) Figure 1 O 2 Figure 3 Figure 4 Figure 5 Figure 6 Off diagram o l. Figure 8 Figure 9

Claims (1)

[Claims] A hole or through-hole deeper than the depth of the element or wiring is provided in a part of the semiconductor substrate on which functional elements and wiring are formed, and where the element or wiring is not present, and an insulating film is formed on the inner wall of the hole or through-hole. A method of manufacturing a semiconductor device, comprising forming a conductive material on at least the surface of the insulating film.